Follow these steps to compile the testbench for simulation and run the chaining DMA testbench.
1. Start your simulation tool. This example uses the ModelSim®software.
2. From the ModelSim transcript window, in the testbench directory (./example_design/altera_pcie_<device>_
hip_ast/<variant>/testbench/mentor) type the following commands:
a. do msim_setup.tcl
b. h (This is the ModelSim help command.)
c. ld_debug(This command compiles all design files and elaborates the top-level design without any optimization.)
d. run -all
The following example shows a partial transcript from a successful simulation. As this transcript illustrates, the simulation includes the following stages:
• Link training
• Configuration
• DMA reads and writes
• Root Port to Endpoint memory reads and writes
Simulating the Example Design 2-13 UG-01097_avst
December 2013
Excerpts from Transcript of Successful Simulation Run
# INFO: 464 ns Completed initial configuration of Root Port.
# INFO: 3661 ns RP LTSSM State: DETECT.ACTIVE
# INFO: 3693 ns RP LTSSM State: POLLING.ACTIVE
# INFO: 3905 ns EP LTSSM State: DETECT.ACTIVE
# INFO: 4065 ns EP LTSSM State: POLLING.ACTIVE
# INFO: 6369 ns EP LTSSM State: POLLING.CONFIG
# INFO: 6461 ns RP LTSSM State: POLLING.CONFIG
# INFO: 7741 ns RP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 7969 ns EP LTSSM State: CONFIG.LINKWIDTH.START
# INFO: 8353 ns EP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 8781 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 8781 ns RP LTSSM State: CONFIG.LINKWIDTH.ACCEPT
# INFO: 9537 ns EP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 9857 ns EP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 9933 ns RP LTSSM State: CONFIG.LANENUM.ACCEPT
# INFO: 10189 ns RP LTSSM State: CONFIG.COMPLETE
# INFO: 10689 ns EP LTSSM State: CONFIG.COMPLETE
# INFO: 12109 ns RP LTSSM State: CONFIG.IDLE
# INFO: 13697 ns EP LTSSM State: CONFIG.IDLE
# INFO: 13889 ns EP LTSSM State: L0
# INFO: 13981 ns RP LTSSM State: L0
# INFO: 17800 ns Configuring Bus 001, Device 001, Function 00
# INFO: 17800 ns EP Read Only Configuration Registers:
# INFO: 17800 ns Vendor ID: 1172
# INFO: 17800 ns Device ID: E001
# INFO: 17800 ns Revision ID: 01
# INFO: 17800 ns Class Code: FF0000
# INFO: 17800 ns Subsystem Vendor ID: 1172
# INFO: 17800 ns Subsystem ID: E001
# INFO: 17800 ns Interrupt Pin: INTA# used
# INFO: 20040 ns PCI MSI Capability Register:
# INFO: 20040 ns 64-Bit Address Capable: Supported
# INFO: 20040 ns Messages Requested: 4
# INFO: 31208 ns EP PCI Express Link Status Register (1081):
# INFO: 31208 ns Negotiated Link Width: x8
# INFO: 31208 ns Slot Clock Config: System Reference Clock Used
# INFO: 33481 ns RP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 34321 ns EP LTSSM State: RECOVERY.RCVRLOCK
# INFO: 34961 ns EP LTSSM State: RECOVERY.RCVRCFG
# INFO: 35161 ns RP LTSSM State: RECOVERY.RCVRCFG
# INFO: 36377 ns RP LTSSM State: RECOVERY.IDLE
# INFO: 37457 ns EP LTSSM State: RECOVERY.IDLE
# INFO: 37649 ns EP LTSSM State: L0
# INFO: 37737 ns RP LTSSM State: L0
# INFO: 39944 ns Current Link Speed: 2.5GT/s
# INFO: 58904 ns Completed configuration of Endpoint BARs.
# INFO: 61288 ns TASK:chained_dma_test
UG-01097_avst Simulating the Example Design
2-14 December 2013
# INFO: 8973 ns RP LTSSM State: CONFIG.LANENUM.WAIT
# INFO: 61288 ns TASK:dma_rd_test
# INFO: 61288 ns TASK:dma_set_rd_desc_data
# INFO: 61288 ns TASK:dma_set_msi READ
# INFO: 61288 ns Message Signaled Interrupt Configuration
# INFO: 61288 ns msi_address (RC memory)= 0x07F0
# INFO: 63512 ns msi_control_register = 0x0084
# INFO: 72440 ns msi_expected = 0xB0FC
# INFO: 72440 ns msi_capabilities address = 0x0050
# INFO: 72440 ns multi_message_enable = 0x0002
# INFO: 72440 ns msi_number = 0000
# INFO: 72440 ns msi_traffic_class = 0000
# INFO: 72440 ns TASK:dma_set_header READ
# INFO: 72440 ns Writing Descriptor header
# INFO: 72480 ns data content of the DT header
# INFO: 72480 ns Shared Memory Data Display:
# INFO: 72480 ns Address Data
# INFO: 72480 ns 00000900 00000003 00000000 00000900 CAFEFADE
# INFO: 72480 ns TASK:dma_set_rclast
# INFO: 72480 ns Start READ DMA : RC issues MWr (RCLast=0002)
# INFO: 72509 ns TASK:msi_poll Polling MSI Address:07F0---> Data:FADE
# INFO: 72693 ns TASK:rcmem_poll Polling RC Address0000090C current data (0000FADE) expected data (00000002)
# INFO: 80693 ns TASK:rcmem_poll Polling RC Address0000090C current data (00000000) expected data (00000002)
# INFO: 84749 ns TASK:msi_poll Received DMA Read MSI(0000) :B0FC
# INFO: 84893 ns TASK:rcmem_poll Polling RC Address0000090C
# INFO: 84893 ns TASK:rcmem_poll Received Expected Data (00000002)
# INFO: 84901 ns Completed DMA Read
# INFO: 84901 ns TASK:chained_dma_test
# INFO: 84901 ns DMA: Write
# INFO: 84901 ns TASK:dma_wr_test
# INFO: 84901 ns DMA: Write
# INFO: 84901 ns TASK:dma_set_wr_desc_data
# INFO: 84901 ns TASK:dma_set_msi WRITE
# INFO: 84901 ns Message Signaled Interrupt Configuration
# INFO: 84901 ns msi_address (RC memory)= 0x07F0
# INFO: 87109 ns msi_control_register = 0x00A5
# INFO: 96005 ns msi_expected = 0xB0FD
# INFO: 96005 ns msi_capabilities address = 0x0050
Simulating the Example Design 2-15 UG-01097_avst
December 2013
# INFO: 96005 ns multi_message_enable = 0x0002
# INFO: 96005 ns msi_number = 0001
# INFO: 96005 ns msi_traffic_class = 0000
# INFO: 96005 ns ---
# INFO: 96005 ns TASK:dma_set_header WRITE
# INFO: 96005 ns Writing Descriptor header
# INFO: 96045 ns data content of the DT header
# INFO: 96045 ns Shared Memory Data Display:
# INFO: 96045 ns Address Data
# INFO: 96045 ns 00000800 10100003 00000000 00000800 CAFEFADE
# INFO: 96045 ns TASK:dma_set_rclast
# INFO: 96045 ns Start WRITE DMA : RC issues MWr (RCLast=0002)
# INFO: 96073 ns TASK:msi_poll Polling MSI Address:07F0--->
Data:FADE...
# INFO: 96257 ns TASK:rcmem_poll Polling RC Address0000080C current data (0000FADE) expected data (00000002)
# INFO: 101457 ns TASK:rcmem_poll Polling RC Address0000080C current data (00000000) expected data (00000002)
# INFO: 105177 ns TASK:msi_poll Received DMA Write MSI(0000): B0FD
# INFO: 105257 ns TASK:rcmem_poll Polling RC Address0000080C current data (00000002) expected data (00000002)
# INFO: 105257 ns TASK:rcmem_poll ---> Received Expected Data (00000002)
# INFO: 105265 ns Completed DMA Write
# INFO: 105265 ns TASK:check_dma_data
# INFO: 105265 ns Passed : 0644 identical dwords.
# INFO: 105265 ns TASK:downstream_loop
# INFO: 107897 ns Passed: 0004 same bytes in BFM mem addr 0x00000040 and 0x00000840
# INFO: 110409 ns Passed: 0008 same bytes in BFM mem addr 0x00000040 and 0x00000840
# INFO: 113033 ns Passed: 0012 same bytes in BFM mem addr 0x00000040 and 0x00000840
# INFO: 115665 ns Passed: 0016 same bytes in BFM mem addr 0x00000040 and 0x00000840
# INFO: 118305 ns Passed: 0020 same bytes in BFM mem addr 0x00000040 and 0x00000840
# INFO: 120937 ns Passed: 0024 same bytes in BFM mem addr 0x00000040 and 0x00000840
# INFO: 123577 ns Passed: 0028 same bytes in BFM mem addr 0x00000040 and 0x00000840
# INFO: 126241 ns Passed: 0032 same bytes in BFM mem addr 0x00000040 and 0x00000840
# INFO: 128897 ns Passed: 0036 same bytes in BFM mem addr 0x00000040 and 0x00000840
# INFO: 131545 ns Passed: 0040 same bytes in BFM mem addr 0x00000040 and 0x00000840
# SUCCESS: Simulation stopped due to successful completion!
UG-01097_avst Simulating the Example Design
2-16 December 2013
Interpreting TLPs at the PIPE Interface
To interpret the TLPs at the PIPE interface, disable data scrambling when compiling your design files. By default, data scrambling is enabled during compilation. Complete the following steps to disable scrambling:
1. Go to <project_directory/<variant>/testbench/<variant>_tb/simulation/submodules/
2. Open altpcietb_bfm_top_rp.v.
3. Locate the declaration oftest_in[2:1]. Settest_in[2] = 1andtest_in[1] = 0. Changing test_in[2] = 1disables data scrambling on the PIPE interface.
4. Save altpcietb_bfm_top_rp.v.