Figure 4.9: 3D view of the camera head [1]. The focal plane is subdivided into four identical quadrants. A quadrant is further subdivided into 16 monolithic sensors, each of which is equipped with 8 readout ASICs comprising 64 × 64 pixels
The physical structure and building components of the camera head have been published in [41]. A 3D view of the camera head is shown in figure figure 4.9. Physically, the pixel matrix of 1024 x 1024 has a size of 21 × 21 cm2 and is structured as follows:
• 4 identical quadrants (512× 512 pixels each) • 4 ladders (512 × 128 pixels each) per quadrant • 2 sensors (256× 128 pixels each) per ladder
4.2 Physical Structure of the Detector Head
Figure 4.10: 3D views of the focal plane stack [41]. Left: side view showing the wire bonding to the sensor. Right: cross section of the stack of sensor, ASIC, heat spreader and main board.
• 8 ASICs (64× pixels each) per sensor
The four quadrants can be moved to form a variable central hole through which the unscattered beam can pass without destroying any system components.
The first element in the focal plane are the sensors, which are bump bonded to the sensor. Figure 4.10 shows the focal plane stack: the sensor-ASIC assembly is hosted on a printed circuit board (PCB), the so called Main Board (MB). To carry out the heat generated by the ASICs which peaks during the XFEL burst phase, they are first glued to a Si-heat spreader using Ag-filled epoxy. The heat spreader further is glued to the MB with a hybrid urethane film adhesive. The choice of adhesive is important here because materials with different thermal expansion coefficients are meeting. A low modulus adhesive which stays above the glass transition temperature throughout the operating temperature range needs to be chosen in order to cushion mechanical stress caused by thermal cycling.
The main board is a 20 layer PCB which hosts clock drivers to distribute the 695 MHz ASIC clocks, filters for the sensor bias voltages and decoupling capacitors for the various supply voltages. The ASICs are electrically connected to the MB through the sensor. The sensor extends a little beyond the ASIC IO bump row. On this balcony, wire bond pads are located which serve to connect the sensor operating and bias voltages and fan out to landing pads for the IO bumps of the ASIC. The sensor bias bonds repeats for each ASIC section to form a regular bonding pattern. On the MB side, cavities are carved out to the inner layers of the MB in order to reduce the length of the wire bonds.
Perpendicular to the MB, there are five PCBs, four of which are so-called regulator boards which generate various supply and bias voltages. The fifth is the co called IO board (IOB) hosting an FPGA which generates control signals for the various components on the MB and the ASICs. It further collects the data from 16 ASICs and merges them into four 3.125 Gbit/s streams for the preceding patch panel transceiver.
Due to the large current request and low duty cycle of the signal processing elements in the ASIC, the corresponding supply voltages are only turned on during the XFEL burst phase of ∼600 µs (see also section 5.2). Each regulator board hosts twelve regulators to generate these pulsed supply voltages and clear gate drivers for 4×4096 pixels. Because of the high peak currents and the lack of sufficiently fast
power supplies3, the regulators generating the ASIC supply voltages are supplied by large capacitors. These are charged up to 7 V before the start of the XFEL burst and discharge along the burst. The gap in between the XFEL bursts is used for recharging up to 7 V. They have been sized such that the current requests of the ASIC can be satisfied, for the analog supply of a single ASIC for instance 3.2A are required. The total required capacitance for this purpose sums up to 8 mF per regulator board. The ASIC has sense outputs for all positive and negative supply voltages which return to the according regulators in order to cancel the voltage drops due to trace resistances.
The gate drivers serve to generate the required clear and clear gate pulses for the DEPFET sensor. The high and low levels can be adjusted, allowing for pulse amplitudes of 18.5 V and 10.5V respectively. At the maximum operating frequency of 4.5 MHz, only 50 ns are available to clear the DEPFET internal gate. A sophisticated driver has been developed which uses a push-pull output stage able to source currents of 9 A and sink currents of 4.4 A at the required speed. A transmission line transports these pulses to the sensors and is terminated with a 10 Ω resistor next to the wire bond pad.
The DEPFET bias voltages are brought to the main board via the IOB. Similar to the ASIC supply voltages, the source voltage which supplies the bias current of up to 150 µA per pixel needs to be power cycled. This voltage is generated per sensor (32k pixels), requiring to supply a total current of up to 5 A. The approach to generate them with dedicated regulators has been studied. However, the larger voltage requirement of up to 7 V and larger load current4. The available area is more efficiently connecting an external (slow) standard power supply and using the available area for capacitors. For a single net of the SOURCE voltage, a total of 37 mF could be placed. The energy required during the burst is thus entirely retrieved from the capacitors since the power supply is too slow to recharge them during the burst. This situation causes a droop of the SOURCE voltage along the XFEL burst. For a the maximum SOURCE current of the voltage has thus drooped by 81 mV at the end of the burst. A thorough investigation was conducted that this droop sustains the DEPFET performance.
These five boards (four regulator and one IO board) are all connected to a module interconnect board. This board mainly contains 28 mF of the capacitance for the DEPFET source voltage. A flex cable directly transports the static DEPFET bias voltages and JTAG signals for the ASIC slow control to the main board.