Readout ASIC

Besides the DEPFET sensor, the readout ASIC has the most significant role for the signal quality as it comprises all of the signal processing steps. The DEPFET is configured in drain readout mode, which means that the drain terminal is DC coupled to the ASIC input (figure 4.6, left side). The ASIC consequently has to sink the current needed to bias the DEPFET. A different approach would be the source follower configuration, where a bias resistor needs to be implemented on the sensor and a voltage signal is AC coupled to the DEPFET. AC coupling has the advantage that possible shifts in the threshold voltage of the DEPFET which increase its bias current can be tolerated more easily. The configuration has been studied by the consortium but has been discarded due to worse performance expectations than the drain current readout.

The ASIC input branch of the DEPFET readout mode comprises an adjustable current source which has to account for a possible increase of the DEPFET bias current as the sensor is exposed to large radiation doses in the experiments.2 _{The actual signal current from the DEPFET is directly processed} by a current mode filer (implementation details in section 5.3.2.1). The filter is of time variant nature and implements a trapezoidal weighting function introduced in section 3.4.4, which is the optimum weighting function at the target readout speed [32]. A triangular form would be slightly better but the flattop is required for signal acquisition and settling. The filter is needed to reach the target signal to noise ratio. After filtering, the signal is directly digitized and stored locally. This approach has been adopted to solve the challenge imposed by the fast maximum frame rate of 4.5 MHz. A precise ADC (implementation details in section 5.3.3) is a complex circuit, especially when implemented in a matrix of 4k pixels. The DSSC concept is therefore to digitize to 8bit only, a 9bit mode is possible for slower operating speeds (≤ 2 MHz). Since the system is required to detect single photons while maximizing the dynamic range, the 8bit ADC is optimally exploited if the first photons (linear range) are attributed to single ADC bins. In this attribution scheme, charge sharing effects can not be compensated for but they have shown to be of marginal effect in [33]. For larger signals, the Poisson statistics underlying the signal are exploited. As more and more photons are attributed to single ADC bins through the nonlinear characteristic of the sensor or front-end a quantization error is introduced. The quantization does however not limit the system performance as long as the Poisson noise is dominant (see figure 4.8b).

This attribution scheme poses two very important requirements on the ADC: there must be a mechanism to set the inner bin offset precisely and the non-linearities in the linear region of the system must be very good. Influences of the non-linearities on single photon resolution have been studied in [39]. The signal is Gaussian distributed due to the electronics noise, and must be centered in the ADC bin in order to maximize the probability of proper detection of a single photon and ideally, the bin sizes should be equal. The concept is illustrated in figure 4.8a. Furthermore, the ADC needs a pixel-wise fine gain adjustment mechanism in order to compensate for a gain spread across the DEPFET pixel matrix. The single slope (Wilkinson) ADC is the architecture of choice because the concept scales nicely for a large matrix and both offset and gain adjustment can be implemented conveniently.

2

The ASIC itself does not need to be radiation tolerant because at the foreseen X-ray energies, virtually nothing reaches the sensitive gates in the ASIC.

4.1 Detector System Concept

(a) (b)

Figure 4.7: Attribution of photons to ADC bins [33]. For the first photons (a), the allocation of photons to ADC bins is 1:1 while for larger signals (b), more photons are attibuted per ADC bin due the non-linear characteristic of the DEPFET or MSDD front-end.

(a) The electronics noise is Gaussian and the ADC is be calibrated that the first photons fall in the middle of the ADC bins. At an energy of 1 keV and an (exemplary) electronics noise of 55 e−_{, this results in} a probability of 0.6% to falsely detect 1 photon.

(b) More and more photons are attibuted to single ADC bins as the amount of detected photons increases, increasing the quantization noise. The total noise is however dominated by the Poisson noise of the photon generation process.

Due to the attribution of single photons to single ADC bins and the non-linear system characteristic, calibration of the detector is a challenging task. The ASIC features various gain setting possibilities and the ADC offset must be set very precisely. Calibration is a separate work package, the latest progress has been reported in [40].

After the signal is digitized, it is saved in a local memory (implementation details in section 5.3.4), because the frame rate is too fast to transport a full frame off the ASIC in between two subsequent events. The wish is of course to store all 2700 events generated by the EuXFEL, such a capacity is however out of reach. The initial target capacity of 512 could be excelled, which is one of the results of this thesis. Thorough compression of layouts and the implementation of a memory with minimal overhead have lead to a final capacity of 800 events for the first full size ASIC. The memory is implemented as an SRAM (Static Random Access Memory). A mechanism is implemented in the chip which allows selectively discarding uninteresting events (implementation details in section 5.5.4). For the slowest target frame rate at the EuXFEL of 1 MHz (and fixed burst length of 600 µs), all 600 events can be stored.