Power management techniques to reduce energy consumption have been extensively studied in prior work. The metrics including but not limited to energy, power, Energy Delay Product (EDP) and Energy Delay-squared Product (ED2P) are used in power studies depending on the goals of the work and the type of platform being studied. Energy is often considered the most fundamental of the possible metrics for platforms, ranging from mobile/embedded to data centres and High Performance Computing (HPC)[70]. Energy can be calculated as:
Energy= power×time (2.1)
where, energy(E) is measured in joules(J), power(P) is measured in watts(W), and the execution time of an application time(t) is measured in seconds(s).
Power-management techniques have been employed/studied extensively at various levels, such as logic, architecture, and an OS-level[102].
The techniques used at the logic level include but are not limited to: clock gating — turning off clock signal to unused circuits; half-frequency and half-swing clock —
where both edges of a clock signal are used enabling operation at half the frequency in the former, and in the latter the clock swings for only half of the V ; asynchronous logic — when a clock signal is completely absent and completion signals are used instead.
The techniques used at the architecture level cover various systems: a memory system— in which various sub-techniques are used, such as selective activation of cache hierarchy and memory banking, compression of instruction in memory saving instruction fetch energy[15, 89]; communication system — e.g. Gray code or bus- invert encoding of address on bus[121] or network-no-chip with topology-aware routing or reconfiguration techniques[108]; parallel processing — in which functional units are replicated to allow processing of data in parallel.
The techniques used at the OS level include: power manager — as in Linux and Windows OS, the power manager allows diverse options such as timer to put display, hard drive, or other components to sleep mode; in Linux cpufreq infrastructure handles Central Processing Unit (CPU) frequency scaling[107].
efficiency reasons such as compiler, application, and network. A large amount of research work has been done in this area, and some surveys[11, 16, 28, 99, 100, 129, 130, 134]that cover various topics are recommended to interested readers.
2.3.1
Power Efficiency vs Energy Efficiency
There is distinction between power-efficient and energy-efficient systems. A power- efficient system may not be an energy-efficient system. As an example, a power- efficient system may decrease the clock frequency which in turn saves power, but this affects the execution time of an application running. There comes a time when the execution time of this application increases to a point when overall energy consumed actually increases, rendering system power-efficient but not energy-efficient.
DVFS and Dynamic Power Management (DPM) are two widely used techniques for reducing energy consumption in the processing unit. As name suggests in DVFS, the voltage and/or frequency of a particular component is changed to decrease power consumption at the price of potentially lower performance. The DPM techniques switch the processor/CPU/core to a low-power inactive state as long as possible[11]. In Complementary Metal-Oxide Semiconductor (CMOS) technology, the total power consumption can further be decomposed into static and dynamic compon- ents[141]:
Ptotal= Pstatic+ Pdynamic (2.2)
Where Pstatic represents static power consumption, resulting due to various factors
including—but not limited to—sub-threshold leakage, tunnelling current through gate oxide, and leakage through a reverse-biased p-n junction [120, 129]. Pdynamic
represents dynamic power consumption, resulting due to the activity of logic gates, i.e. charging/discharging of capacitors and temporary current paths between the supply rails. The dynamic power consumption increases with the increase in switching frequency. This is due to the fact that dynamic power consumption occurs only during gate activity. DPM solutions are best suited for decreasing the impact of the static power component, as the static power consumption is always present, even when the circuit is on stand-by. In contrast, the dynamic power consumption is present when there is some activity, and as such, DVFS approaches are more suitable for reducing the dynamic power consumption.
2.3.2
Dynamic Power Consumption
The dynamic power consumption of a core can be calculated as:
Pdynamic= aCV2f (2.3) where a is switching activity factor, i.e. how many transitions occur in a chip, C is physical capacitance, V is supply voltage, and f is clock frequency. Each of these parameters can be used to reduce the dynamic part of power consumption. Power consumption due to the switching-activity factor a can be decreased by using techniques like clock gating, in which clock signal is not sent to idle circuits, e.g. caches. Power consumption due to the physical capacitance C can be reduced by changing low-level design parameters such as transistor sizes and wire lengths. By decreasing the clock frequency f power consumption can be reduced, but as we noted earlier, the energy consumption may or may not improve. Reducing the supply voltage V will also reduce power consumption. This is better than frequency as a small change in voltage will have a big impact on power consumption, although decreasing voltage also requires a decrease in frequency to allow safe operation of the chip.
A change in voltage can change the energy-optimal point of operation for a core. Since core frequency has an approximately linear relationship with supply voltage, and power consumption is approximately quadratic with voltage as can be seen from Equa- tion2.3, this provides a single knob to adjust power consumption and performance.
Since in the context of this thesis we used only DVFS to reduce energy consump- tion, we will focus only the dynamic part of the power consumption in general. As we already noted that voltage change has a big impact on power consumption in comparison to other parameters, our centre of interest lies in DVFS techniques. The DVFS techniques can be subdivided further into offline and online. The distinction is based on when the DVFS decision is made, i.e. statically at compile time (offline) or dynamically at runtime (online). We will visit DVFS again in Chapter7.