The DECstation
3 100
CPU consists of the M I PSR2000
integer processor, theR2010
floating point coprocessor, a nd fou rR 2020
write buffers. The chip set operates at16.67
megahertz.In the DECstation
3100,
theR 2000
chip set runsin " Little End ian" mode. In other words, bits within bytes and words are counted from right to left , and the low-order bit is the rightmost bit in a word. " Little Endian" mode means that the integer data
format of the OECstation
3100
is identical to thei nteger data format of any VAX processor. The floating point data format is compliant with IEEE standards.
The
R 2000
CPU implements the instruction set, processor registers, virtual memory, and interruptsystem as defined by the R 2000 architecture. The CPU maintains the direct-mapped, write-through data cache. Each cache is 64 kilobytes (KB) in capac ity with a 4 -byte l ine size. The tag and data stares of each cache are byte-parity protected, and cache parity errors transparently generate cache misses ro reload the cache from memory.
The R 20 10 floating point coprocessor i mp le ments the I EEE arithmetic functions and coproces sor registers defined by the R 2000 architecture.
The R 2020 write buffer implements a four-stage write bu ffer for the CPU . This write buffer allows the C PU to write to its write-th rough cache without stall ing the CPU as long as the write buffer is not ful l .
Graphics
Graphics on the DECstation 3 100 is implemented in a tightly integrated subsystem. Frame bu ffer mem ory is a region of memory in the processor address space - 256 KB in a monochrome system and 1 M B in a color system. Less than half of the monochrome frame bu ffer and three quarters of the color frame bu ffer are displayed on the workstation monitor. The remaining frame buffer memory may be used for storage of graphics data structures such as fonts. The frame bu ffer memory is not parity protected.
At boot time, the lJLTRIX operating system detects the size of frame bu ffer memory and whether the system is monochrome or color. Because frame bu ffer memory is cacheable and addressable in the same way as the dynamic ran dom access memory (DRAM), the software is able to ach ieve extremely high performance without any special-purpose graphics hardware.
A color plane mask allows processor writes to the color frame bu ffer to a ffect only specific bits of a pixel. This design al lows modi fication of a given plane of the color frame buffer using only write cycles, which i nc reases performance significantly.
The graphics progra mmable cursor supports a 16-hy- 16 pixel, two-plane cursor. The cursor can take two forms : a 1 6-hy- 16 bit pattern or a crosshair whose l i nes may extend to the edges of the visible raster or may be clipped to a programmed region. The cursor in a color system may have up to three colors, and the cursor in a monochrome system may have up to th ree gray-scale values.
Memory
The DECstation 3 100 supports 8MB to 24 M B of byte parity protected memory in 4 M B increments. The memory system includes both the DRAM array and a video random access memory (YRAM) frame buffer. The video frame bu ffer has the same memory access
Dtgitul TeclmicaljourrUll Vol. J No. 2. Spring 199()
Development of the DECstation 3100
characteristics as memory and may be cached if desired. The memory system supports byte, half word, word writes, and word read s.
The memory system control logic is optimized for m inimum memory read latency, at a sl ight cost in memory write latency. On a memory read, the CPU incurs a five-cycle stall in the absence of mem ory refresh contention. The memory system can sustain five-cycle reads, which results in a peak read bandwidth of 13.3MB per second .
Memory writes to an empty write buffer com plete in eight cycles, but do not stall the CPU . Suc cessive memory writes complete at the rate of six cycles, and the CPU stalls whenever the write buffer is ful l . The memory system can sustai n six-cycle writes, which results in a peak write bandwidth of
1 1 . 1 MB per second.
The DRAM and VRA M arrays are implemented with SIMMs. Each DRAM array contains 2 M B of
memory on a double-sided modu le. The VRAM
arrays contain either 1 megabit (Mb) (monochrome) or 8Mb (color) of frame buffer memory on single sided modules.
Ethernet
The Ethernet interface on the DECstation 3 100 con sists of a CMOS controller chip and a 64 KB buffer. The controller chip manages transmission and reception of packets through ring descriptors and packet bu ffers located in the Ethernet bu ffer. The buffer is time-multiplexed between the controller chip and the workstation CPU .
Connection to the Ethernet is by a thick-wire or ThinWire cable. A push-button switch on the rear of the system box selects the appropriate connector.
SCSI
The DECstation 3 100 supplies a small computer
system interconnect (SCSI) as the interconnect for
storage peripherals. The workstation's SCSI i nter face consists of a gate array controller chip and a
1 28 K B buffer. The controller chip manages the SCSI bus through selection, DMA data transfer, and dis connect commands. The interface supports com mand d isconnect/reconnect and synchronous data transfers at 4 MB per second on the SCSI bus. The buffer is time-multiplexed between the controller chip and the workstation CPU .
An SCSI connector on the rear of the DECstation 3 100 system box allows connection of external SCSI peripheral devices. Digital offers a 332 M B disk , a 95 MB tape, and a 600 MB CDROM reader. Each of these devices is packaged with power in its own sidecar box .
Table 1 Comparison of RISC System Performance DECstation
3 1 00
D h rystones/second 22.7K
Li npack single precision 3.7
(M FLOPs)
Unpack double precision 1 . 6
( MFLOPs)
Stanford small i nteger bench mark 0 . 1 1 5
(seconds)
Digital Review's CPU 2 benchmark 6.91
suites (seconds)
X L I B graphics performance rate 4.9K