Raman Spectroscopy

Raman spectroscopy is a technique based on the inelastic scattering of monochromatic light, first demonstrated in 1928 by Sir C. V. Raman, whom the technique has since been named after. In this work, Raman spectroscopy has been applied to determine the effectiveness of annealing processes used to recover crystal damage inflicted during ion implantation as well as the free carrier concentration in the implanted regions of the devices. All Raman spectroscopy performed in this thesis has been carried out using a 244 nm DUV laser within the Department of Physics at the University of Bath, UK [152]. In Raman spectroscopy, light from a laser source interacts with molecular vibrations, phonons or other excitations in the system, which results in the energy of laser photons being shifted up or down. This shift in energy is utilised to give information concerning the vibrational modes in the system. An energy level diagram showing the states involved in a Raman signal is shown in Figure 5.11. Due to it having relatively low absorption coefficients in the visible region, thus giving large penetration depths for Raman probe lasers, the analysis of ion implanted regions in SiC typically requires a UV laser. For a laser wavelength of 244 nm, a penetration depth of 50-100 nm is expected [153]. A detailed discussion of the theory of Raman spectroscopy is given in [154].

4 3 2 1 0 Virtual energy states Vibrational energy states Infrared absorption Rayleigh scattering Stokes Raman scattering Anti-Stokes Raman scattering

Figure 5.11: Energy level diagram showing the states involved in a Raman signal. The line thicknesses are approximately proportional to the signal strength from the different

transitions.

5.3

Summary

In this Chapter, both the electrical and physical characterisation techniques that will be applied to the 4H-SiC power devices fabricated in this thesis have been presented. Details of the characterisation equipment, both electrical and physical, that will be used have been provided, in addition to the specific techniques that will be used to extract important device parameters such as ohmic contact resistance and carrier lifetime.

6

4H-SiC PiN Diodes

In this Chapter, the fabrication processes required for high voltage 4H-SiC PiN diodes that have been developed are presented. Firstly, characterisation and optimisation of dry etching processes was carried out. Following this, a study into the formation of low- resistance, reliable ohmic contacts to p-type 4H-SiC has been undertaken, encapsulating both electrical and physical characterisation to determine the mechanisms behind the performance of these contacts.

6.1

RIE and ICP Etching Characterisation

The etching of 4H-SiC typically demands the use of RIE or ICP etch methods, due to the high temperatures required for wet etching processes, as described in Chapter 3. For the high voltage devices fabricated in this work, the profile of the etched 4H-SiC mesa sidewalls is important, as rough, jagged features can enhance electric field crowding and thus reduce the breakdown voltage capability of the device [76]. Moreover, poor surface morphology resulting from etching processes can increase the surface recombination rate

due to defect centres created, thus reducing the overall carrier lifetime in the device. As such, the use of an optimised 4H-SiC etch method is crucial if high performance PiN diodes are to be realised.

As well as the etching of 4H-SiC, the etching of the mask used for the 4H-SiC etch is also important, as it is the profile of this that dictates the profile of the etched 4H- SiC features. Masking materials that have been deployed in this work include photoresist,

SiO2and NiV. However, in order to prevent micro-masking, the deposition of NiV masking

layers directly onto the 4H-SiC material has been avoided [76]. The etch rates and mask selectivity of etch processes that have been experimentally determined in this work are summarised in Table 6.1. In order to measure etch steps heights, an Ambios Technology stylus profileometer has been used. One fundamental observation that can be made from the data in Table 6.1 is the vast difference in etch rate between the RIE and ICP processes

for the SiO2 etch, which, coupled with the fact that RIE processes typically inflict more

damage on the etched surface, makes ICP etching the preferred technique to use. Though not shown in the Table, the RIE etch rate for 4H-SiC was markedly slower than the ICP etch rate, etching at a rate of approximately 12 nm/min, rendering it impractical for etching features greater than a few hundred nm in depth.

Initial characterisation of SiC etching involved using a tetraethyl orthosilicate (TEOS)

SiO2 mask, itself masked by S1818 photoresist to enable patterning of the SiO2. After

photolithography, the SiO2 was patterned using the SiO2 vertical ICP etch for a duration

sufficient to penetrate the SiO2 mask. However, due to inadequate heat sinking of the

4H-SiC sample during the etch, the photoresist was heat-damaged during this process.

The photoresist was then removed in O2 plasma, and the SiC was etched using the 50 SF6

+ 3 O2 1000 W ICP program. Upon completion of the SiC etch, the remaining SiO2

etched SiO2 and SiC. Figure 6.1 illustrates the profile of etched SiO2 mesa mask after the

photoresist was removed. It is evident from this Figure that not only are the sidewalls of poor morphology due to the photoresist being heat-damaged, but the surface of the

SiO2 from which the photoresist has been removed also shows signs of damage. As shown

in Figure 6.2, this poor morphology of the SiO2 mask has been replicated when etching

the 4H-SiC, which would clearly have implications for the electrical performance of the device.

Table 6.1: Summary of etch rates and mask selectivity for RIE/ICP etch processes.

Etch process Mask used Etch rate (nm/min) Selectivity

SiO2 RIE (100 CHF3 + 5 O2, 170 W) Photoresist ∼28 1.5

4H-SiC (50 SF6 + 3 O2, 1000 W ICP) SiO2 ∼820 1.7

4H-SiC (50 SF6 + 3 O2, 1000 W ICP) NiV ∼735 20

SiO2 vertical ICP etch (800 W ICP) Photoresist ∼415 1.6

SiO2 sloped ICP etch Photoresist ∼535 2.0

In order to prevent this problem of poor morphology resulting from the use of a heat- damaged photoresist mask, it was clear that either the etching process had to be modified so that the photoresist would not become damaged, or, alternatively, the use of photoresist

for masking the SiO2 during the ICP etch had to be eliminated. Unfortunately, because

of the design of the RIE/ICP etching equipment, it is difficult to achieve satisfactory heat sinking when using small (sub-4 inch) wafer samples, as these samples have to be mounted on a Si carrier wafer and thus do not gain the benefit of the helium chuck that thermally connects the 4 inch wafer to the chiller system. Another possible option could be to decrease the power of the ICP etching program and correspondingly increase the etch time, though due to the unsatisfactory heat sinking performance, this is still potentially problematic. It was therefore decided to eliminate the use of photoresist during any ICP etch programs, instead using a NiV mask. Though this adds additional processing steps,

Figure 6.1: ICP etched SiO2 mask patterned using photoresist (photoresist mask removed prior to SEM imaging).

the NiV is a lot less susceptible to the heat generated during ICP etching than photoresist, and should result in better 4H-SiC feature definition. Figures 6.3 and 6.4 show the profile of an etched 4H-SiC mesa sidewall after mask removal; it is evident that the surface quality is significantly improved. In addition, the masked surface of the 4H-SiC was unaffected by the etch process, as intended. The sidewalls now exhibit a smooth texture, though the shortcomings of the photolithography, which have resulted in striation of the sidewalls, are visible [155]. Due to the relatively large size of the devices fabricated in this work compared to the sidewall imperfection this is not considered to be a cause for concern; however, it is noted that further refinement of photolithographic feature definition would be required for devices that rely on a uniform sidewall, such as trench MOSFETs.

Figure 6.2: ICP etched SiC mesa sidewall with SiO2 mask patterned using photoresist

(SiO2 mask removed prior to SEM imaging).