Registers

The PowerPC has 32 general purpose integer registers, r0 to r31, a condition register, CR, and a

link register, LR. Other registers including a special purpose register XER and a count register

CTR. Although there is no program counter visible to the object code programs of the PowerPC,

a program counter is assumed in the definition of the semantics given in the processor manual (Motorola Inc. and IBM Corp., 1997). The set of registers for the PowerPC will include the identifier pc to act as the program counter of the languageL.

fr0

;

r1

;::: ;

r31

;

CR

;

LR

;

XER

;

CTR

;

pcgRegs

All registers store values as bit-vectors of length32. The general purpose registers r0 to r31 store addresses in memory for instructions which move data between the registers and memory. The general purpose registers also store the arguments to and results of the operations implemented by the processor instructions. The link register LR is used to implement sub-routines and stores the address to which control is to return.

5.3 The PowerPC Architecture 158

The condition register, CR, is organised as8fields of4bits each. Each field reflects the result of an operation on data and is similar to the status register, SR, of the M68000. Bit0of a field indicates that the result of an operation was a negative number (using two’s complement repre- sentation); bit1indicates that the result was a positive number (greater than 0); bit 2indicates that the result was0 and bit3 indicates that an overflow occurred. An instruction may specify the field of the condition register to be used, when the field is not specified, field0is assumed.

The XER register is also used to store information about data. The two most significant bits of the register indicate that an operation generated an overflow, the third most significant bit indicates that an operation generated a carry. The least significant byte of the register is used by some instructions as a counter. The count register, CTR, is used together with some forms of the jump instruction to implement iteration and stores the number of iterations be performed. The count register is also used in some instructions to store the label of the instruction to which control is to pass.

5.3.2

Instructions

The general form of a PowerPC instruction isinst dst

;

src1

;

src2 whereinstis the instruction name, dst is the destination argument and src1

;

src2 are the source arguments. Each instruction operates on data of a given size and this determines the instruction name. For example, the instructions namedlbzandlwzimplement the same operation but operate on a byte and a long- word (a PowerPC word) respectively.

When the general purpose registers, r0

;::: ;

r31 occur as an argument to an instruction, they

are denoted by the numbers 0to 31. Whether an instruction argument such as 1is interpreted as a register or as a value is determined by the semantics of the instruction. Here, instruction arguments which are registers will be written r

;

r0

;:::

and values will be denoted

v;v

0

;:::

. The instructions may interpret a value

v

as either a signed or an unsigned number.

Data Movement

There are two types of data movement instruction: a load moves data from the memory variables to the registers, a store moves data from the registers to memory. For both operations, a number of instructions are defined to operate on different sizes of data and to use the different addressing modes of the PowerPC.

In the register indirect addressing mode, the operand is in memory at the location determined from a register r. In the register indirect with immediate index mode, an argument is written

v

(r) and the address of the operand is obtained by the addition of

v

to the register r. In the register

indirect with index mode there are at least two source registers r1 and r2 and the address is

obtained by the addition of r1 and r2. All addressing modes for the data movement instructions interpret the register r0 as the value0. For either of the indexed addressing modes, the instruction may also update a register with the calculated address.

5.3 The PowerPC Architecture 159

The load word and zero with update indexed, written lwzux r1

;

r2

;

r3, operates on a long-

word (a PowerPC word) and uses register indirect with index addressing. Register r1 and r2 are destination arguments and the source argument is register r3. The sum of r2 and r3 identifies a location in memory in which a value

v

is stored. Register r1 is assigned the value

v

and register

r2 is assigned the address of

v

.

r1

;

r2:=ref(r2+ 32r3

)

;

r2+ 32r3

(if r16=0)

The PowerPC reference manual defines the instruction in which r1 = r2 to be invalid. This ensures that the assignment to r1 and r2 is always correct.

The store half-word with update instruction, writtensthur1

;v

(r2), stores the16bit value (a PowerPC half-word) contained in the lower half of the register r1 in the memory location whose address is the sum of

v

and r2. Register r2 is updated with this address.

ref(r2+ 32ext

(Long

;

Word

;v

))

;

r2:=mkWord(r1)

;

r2+ 32ext

(Long

;

Word

;v

)

Program Control

A branch instruction passes control to a target location and may be conditional on the value of the register CR. The target of the branch is a constant or is obtained from the link register LR or the count register CTR.

An unconditional branch has a single argument from which the target of the jump is cal- culated. The absolute branch instruction, ba

v

, passes control to the instruction at address

v

,

goto loc(

v

). The branch and link instruction,bl

v

, stores the address of the next instruction in memory in the link register. The target of the branch is the instruction whose address is calculated from pc+

v

(where

v

is interpreted as a signed number).

LR

;

pc:=pc+ 32

4

;

loc(pc+ 32

v

)

The instruction branch to link register, blr, implements a return from sub-routine: control is passed to the address stored in the link register, goto loc(LR).

Conditional branch instructions have the form bc

a;b;v

where

a;b

31are control argu-

ments and

v

is the target address. Argument

a

2 Values determines how the result of the test is to be interpreted and argument

b

2 Values determines the bit of the condition register CR to be tested. Argument

a

may also provide information to allow the processor to predict the result of the test. This allows the processor to perform some optimisations but does not otherwise affect the execution of the program.

In the branch conditional instruction,bc 4

;

6

;v

the first argument,4, indicates that the tested bit must not be0. The second argument indicates that the test is of bit6of the condition register

CR (bit2of field1of the condition register). Argument

v

is the address, relative to the current instruction, to which control passes.

if not bit(6)(CR)then goto loc(pc+ 32

v

5.3 The PowerPC Architecture 160

int strlength(char *a) f int c; c=0; while(*(a+c)!=0) fc=c+1;g return c; g

Figure 5.11: Strlength: C Program

Arithmetic and Comparison Instructions

The arithmetic operations include addition, subtraction, multiplication and division on bytes, words and long-words. The arithmetic instructions are typically of the form inst r0

;

r1

;

r2

and implement the operation r0 :=

f

(r1

;

r2), where

f

is a function on the values. The add instruction,add r0

;

r1

;

r2, assigns to r0 the sum of r1 and r2. The add immediate instruction,

addir0

;

r1

;v

, assigns to r0 the sum of r1 and

v

2Values. addr0

;

r1

;

r2 r0:=r1+

32r2 addir0

;

r1

;v

r0:=r1+

32

v

Comparison instructions set the flags of the registers CR and XER to reflect the difference

between the operands. The compare instruction is writtencmp

a;

r0

;

r1 and the comparison is by

the subtraction of r1 from r0. Field

a

, for

a <

8, of the condition register CR is set to reflect the result of the comparison. One of bits0,1and2of field

a

is set and the remainder are cleared.

Summary

The PowerPC processor language is based on a large number of general purpose registers. There are only three addressing modes and only data movement instructions can transfer data between registers and memory variables. The PowerPC supports sub-routines by providing the link regis- ter LR but does not otherwise support facilities such as stack or frame pointers. The instructions of the PowerPC are generally simpler than those of the M68000. For example, both the M68000 and the PowerPC have instructions to add two variables. However, the PowerPC addition instruc- tion can only make use of the registers while the M68000 instruction can also access memory variables using a range of addressing modes. The simplicity of the PowerPC instructions and the memory operations of the processor mean that the model of instructions in the languageLis straightforward. This model also illustrates the ability of the languageLto describe the instruc- tions of different processors. The complexity of the model inLdepends on the complexity of the instructions and data operations of the processor. The languageLdoes not, therefore, introduce additional complexity in the model of processor instructions.

5.3 The PowerPC Architecture 161

In document Object code verification (Page 175-179)