Ring Ptuging Algorithm

One of the well- known problems on a token ring is the circul ation of frames or long fragments that are not stripped by the t ransm i t ter. The frame or long fragment not stri pped b\· the t ra nsm i t te r is cal led a no-own e r frame ( NOF). On an id le ri ng, 1"\JOFs can

circu late a ro u nd the r i ng, a long w i th the token, continuously at the speed of the ri ng. NOFs may be rece ived by one or more systems on the r i ng re peatedly at an extremely h igh rate, which can lead to severe congestion and waste of system resources. For example, a s i ngle NOF on an i d le ring c a n create a frame a rrival rate of 2,700 frames p e r second (for m a x i m u m s i ze frame) to about 290,000 frames p e r second (for m i n i m u m size frame). I n t h e best case, the NOFs a rc removed when they arrive at a MAC that is transm i t t i ng (i.e . , hold i ng the token).

Digita l developed an a lgori t h m c a l l ed the r i ng purgi ng a lgori t h m to remove NOFs. The ring p urg i ng a lgori t h m ensures that NOFs do not t raverse the r i ng m ore than twice. The implementa t i o n of ring purging consists of two related, but d i fferent, a lgo rithms. The first one is the purger elect i o n algo rithm, which is a d istributed election a lgo rithm to select a designated MAC _{to be the p u rge r for the} ring. The second a lgorithm is the p urging a lgorithm, which is execu ted by the designated MAC _{to clean} the ring of NOFs. We describe the p urgi ng a lgorithm in th is sect ion .

The p urgi ng a lgori t h m adopted for Digita l's FDD I data l i n k p u rges the r i ng t ra nspare n t l y each t ime a token is received by the p u rger. When the pu rge r recei ves a token , i t begins a p u rge cycle by t rans m i t t i ng two speci a l fra mes. cal led void frames. I f the p u rger h a s frames to t rans m i t, i t completes the t ransmissi on of i ts frames before start i ng the p u rge cycl e . Once the purge cycle has started , the p u rger u n cond i t iona l l y removes a l l frames or fragments received. The p u rge cycle is t e r m i nated when the p u rge r rece ives one of its e rror-free void frames, a token, o r a r i ng i n i t i a l i za t i o n fram e . I n order to i n crease the p robab i l i ty of correctly terminating the p u rge cycle, t h e p u rger t ransmits two vo id frames: b u t i t term i n ates its p u rge cycle based on receiving only one e rror- free vo icl .

Figure :) shows the operations of the ring p u rge r i n rem ov i ng a n NOF, cl u ri n g a n i d le ri ng and d u r i ng a bu S\' r i ng. Each t i me s t a t i o n S:) (the pu rger) receives t h e token, it may t rans m i t its fra mes, fo l lowed by rwo void frames and t h e n the token . It p u rges t he r i ng u n t i l it receives one of its error-free void fra mes. As show n in t he exam ple, the NOF was p urgetl hy station S:) on its second t raversal around the ring. Also. the exa m p le shows that the p u rg i ng of the ring is transparent ( i . e . , there is no d isruption to the r i ng).

The i mp act of ring p u rging on ring performance is negl igible, because the r i ng p urger only i n i t iates the p urge cycle when it has the right to use a token.

SPAC E - ' / ' �- - .. ' · . . --- - -=

::

1 NOF NO·OWN E R F R A M E N O T E T H I S F I G U R E IS N O T T O SCALE.

Figure

3

Ring Pu rging t::xarnple

In the worst case, the ring purger's effect on usable bandwidth is Jess than 0.22 percent. For implemen tati ons compliant to the ANSI FDDI MAC standard, these void frames have no effect since the standard prohibits copying void frames.

The ring p urging algorithm removes NOFs, includ ing long fragments. without d isrupting the operation of the ring, and it removes NOFs within two traver sals of the frame. In ackl it ion, it has an important property that p e r m i ts m ore than one p u rger to opc:rate i n the same ring at any time. This property

Di,�ilttf Tee/m ica/ journal HJ/. 3 No . .! Sprinf,

1991

fDDI Datu Unk Det ·e!opment

a l lows the purger elect ion a lgorithm to be more optim istic (i.e . , when in doubt during election, one can start purging) during the transition period when the distributed election a lgorithm is stabil izi ng. The p u rger election a lgorit h m is implemented i n t h e Common Node Softwa re (CNS), and the p u rg ing algorithm is implemented in the :.1AC chip.

FDDI Data Link Chips

The fDDI 1\1AC sublaye r hmct ions arc implemented by the three FDDI data l i n k chips: the ring mem ory controller (RMC), med ia access control ( iVIAC ) , and content addressable memory (CAM). The RJVIC interfaces between the frame buffer memory on the system side and t he 1'<1AC chip on the network side. It consists of a d i rect memory access (DMA) _engine designed to supply the MAC _{chip with frames to send} and to store frames received from the ;vlAC chip. The interface on the system side provides gathered reads on transm i t and scattered wri tes on receive. Although tile &VIC's i nte rface to the MAC chip was custom designed for FDOI operat ion, the RMC can, in principle, be used for other data l in ks t hat run at 100 megabits per second or less. The MAC and CAM chips implement the FD D l MAC: protocol func tions. The functions implemented by the MAC chip i nclude t he token access protocols, frame del i n eation, frame parsing. address recognition, frame check sequence generation and verification, frame i nsertion, frame repet i t ion, frame removal , token generation, and error detection and recovery a lgo rithms (e.g . , the beacon and claim algorithms). The CAM chip provides the des t i nation address fil tering, which determines if a rece ived frame is to be received or d iscarded , and the sett i ng of the A-indicator, which is part of the frame status field.

RMC Chip

The RMC _{chip is a high-performance coprocessor} i ntended for full-duplex data transfe r between the buffer memory and the MAC chip. It uses a pair of circular bu ffer queues for transm i t and receive to manage DMA data transfers to and from the buffer memory. Two independent on-ch i r . first in, first out (FIFO) buffers, for receive and transmit, are pro vided to decouple the buffer memory from the real t i me nature of the �lAC i nterface. A fragment ancl frame fi lter is provided to reduce unnecessary mem ory accesses caused by the reception of fragments or frames not addressed to this station. As shown

in Figure 4, t he RMC chip has three interfaces: the processor interface, the M A C _c_{hip interface, and the} buffer memory i n terface. The processor i n terface

Fi ber Distributed Data Interface

TO/FROM B U F F E R M E M O R Y

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3 2 BITS DATA PLUS PARITY

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BUFFER MEMORY INTERFACE A N D A R B I TE R

R E C E I V E DMA TRANSMIT _DMA

STATE MACHINE STATE MACHINE

TRANSMIT F I FO R E C E I V E F I FO B U F F E R B U F F E R ( 1 28 BYTES I N ( 2 5 6 BYTES I N 32 BY 40 BITS) 64 BY 41 BITS) MAC R E C E I V E M A C TRANSMIT I N T E R FACE I N T E R FACE P ROCESSOR I N T E R FA C E I I I I

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EXTERNAL DATA PATH

I NT E R NAL CONTROL M E D I A ACCESS CONTROL D I R ECT MEMORY ACCESS F I RST IN. F I R ST OUT

PROCESSOR I N T E R FACE

Figure 4 Ring Memo1T Con trolfer Cbip Block Diagram

al lows the initialization, control. and obse rva t i o n

o f the RMC The MAC chip i nterface consists of h igh speed trans m i t and receive data paths for tran_s_fer

of data and control in formation between the M AC chip and rhe IlviCs f'I

F

O buffers. The buffer memory interface provides a hurst mode

DMA

for read/ write from/to the bu ffer memory on a si ngle bus a rbitrat ion cycl.e , where the burst size can he up to fou r o r eight longwords. The

RMC: can

provide a

maximum data transfer rate o f abou t

44 mega

byres per second.

The RMC is implemented u s i ng a

I .')

-micron drawn , rwo-meral- lay<.:r custom compl eme ntary metal oxide sem i conductor (CM OS) technology. lt uses roughly 87,000 transistors, a l a rge nu mber of which are useu for the two FIFO bu ffers, where the receive FIFO buffer is 2'56 byres and the t ransm i t

l'I FO buffe r is 1 2 8 byt<.:s. T h e R MC u se s 1 0 2 s i gna l pins and is avai lable i n a 132-pin cnquad package.

I t is also a fu l l y synchronous design ]some self-timed logic is used i n the

FIFO

random access memory (RAM) devices] u s i ng a 12.5 -megahertz (MHZ) pri m:�ry clock and 25 -MHz clock for sampling i n com i ng signals. The

FJFO

RAM was implemented using

a

fu l l custom methodology, and the remai nder was implemented u s i ng an automated standard

eel I methodology.

The flYIC interfaces to buffer memory using a data and address multiplexed bus, which is a 32-bi r -wide bus plus the four pa rity signals and add i t i onal con trol signals. A bus transaction consists of an address cycle driven by t he RMC : followed by a burst of data cycles, either driven by the RMC _{on re}_ce_{ive or driven} by the b u ffe r memory on trans m it. One of the unique featu res of this chip is that it is able to use a 52-bi t -wide buffer memory composed of low-cost 1 100-nanosccond (ns) access t ime ] dynamic random access memory (DRAM) chips, whereas many of the

other

FOD!

memory control lers avai I able on the market requ ire a 64-bit buffe r memory or require very fast DRA!'vl _{or static random access memory}

(SRAM) _{chips. To achieve these reduced memory}

and chip requirements, the R MC's buffer memory accesses were done in bursts of between one and eight Jongwords. Then, by making use of the D�Yl's fast page mode, in which subseq uent, sequen t i a l reads/writes are faster than t h e first one, the needed buffer memory bandwidth is attainable.

The R.MC d i rect l y accesses a transmit ring and a receive ring, each consist ing of a circular queue of descriptors. Each descriptor suppl ies the buffer memory address of a t ransm i t bu ffer or a receive buffer. An OWN b i t mechanism is used in each descriptor to determine if the descrip tor and i ts bu ffer is owned by the .RNIC or not. It supports gath ered read and scattered write in which frames to be received or transmi tted can use one or multiple

FDDJ Data Link Det •elopment

buffe rs (and hence multiple descriptors), but a speci

fic buffer/descriptor can only be used by one frame. Each receive buffer is required to be 512 bytes long. The RMC rewrites each descriptor in the receive ring to i nd icate the nu mber of bytes actu a l l y used ; and if the buffer is t he last one for the frame, then the RMC writes the receive status and the frame byte count into the descriptor. Transmit buf fers are also 512 bytes long and the RMC _{reads the}

size (in bytes) from the first descriptor for the frame.

MAC Chip

The MAC _{chip i mplements the}_{FDD! MAC}_protocols, and it interfaces between the RMC _{or equivalent} chip and t he FDDI physical layer chip.'' As shown in Figure 5, the MAC has fou r i nterfaces: the processor i nterface, the RMC i nte rface, the phys ical layer chip inte rface, and the CAM inte rface. The proces sor interface allows t he initial ization, controL ancl

PROCESSOR RMC I N T E R FACE INTERFACE

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RMC R E C E I V E I N T E R FACE . . . - - - · PHY RECEIVE INTERFACE ADD RESS COMPARE R E C E I V E STATE MAC H I N E R E C E I V E C R C C H E C K E R RMC TRANSMIT I N T E R FACE T I M ERS TRAN S M I T PROCESSOR STATE MAC H I N E INTERFACE TRANSMIT CRC _SEND C H ECK! FRAME G E N E RATE 8 BITS PHY TRANSMIT I N T E R FACE · ···--- •• • • • •• • • • • •• • • • • •• • • • • • • J - - - -

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-�- - - -

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t

KEY - I NT E R N A L DATA PATH

•• • - EXTERNAL DATA PATH

- INTE RNAL CONTROL

PHYSICAL LAYER C H I P I N T E R FACE

RMC RING M E MORY CONTROLLER CRC CYC LIC R E D U N DANCY C H E C K CAM CONTENT ADD RESSABLE M E MORY PHY PHYSICAL LAYER

Figure 5 Media A ccess Control Cbip Block Diagram

Fiber Distributed Data Interface

observation of the MAC. The RMC i nt erface is cus tom designed for FDDJ operation ancl al lows the MAC to i nterface to either the RMC or to equivalent chips implemenring the RJv!C i nterf<�ce. The physi cal layer chip i nterf<�ce a l lows the ,vlAC to receive and trans m i t on the FDDI ring.

The MAC chip is implemented using a L5-micron drawn, channel less, two-metal-layer

CMOS

gate-array technology and u ses rough l y 49,000 t ra nsistors ( 12,000 used gates). The MAC chip uses 86 s ignal pins and is ava i lable in either a 120-p i n p i n grid array ( PGA) package or a 120-pin pl astic quad flat pack (PQFP) package. This ful l y synchronous design uses primaril y a single 12.5 -MHz clock (80-ns cycle t ime): this operation is appl ied to the m icroproces sor bus as wel L An add i tional double-speed cl ock is used i n some of the peripheral i nterface logic to

In document dtj v03 02 1991 pdf (Page 36-41)

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