4. Pinout and Package Definitions
5.3. ADC0 Operation
5.3.6. Settling Time Requirements
A minimum tracking time is required before an accurate conversion can be performed. This tracking time is determined by the AMUX0 resistance, the ADC0 sampling capacitance, any external source resistance, and the accuracy required for the conversion.
Figure 5.6 shows the equivalent ADC0 input circuit. The required ADC0 settling time for a given settling accuracy (SA) may be approximated by Equation 5.1. When measuring VDD with respect to GND, RTOTAL reduces to RMUX. See Table 5.3 and Table 5.4 for ADC0 minimum settling time requirements.
Equation 5.1. ADC0 Settling Time Requirements
Where:
SA is the settling accuracy, given as a fraction of an LSB (for example, 0.25 to settle within 1/4 LSB) t is the required settling time in seconds
RTOTAL is the sum of the AMUX0 resistance and any external source resistance.
n is the ADC resolution in bits (12).
Figure 5.6. ADC0 Equivalent Input Circuits t 2
nSA
---
× R
TOTALC
SAMPLEln
=
RMUX = 5
CSAMPLE = 12 pF
RCInput= RMUX* CSAMPLE
MUX Select
Px.x
kΩ
SFR Definition 5.1. ADC0MX: ADC0 Channel Select
Bits7–5: UNUSED. Read = 000b; Write = don’t care.
Bits4–0: AD0MX4–0: AMUX0 Positive Input Selection
*Note: Only applies to C8051F410/2; selection RESERVED on C8051F411/3 devices.
R R R R/W R/W R/W R/W R/W Reset Value
- - - AD0MX 00011111
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xBB
AD0MX4–0 ADC0 Input Channel
00000 P0.0
00001 P0.1
00010 P0.2
00011 P0.3
00100 P0.4
00101 P0.5
00110 P0.6
00111 P0.7
01000 P1.0
01001 P1.1
01010 P1.2
01011 P1.3
01100 P1.4
01101 P1.5
01110 P1.6
01111 P1.7
10000 P2.0
10001 P2.1
10010 P2.2
10011 P2.3*
10100 P2.4*
10101 P2.5*
10110 P2.6*
10111 P2.7
11000 Temp Sensor
11001 VDD
11010 - 11111 GND
SFR Definition 5.2. ADC0CF: ADC0 Configuration
Bits7–3: AD0SC4–0: ADC0 SAR Conversion Clock Period Bits.
SAR Conversion clock is derived from FCLK by the following equation, where AD0SC refers to the 5-bit value held in bits AD0SC4-0. SAR Conversion clock requirements are given in Table 5.3.
BURSTEN = 0: FCLK is the current system clock.
BURSTEN = 1: FCLK is a maximum of 25 MHz, independent of the current system clock.
* or
*Note: Round the result up.
Bits2–1: AD0RPT1–0: ADC0 Repeat Count.
Controls the number of conversions taken and accumulated between ADC0 End of Conversion (ADCINT) and ADC0 Window Comparator (ADCWINT) interrupts. A convert start is required for each conversion unless Burst Mode is enabled. In Burst Mode, a single convert start can initiate multiple self-timed conversions. Results in both modes are
accumulated in the ADC0H:ADC0L register. When AD0RPT1-0 are set to a value other than '00', the AD0LJST bit in the ADC0CN register must be set to '0' (right justified).
00: 1 conversion is performed.
01: 4 conversions are performed and accumulated.
10: 8 conversions are performed and accumulated.
11: 16 conversions are performed and accumulated.
Note: The ADC0 output register is automatically reset to 0x0000 upon reaching the last conversion specified by the repeat counter. If the ADC is disabled during a conversion and re-enabled later, the ADC0H and ADC0L registers should be manually cleared to 0x00.
Bit0: RESERVED. Read = 0b; Must write 0b.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0SC AD0RPT Reserved 11111000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xBC
AD0SC FCLK CLK
SAR--- – 1
= CLK
SARFCLK
AD0SC + 1
---=
SFR Definition 5.3. ADC0H: ADC0 Data Word MSB
SFR Definition 5.4. ADC0L: ADC0 Data Word LSB
Bits7-0: ADC0 Data Word High-Order Bits.
For AD0LJST = 0 and AD0RPT as follows:
00: Bits 3–0 are the upper 4 bits of the accumulated result. Bits 7–4 are 0000b.
01: Bits 5–0 are the upper 6 bits of the accumulated result. Bits 7–6 are 00b.
10: Bits 6–0 are the upper 7 bits of the accumulated result. Bit 7 is 0b.
11: Bits 7–0 are the upper 8 bits of the accumulated result.
For AD0LJST = 1 (AD0RPT must be '00'): Bits 7–0 are the most-significant bits of the ADC0 12-bit result.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xBE
Bits7-0: ADC0 Data Word Low-Order Bits.
For AD0LJST = 0: Bits 7-0 are the lower 8 bits of the ADC0 accumulated result.
For AD0LJST = 1 (AD0RPT must be '00'): Bits 7-4 are the lower 4 bits of the 12-bit result.
Bits 3-0 are 0000b.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
0xBD
SFR Definition 5.5. ADC0CN: ADC0 Control
Bit7: AD0EN: ADC0 Enable Bit.
0: ADC0 Disabled. ADC0 is in low-power shutdown.
1: ADC0 Enabled. ADC0 is active and ready for data conversions.
Bit6: BURSTEN: ADC0 Burst Mode Enable Bit.
0: ADC0 Burst Mode Disabled.
1: ADC0 Burst Mode Enabled.
Bit5: AD0INT: ADC0 Conversion Complete Interrupt Flag.
0: ADC0 has not completed a data conversion since the last time AD0INT was cleared.
1: ADC0 has completed a data conversion.
Bit4: AD0BUSY: ADC0 Busy Bit.
Read:
0: ADC0 conversion is complete or a conversion is not currently in progress. AD0INT is set to logic 1 on the falling edge of AD0BUSY.
1: ADC0 conversion is in progress.
Write:
0: No Effect.
1: Initiates ADC0 Conversion if AD0CM1-0 = 00b Bit3: AD0WINT: ADC0 Window Compare Interrupt Flag.
This bit must be cleared by software.
0: ADC0 Window Comparison Data match has not occurred since this flag was last cleared.
1: ADC0 Window Comparison Data match has occurred.
Bit2: AD0LJST: ADC0 Left Justify Select
0: Data in ADC0H:ADC0L registers is right justified.
1: Data in ADC0H:ADC0L registers is left justified. This option should not be used with a repeat count greater than 1 (when AD0RPT1-0 is 01b, 10b, or 11b).
Bits1-0: AD0CM1-0: ADC0 Start of Conversion Mode Select.
00: ADC0 conversion initiated on every write of ‘1’ to AD0BUSY.
01: ADC0 conversion initiated on overflow of Timer 3.
10: ADC0 conversion initiated on rising edge of external CNVSTR.
11: ADC0 conversion initiated on overflow of Timer 2.
R/W R/W R/W R/W R/W R/W R/W R/W Reset Value
AD0EN BURSTEN AD0INT AD0BUSY AD0WINT AD0LJST AD0CM1 AD0CM0 00000000
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 SFR Address:
(bit addressable) 0xE8