Timing diagram A diagram showing how two or more digital waveforms in a system relate to each other over time.
Simulation The verification, using timing diagrams, of the logic of a digital de- sign before programming it into a PLD.
Stimulus waveforms A set of user-defined input waveforms in a simulator file designed to imitate input conditions of a digital circuit.
Response waveforms A set of output waveforms generated by a simulator for a particular digital design in response to a set of stimulus waveforms.
Propagation delay Time difference between a change on a digital circuit input and a change on an output in response to the input change.
An important part of the CPLD design process is simulation of the design. A simulation tool allows us to see whether the output responses to a set of circuit inputs are what we ex- pected in our initial design idea. The simulator works by creating a timing diagram. We specify a set of input (stimulus) waveforms. The simulator looks at the relationship be- tween inputs and outputs, as defined by the design file, and generates a set of response outputs.
Figure 5.8 shows a set of simulation waveforms created for the 2-line-to-4-line de- coder in Figure 5.4. The inputs D1 and D0 are combined as a single 2-bit value, to which an increasing binary count is applied as a stimulus. The decoder output waveforms are ob- served individually to determine the decoder’s response. Once we have entered the design in the MAXPLUS II Graphic Editor and compiled it, we can create the waveforms as follows.
K E Y T E R M S
FIGURE 5.8
Simulation Waveforms for a 2- to-4 Decoder with Enable
From the File menu, select New. On the resultant dialog box, select Waveform Edi-
tor File, with a default file extension scf. From the File menu, choose Save As, then enter drive:\max2work\chapt05\decoders\2to4dcdr.scf.
➥2to4dcdr.gdf 2to4dcdr.scf
5.1 • Decoders 163 We specify the inputs and outputs we want to view by selecting Enter Nodes from
SNF on the Node menu, shown in Figure 5.9. In the dialog box that pops up (Figure 5.10),
there are two boxes labelled Available Nodes & Groups and Selected Nodes & Groups, with an arrow () pointing from one to the other. Select the List button to show the “available” signals and click the arrow to transfer them all to the “selected” box. Click OK to close the box.
Figure 5.11 shows the simulation waveforms in their uninitialized (default) states. In- puts and outputs are shown by symbols in front of the signal names. Inputs are at logic 0 and outputs are indicated as X or unknown values.
FIGURE 5.9
Node Menu
FIGURE 5.10
Selecting Nodes for Waveform Editor
FIGURE 5.11
We now set the timing length of the simulation. The default value is 1 s, written
1.0us. For this example, we will leave the end time at the default value. However, if we
want to change it, we select End Time (File menu, Figure 5.12) and enter the new time for the end of simulation in the dialog box of Figure 5.13. Click OK.
FIGURE 5.12
Setting the End Time of a Simulation (File Menu)
FIGURE 5.13
End Time Dialog Box
FIGURE 5.14
Setting Simulation Grid Size (Options Menu)
FIGURE 5.15
Grid Size Dialog Box
The End Time dialog sets the end of the simulation. We should also set the Grid Size, which determines the size of the smallest time division in the simulation. To do so, select
Grid Size from the Options menu, shown in Figure 5.14. In the dialog box of Figure 5.15,
5.1 • Decoders 165 because it corresponds to one half period of the oscillator on the Altera UP-1 board. In the simulator, one full period requires two grid spaces.)
When we created the simulation file, the D inputs were entered as separate waveforms. We can join these waveforms to make a Group. Highlight both D1 and D0 by clicking on one name and dragging the mouse to the next name, as in Figure 5.16. From the Node menu or the pop-up menu in Figure 5.17, select Enter Group. The dialog box shown in Figure 5.18 appears, containing the most likely name derived from the highlighted group. Either type a new group name or accept the original name by clicking OK.
FIGURE 5.16
Highlighting a Group
FIGURE 5.17
Pop-up Menu (Enter Group)
FIGURE 5.18
Save the file. From the MAXPLUS II menu, bring the Simulator to the front and
click Start. When the simulation is finished (almost immediately), click Open SCF and maximize the window. From the View menu, select Fit in Window or select the toolbar button for this function.
The simulator output, shown in Figure 5.21, shows the result of a repeating binary count at the decoder input when the outputs are always enabled. The outputs activate in a repeating sequence, from Y0 to Y3.
You will notice that the D inputs change exactly on the grid lines, but the Y outputs change slightly after. This is due to propagation delay, defined as the time between an As a decoder stimulus, we will define an increasing binary count on the D inputs. Highlight the input group by clicking in the Value column. Use the Overwrite Count tool- bar button to create an increasing binary count on the group, D[1..0]. Fill in the dialog box as shown in Figure 5.19 and click OK. The count is increased every 40 ns (2 20 ns), as shown in Figure 5.20.
Overwrite Count Button
FIGURE 5.20
Group Input with Binary Count
FIGURE 5.19
Overwrite Count Value Dialog Box
Fit in Window Button
FIGURE 5.21
Decoder Simulation with Enable Always Active
input change and the time an output changes in response to that input. In the EPM7128SLC84-7 CPLD, for which this simulation is created, propagation delay is about 7 nanoseconds. (The MAXPLUS II simulator accounts for the propagation delay in dif- ferent CPLDs.) Later simulations in this chapter will not necessarily show the delay, as the timing chosen may be very long compared to delay times.
To see the result of the enable input, highlight the G waveform from approximately 500 ns to 1 s by dragging the mouse along this part of the waveform. Overwrite the high- lighted part by clicking the Overwrite with HIGH button. When we run the simulation again, we get the waveforms shown in Figure 5.8.