Selected signal assignment statement A concurrent signal assignment in VHDL in which a value is assigned to a signal, depending on the alternative values of an- other signal or variable.
Conditional signal assignment statement A concurrent VHDL construct that as- signs a value to a signal, depending on a sequence of conditions being true or false.
In Chapter 4, we saw an example of how we can use VHDL to define the function of a 2-line-to-4-line decoder. For reference the description is replicated below, with the differ- ence that the input and output ports are defined as BIT rather than STD_LOGIC types. (This is sufficient for a combinational circuit like a decoder, as the only I/O (input/output) values required are ‘0’ and ‘1’. If we use BIT types, we do not require a reference to the IEEE library, as we do to define STD_LOGIC types.)
ENTITY decode1 IS PORT(
d1, d0 : IN BIT; y0, y1, y2, y3 : OUT BIT); END decode1;
ARCHITECTURE decoder1 OF decode1 IS BEGIN
y0 <= (not d1) and (not d0); y1 <= (not d1) and ( d0); y2 <= ( d1) and (not d0); y3 <= ( d1) and ( d0); END decoder1;
The above formulation has no enable input. If we wish to include the enable function, we must modify the entity declaration to include that input and change the signal assign- ment statements, as well. The new VHDL code is as follows.
ENTITY decode2 IS PORT(
d1, d0, g : IN BIT; y0, y1, y2, y3 : OUT BIT); END decode2;
ARCHITECTURE decoder2 OF decode2 IS BEGIN
y0 <= (not d1) and (not d0) and (not g); y1 <= (not d1) and ( d0) and (not g); y2 <= ( d1) and (not d0) and (not g); y3 <= ( d1) and ( d0) and (not g); END decoder2; K E Y T E R M S 5.1 • Decoders 167 Overwrite with HIGH Button ➥decode1.vhd ➥decode2.vhd
In addition to coding the Boolean expressions directly, we can use two types of concurrent signal assignments to create decoder circuits: the selected signal assign-
ment statement and the conditional signal assignment statement. Both the Altera
VHDL manual and the Help menu in MAXPLUS II have a section on “Golden Rules” for VHDL. The VHDL Golden Rules suggest that you should use a selected sig- nal assignment rather than a conditional signal assignment, if possible. This is because, in certain cases, the selected signal assignment uses the internal circuitry of the CPLD more efficiently.
The selected signal assignment has the form: label: WITH __expression SELECT
__signal <=__expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value, __expression WHEN __constant_value;
The signal indicated in the second line of the statement template is assigned one of several expressions, depending on the constant value of the expression in the first line. The label is optional. Examine the selected signal statement below:
circuit: WITH mode SELECT y <= q WHEN “00”
not q WHEN “01”, p WHEN “11”, ‘1’ WHEN others;
Signal y is assigned one of three values, p, q, or not q, depending on the status of a two-bit variable called mode. Note that the value of y for the case when mode “10” is not explicitly stated. This is covered by the last clause (WHEN others), which defines a default value for signal y of logic 1.
The following VHDL code implements a 2-line-to-4-line decoder using a selected sig- nal assignment statement.
LIBRARY ieee;
USE ieee.std_logic_1164.ALL; ENTITY decode3 IS
PORT(
d : IN STD_LOGIC_VECTOR (1 downto 0); y : OUT STD_LOGIC_VECTOR (3 downto 0)); END decode3;
ARCHITECTURE decoder OF decode3 IS BEGIN WITH d SELECT y <= “0001” WHEN “00”, “0010” WHEN “01”, “0100” WHEN “10”, “1000” WHEN “11”, “0000” WHEN others; END decoder;
The selected signal assignment statement evaluates input d. For every possible combi- nation of the 2-bit input vector, d, a particular value is assigned to the 4-bit vector, y. (For example, for the case d1d010 (210), the output y2is HIGH: y3y2y1y00100.)
The default case (“WHEN others”) is required because of the multivalued logic type STD_LOGIC_VECTOR. Since a STD_LOGIC_VECTOR can have values other than ‘0’ and ‘1’, the values listed for d don’t cover all possible cases. The default output (which will never occur if we only use ‘0’ and ‘1’ inputs) is chosen such that no output is active in the ➥decode3.vhd
5.1 • Decoders 169 default case. The default case would not be required if we chose to use BIT_VECTOR, rather than STD_LOGIC_VECTOR, since the listed combinations of d cover all possible combinations of a BIT_VECTOR. However, it is a good practice to include the default case, in order to account for all possible contingencies.
In order to include an enable input (g) in a decoder, we can increase the input vector size to include the g input, as shown in the following code.
LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY decode3a IS PORT( d : IN STD_LOGIC_VECTOR (1 downto 0); g : IN STD_LOGIC;
y : OUT STD_LOGIC_VECTOR (3 downto 0)); END decode3a;
ARCHITECTURE decoder OF decode3a IS
SIGNAL inputs : STD_LOGIC_VECTOR (2 downto 0); BEGIN
inputs(2) <= g; inputs(1 downto 0) <= d; WITH inputs SELECT
y <= “0001” WHEN “000”, “0010” WHEN “001”, “0100” WHEN “010”, “1000” WHEN “011”, “0000” WHEN others; END decoder;
To include g and d in a single vector, we create a signal called inputs, a vector with three elements in the sequence g, d(1), d(0). When assigning the d to the last two elements of inputs, we must be explicit about which elements of inputs we want to use. Since d only contains two elements and we are assigning them to two elements of inputs, we don’t need to list the elements of d explicitly.
We can use a selected signal assignment statement to evaluate all inputs, including g , and assign outputs accordingly. When g ‘0’, the decoder outputs are assigned the same as they were in the example without the enable input. The cases where g ‘1’ are covered by the others clause. In this default case, all decoder outputs are LOW (inactive).
Another way to include an enable input is to use a conditional signal assignment state- ment, which makes an assignment based on a Boolean expression. This template for the conditional signal assignment statement is:
__signal <= __expression WHEN __boolean_expression ELSE __expression WHEN __boolean_expression ELSE __expression;
The first Boolean expression in the statement is evaluated. If it is true, the correspond- ing expression is assigned to the signal. If false, the next Boolean expression is evaluated, and so on until a true Boolean expression is found. If none are true, the signal is assigned a default expression, listed last in the statement.
The VHDL code below implements the decoder with an active-LOW enable. If g is LOW, one decoder output activates, depending on the value of d. Note that the d inputs are defined as type INTEGER, rather than BIT_VECTOR or STD_LOGIC_VECTOR. In this situation, we don’t need to specify the number of inputs; the compiler automatically de- fines the required inputs d1 and d0 when fitting the design to the selected CPLD. Also, since d is of type INTEGER, we write its value in the selected signal assignment statement directly, without quotes.
LIBRARY ieee; USE ieee.std_logic_1164.all; ENTITY decode4g IS PORT( d : IN INTEGER RANGE 0 to 3; g : IN STD_LOGIC; y : OUT STD_LOGIC_VECTOR (0 to 3)); END decode4g; ARCHITECTURE a OF decode4g IS BEGIN
y <= “1000” WHEN (d=0 and g=‘0’) ELSE “0100” WHEN (d=1 and g=‘0’) ELSE “0010” WHEN (d=2 and g=‘0’) ELSE “0001” WHEN (d=3 and g=‘0’) ELSE “0000”;
END a;
MAXⴙPLUS II Report File
In the Altera Golden Rules, we are told to choose a selected signal assignment over a con- ditional signal assignment because it uses the CPLD resources more efficiently. How do we check this assertion? Is it always true? This information is stored in a MAXPLUS II
report file (rpt), which is created at compile time.
The compile process of MAXPLUS II goes on behind the scenes; until now we have not enquired about the result of this process. One of many functions of the compiler is to reduce the design information in a graphic or text file to a series of Boolean equations that can be programmed into a PLD.
For example, the report file decode3a.rpt, for the file that uses the selected signal as- signment, gives us the following information under the EQUATIONS heading.
** EQUATIONS ** d0 : INPUT; d1 : INPUT; g : INPUT; — — Node name is ‘y0’
— — Equation name is ‘y0’, location is LC117, type is output. y0 = LCELL( _EQ001 $ GND);
_EQ001 = !d0 & !d1 & !g; — — Node name is ‘y1’
— — Equation name is ‘y1’, location is LC115, type is output. y1 = LCELL( _EQ002 $ GND);
_EQ002 = d0 & !d1 & !g; — — Node name is ‘y2’
— — Equation name is ‘y2’, location is LC118, type is output. y2 = LCELL( _EQ003 $ GND);
_EQ003 = !d0 & d1 & !g; — — Node name is ‘y3’
— — Equation name is ‘y3’, location is LC120, type is output. y3 = LCELL( _EQ004 $ GND);
_EQ004 = d0 & d1 & !g;
Each output is designated as a node. Let us examine the equation of one node in detail so that we will know how to interpret the others.
➥decode4g.vhd
5.1 • Decoders 171 The Boolean format in the report file uses different operators than VHDL. They are as follows:
! = NOT & = AND # = OR $ = XOR
Thus, the equation given as _EQ001 = !d0 & !d1 & !gis equivalent to the Boolean expression _EQ001 d0d1g.
In the expression (y0 = LCELL ( _EQ001 $ GND);), equation _EQ001 is XORed with GND (logic 0) and applied to an LCELL (logic cell) primitive to yield y0. The LCELL represents one output of the CPLD. The XOR function is a way to either invert or not invert a logic function by setting one XOR input to GND (noninverting) or VCC (in- verting). Thus _EQ001 is applied to a CPLD output without inversion.
A comment in the report file indicates that y0 is assigned to logic cell LC117 (out of 128), which corresponds to pin 75 (out of 84) on the CPLD. Other equations are assigned to other LCELLs with other Boolean functions, as appropriate. Every pin number on the CPLD package is permanently connected to a specific LCELL. The compiler chooses the LCELL/pin assignments automatically; if we desire specific pin number assignments, we must assign them explicitly before compiling.
How does this compare with the report file for the design with the conditional signal assignment? If you examine decode4g.rpt, you will find that the Boolean equations are ex- actly the same. Thus, we can conclude that for a simple function, such as a 2-line-to-4-line decoder with enable, the two statement forms are easy enough for the compiler to interpret both in the most efficient way.