Summary: Ferroelectricity in a Layered Structure

7.6.5 Integrating Ferroelectrics and Semiconductors

The integration of ferroelectrics on semiconductors can be facilitated by using ferro-electrics with low crystallisation temperatures or by using buffer layers. When using ferroelectrics with low crystallisation temperatures the solution is efficient as there should be no degrading of the semiconductors transport properties. Initially, it was thought that the high temperature and chemical stability of the GaN-based semiconductors would min-imise inter-diffusion and allow them to have the high temperature perovskites deposited onto them. However, it was determined that this was not the case and that careful con-trolling of the semiconductors transport properties need to be done in order to monitor any change in them.

7.7 Summary: Ferroelectricity in a Layered Struc-ture

It has been theoretically derived that when depositing a ferroelectric layer on a semicon-ductor heterostructure, which has a dielectric layer of finite thickness, the spontaneous polarisation in the ferroelectric layer can be decreased in comparison to when it is in a capacitor, MFM, structure. This decrease in spontaneous polarisation is due to both the depolarisation field and incomplete charge compensation at the ferroelectric/dielectric interface. If a ferroelectric layer is deposited onto a semiconductor, whose channel to be modified is directly under the ferroelectric layer this decrease in polarisation is less prominent. But in the cases for semiconductor heterostructures where the channel that is modified is located a distance greater than 20 nm from the ferroelectric/dielectric interface these physical phenomenons have a greater impact on the decrease of the spontaneous polarisation.

When trying to use PZT as the ferroelectric gate with Al_0.3Ga_0.7N the depolarisation field is constrictively high. This is in large part due to the large dielectric constant of the PZT layer in comparison to that of Al_0.3Ga_0.7N. This depolarisation field alone can completely negate all of the spontaneous polarisation in the PZT layer until the PZT has a thickness greater than 1 µm. Due to the fact that depletion observations were made experimentally with a PZT layer of thickness 130 nm helped us understand that all phenomenon were not taken into account. It was necessary to include charge compensation in the derivation of the modified spontaneous polarisation. With this modification it was termed feasible to decrease the sheet resistance of the 2DEG by a factor three. This theoretically verified our experimental observation of a decrease in the electron sheet concentration by a factor of 1.5.

Since the developers of semiconductor heterostructures have already minimised the thick-ness of the dielectric layer, 20 nm, with a dielectric constant of approximately 10 it is more interesting to vary the ferroelectrics properties in order to minimise any changes in the spontaneous polarisation. The two ways to do this is by using a ferroelectric layer with a small dielectric constant or by using a thick ferroelectric layer.

Working with a ferroelectric layer of low dielectric constant is one approach to minimise the depolarisation field and conserve the spontaneous polarisation of the ferroelectric. This was done by experimenting with the co-polymer P(VDF/TrFE)(70:30). With the theory

164 CHAPTER 7. FERROELECTRIC GATE OPERATION

derived here it should be feasible to deplete the 2DEG with this layer as the reduction in spontaneous polarisation is less significant. However, the experimental results showed that it is possible to deplete the electrons in the 2DEG by poling the P(VDF/TrFE) layer without having long term retention of this depletion. This can be due to the fact that compensating charge is built up, with time, at the ferroelectric/semiconductor interface causing the elimination of all spontaneous polarisation in the ferroelectric layer.

Chapter 8 Conclusion

The present work directly demonstrates the ferroelectric gate operation and capabilities in the PZT/AlGaN/GaN and P(VDF/TrFE)/AlGaN/GaN systems, which constitutes a new step towards a GaN-based ferroelectric FET device.

8.1 Gate Operation

It was proven that once PZT had been deposited on AlGaN/GaN it was possible to pole the PZT and have it retain this polarisation. Hall measurements showed that the polari-sation of the PZT layer impacts the conductivity in the 2DEG, inducing local depletion of charge carriers in the 2DEG when it is poled negatively. More specifically, a (111) oriented sputtered PZT(40:60) ferroelectric gate, of 130 nm, on the Al_0.3Ga_0.7N heterostructure de-pleted the two dimensional electron gas with an increase of the sheet resistance by a factor of three, when poling the PZT layer with −40 V directly to the conductive cantilever used in a piezoresponse force microscope. This increase in sheet resistance was stable for more than three days and was the first successful observation of a PZT gate on a semiconductor heterostructure. More measurements can be done in varying the thickness and composi-tion of the PZT layer to get a better fundamental understanding of the PZT/AlGaN/GaN system before it becomes suitable for FeFETs. With improved quality of the PZT film and an optimised poling procedure one may expect a stronger depletion effect than that reported.

The ferroelectric co-polymer P(VDF/TrFE) (70:30) was investigated as a gate on the Al_0.3Ga_0.7N heterostructure, due to its low dielectric constant, =13. It was also of in-terest to investigate this ferroelectric because it has a low crystallisation temperature of 130^◦C which most semiconductors will be able to sustain, without any degradation to its properties. When the P(VDF/TrFE) was poled, with −30 V to a top gold electrode, the sheet resistance was modulated by a factor three. There was only short term retention of this modulation, possibly due to the increase of charge compensation with time until a full suppression of the spontaneous polarisation ocurred. Currently, this structure does not meet the demanding 10 year retention requirements necessary for FeFETs. One appli-cation, for this structure, is dynamic random access memory, DRAM, where the refresh rate necessary would be minimised, allowing for lower power consumption.

The Landau theory was combined with the concept of ferroelectric depolarisation field