Surface morphology and microstructure at the metal/3C-SiC interface

To further confirm the above assumption, a detailed structural view of the implanted 3C-SiC film can be helpful. TEM was used to observe the as-deposited metal/3C-SiC in-

terface. The samples were prepared with FIB-SEM utilising a standard lift-out technique, followed by low energy polishing.

Figure 4.12: TEM images for the as-deposited Ni/Ti/3C-SiC interface: (a) 1.5×1019

cm-3, (b) 4×1019 cm-3 and (c) 6×1020 cm-3.

As can be seen in Figure 4.12c, for the highest doped sample, even after the 1h 1375◦C PIA, there is still a great amount of line defects (highlighted with red dotted lines)

remaining in the top layer. Since these defects do not extend into the as-grown epilayer, they can be ruled out as stacking faults and are most likely lattice damages induced by the ion implantation. In [83], a similar amorphous layer was observed in nitrogen implanted 3C-SiC, and with a 1h 1350◦C annealing process, the amorphous layer depth and defect

density was found to decrease in more lowly doped samples, also observed here as seen in Figure 4.12a and 4.12b. According to the dopant position-dependent band bending theory,

the Schottky barrier elimination at the metal/3C-SiC interface then can be attributed to the dipole field created by the excessive lattice defects located near the interface. For the lowest doped sample, the defect density in the top surface layer was probably not high enough to flatten the barrier, and an additional heat treatment was necessary to bring the interface to a more suitable position, although some other mechanisms may also have occurred during the RTA.

Figure 4.13: AFM images for the metal/3C-SiC (6×1020 _cm-3_{) contact surface: (a)}

as-deposited, (b) 900◦C annealed, (c) 1000◦C annealed and (d) 1100◦C annealed.

Although the post metallisation heat treatment is found not to change the carrier transport mechanism, it successfully reduces ρc values, thus is still vital in achieving

low resistivity Ohmic contacts. As such, it is also studied here for the highest doped sample who gives lowest ρc values. AFM results shown in Figure 4.13 indicate a surface

degradation with the increasing annealing temperature, most likely caused by stronger silicide reactions.

ρc values of the as-deposited contact and those annealed (800◦C, 900◦C, 1000◦C and

1100◦C) on the 6 ×1020 cm-3 doped sample are compared in Figure 4.14. It shows a continuous reduction of contact resistivity from 3 ×10−5Ω.cm2 to 9×10−6Ω.cm2 with increasing annealing temperature up to 1000◦C, after which the value increases to 2.5× 10−5Ω.cm2 at 1100◦C.

Figure 4.14: Contact resistivity dependence on the PMA temperature for the 6×1020

cm-3 doped sample.

In Figure 4.12 the as-deposited contact interface demonstrates three distinctive layers: Ni, Ti and 3C-SiC. After 900◦C annealing (see Figure 4.15a), however, the Ni layer diffused

Figure 4.15: Metal/3C-SiC (6×1020 _cm-3_{) interface structure evolution with the heat}

analysis, the region formed by dark lumps is nickel- and silicon-rich, namely most likely a nickel silicide layer. Along with the dark lumps there are some small bright dots, which were found to be carbon-rich. These carbon clusters were commonly found before inside 4H- and 6H-SiC silicide [117,118] and were considered to increase the interfacial net carriers, helping to reduce the contact resistivity. With the annealing temperature further increased to 1000◦C (Figure 4.15b), the Ti interlayer became less noticeable and a series

of void (highlighted by red dotted circles) emerged along it. These vacancies are caused by silicon diffusion into the nickel (Kirkendall Effect) and will not have an impact on the contact resistivity, although they are harmful in terms of contacts reliability [119]. The small carbon clusters spotted previously are shown to expand in Figure 4.15b, which can be explained by the further reaction of Si with Ni. This further increases the interfacial carrier concentration, leading to a resistivity drop from 900◦C to 1000◦C. At 1100◦C, even

more severe carbon clustering is observed (Figure 4.15c) with large carbon crystallites formed. It is hypothesised that the extra active donors generated could be high enough that Coulomb scattering effects start to dominate and increase the contact resistance.

4.4.4

Silicide phase at the metal/3C-SiC interface

The TEM and EDX results in last section reveal the existence of a ≈ 150 nm silicide layer below the interface, indicating a strong reaction between metal and 3C-SiC during the PMA. In this section, XRD is applied to further explore the details of the silicide.

High-resolution XRD was performed using a Panalytical X’Pert ProMRD equipped with a 4-bounce hybrid monochromator giving pure Cu K 1 radiation and a solid-state Pixcel detector, the wavelength was 1.540598 ˙A. The 3C-SiC(200) peak was aligned to maximise the intensity and minimize the full-width at half-maxima (FWHM). 2θ −Ω “powder” scans were measured between 35 and 55 2θ degrees and the resultant spectrums for as- deposited contact and those annealed from 500◦C to 1100◦C are shown in Figure 4.16.

Figure 4.16: XRD measurements of metal/3C-SiC (6×1020 _cm-3_{) interface after various}

temperatures PMA.

As can be seen, between 500◦C and 600◦C, a coexistence of Ni2Si(121) and Ni31Si12(300)

are observed. While the Ni31Si12(300) peak gradually vanishes at higher temperature,

readily formed at 600◦C and no other phases noticeable above that temperature, the

Ni2Si(002) phase enhancement can be one of the reasons behind the contact resistivity

drop from 800◦C to 1000◦C. The Ti interlayer should have reacted with 3C-SiC forming

TiC or Ti3SiC2 [120], but no products are observable probably because the 30nm Ti layer

is too thin.

4.5

Summary

In this chapter, the formation of Ni/Ti Ohmic contacts on nitrogen heavily implanted 3C- SiC layer are investigated using both electrical and physical characterisation. Temperature dependent I-V measurements reveal the unique inherent thermally stable feature of 3C- SiC Ohmic contacts, which is explained by the elimination of Schottky barrier at the metal/3C-SiC interface. The accumulation type Ohmic contact is possible with 3C-SiC due to its relatively high electron affinity of 3.8 eV and will be difficult to reproduce on 4H- SiC who has a much lower value of 2.9 eV. Relating TEM results to the literature, dopant and defect-induced dipole field was considered to have caused severe band bending at the metal/3C-SiC interface, and should be the main cause of the temperature independent

ρc values. As-deposited Ohmic contacts are particular attractive from a fabrication point

of view, since it not only reduces the thermal budget but also eliminates the potential harms which the contact annealing process can induce to other sensitive device features, such as Schottky and MOS interface. The lowest as-deposited ρc value is already quite

low, around 2×10−5Ω.cm2 obtained for the highest doped sample. However, there had been suggestions that the SiC contact resistivity has to be less than 1 × 10−5Ω.cm2, otherwise the advantage of the reduction in specific on-resistance over Si power devices will be nullified [17]. As a consequence, an extra contact annealing had to be applied to further reduce ρc, and the lowest value is ∼ 1×10−6Ω.cm2 obtained for the 6×1020

cm-3 _{doped sample annealed at 1000}◦_{C for 1minute. The effect of thermal treatment}

after contact metallisation was also examined. XRD results indicated an enhancement of the Ni2Si(002) phase for annealing temperatures above 600◦C, which may have helped

to reduce ΦB. However, it is considered that the reduction of contact resistivity up

to 1000◦C should be mainly caused by the increment of interface carbon clusters with

Chapter

5

Study on 3C-SiC/SiO₂

MOS Interface

In 1914, Thomson may have been the first to postulate the existence of field-effect [121], which describes the phenomenon that, with an external electric field being applied on a semiconductor surface, the concentration or even polarity of free carriers in that region can be altered. In such a way that the current conduction can be modulated and devices working on this principle are called field-effect transistors (FET). The very early FETs were proposed by Lilienfeld [122] and Heil [123] in 1930s, which included a MOS feature in the device structure. “MOS” is short for metal-oxide-semiconductor, one of the most widely seen features in integrated circuits today. Back then, these devices were suffering from unstable electrical performance due to the poor semiconductor/insulator interface (more frequently called MOS interface), thus did not draw much attention from the in- dustry. The insulator in a MOS system was introduced to protect the semiconductor surface from potential damage caused by the electric field, while on the other hand, the

amount of charge built up at the MOS interface due to the poor processing environment led to the shielding of the field-effect, and cause the device to malfunction [96]. Around the same period, Bipolar Junction Transistors (BJT) were invented, and proved to be much more reliable since they do not have a MOS interface. As a result, BJT technology dominated the transistor market for quite a long time, until 1970s, when the computer industry started to develop. Computer microprocessors and memories favour the idea of fabricating multiple transistors on a single chip rather than discrete transistors, since more devices and therefore more operations per unit area can be achieved in this way [124]. The features of MOSFET technology such as low fabrication cost, large yield, and partic- ularly, improving performance with smaller dimensions seemed very attractive. Also, the MOS interface quality had been greatly improved by Kahng and Atalla, by using Si as the substrate and thermally growing oxide on top of it [125]. In spite of that, MOSFETs have been mainly used for low power applications, due to the rapidly increasing of devices resistance with voltage and operating temperature. The adoption of WBG semiconduc- tors enables MOSFETs to be used in power electronics applications with much higher power levels. While the Si/SiO2 interface has been intensively studied and the technology

is very mature, the SiC/SiO2 interface is still an active topic, revealing many challenges.

We will now describe the operation principles of MOS devices and discuss trap models developed for the MOS interface. Previous efforts for improving the SiC/SiO2 MOS inter-

face are also discussed. Finally, commonly used MOS characterising tools are introduced, and applied to the 3C-SiC/SiO2 interface.

5.1

MOS Technologies: Theories and Applications