Switching architectures

The first of presented architectures is based on output queuing and depicted in Fig. 2.

Based on [1], we assumed that WDM input signal consists of 4 wavelengths: λ1… λ4.

First QD-SOA changes wavelength so that packets enter the branch that correspond to the proper output.

Fig. 2. Output queued switch architecture with the optical buffer.

Switching control should be easy to implement and done in a very fast way. To achieve maximum simplicity, we use counters as the main component in the scheduling process. We assume that every output has its own counter that shows the current buffer state (a queue length). An example of the counter is shown in Table 1. The scheduling algorithm is described below.

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Output number 1 2 3 4

Delayed packets [counters] 3 2 2 0 Tab.1. An array representation of counters.

There are n counters; each of them shows how many packets are in the queue to the given output. In the beginning we started from resetting all counters. In every time slot we decrease all counters by one (if counter > 0) and check if any packet appears at any input. If a new packet appears we check the counter, determine a proper delay, and increase the counter by one. In every time slot we may begin to search from the input next to the last searched, so that every input will have the same priority. At the end of every time slot, we decrease all counters by one.

Counter-based scheduling algorithm:

1. In the first time slot set all counters on zero

2. Set i=0,

3. Check if there is a new packet in i-th input

4. If there is a new packet,

a. Determine its delay by counter value.

b. Change counter value:

new counter value = old counter value + packet length

5. If not, i = i+1 and go to step 3. If all inputs are checked, go to step 6

6. Set QD-SOA’s,

7. Decrease all counters by one

8. Go to next time slot and start from step 2.

The presented architecture has many advantages. First of all, it is an output buffering switch which is characterized by the best queuing properties. Using 4 internal wavelengths for one input wavelength, we can obtain the 15 time slots buffer in 2 QD- SOA sections. Adding one more QD-SOA extends buffer to 63 time slots (Fig. 3). The proper buffer size depends on traffic conditions as well as the size of the switch.

One of the interesting functions of QD-SOA is that it may copy one signal to more than one wavelength, so packets can be distributed over many outputs. As such we are able to apply the multicast feature in this architecture. There is also no need to segment packets into smaller fixed-size cells.

Other interesting architecture is depicted in Fig 4. Buffer size is equal to 15 time

slots. We assume that input WDM signal consists of 4 wavelengths: λ1… λ4 and is

introduced to QD-SOA. Every control signal convert input wavelength to one of four wavelengths so that the optical signal goes through the relevant MUXs output and reaches the next QD-SOA. The second QD-SOA converts the signal to achieve desirable delay. After the buffering stage, a switching should be performed. It can be accomplished by combining an AWG and a QD-SOA.

Fig. 4. Switch architecture with parallel, optical buffer.

The main problem arises when 2 or more packets from the same input go to different outputs but arrive to the same QD-SOA simultaneously. Counter-based scheduling algorithm doesn`t take it into consideration and the packet contention appears. In the proposed “parallel buffer” architecture, there will be no contention in the buffering stage but could appear in the switching stage.

Let us consider the example shown in Figures 5-7. In x-th time slot only packet P1,2

(from the first input to the second output) enter the switch. It goes through the third

branch and then enters the first delay line. Six time slots later, packet P1,4 enters the

switch. The route for this packet within the buffering stage is shown in Fig.6. In (x+8)-th. time slot both packets enter the switching stage. QD-SOA will not serve two signals from the same input at the same time. Contention will occur because this is not possible to

convert e.g. λ1

I

and λ1

II

simultaneously in one QD-SOA device. Of course, it is possible that more than 2 packets will compete in the QD-SOA. This situation is analogous to that considered earlier and will not be further discussed.

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Fig. 5. Packet P1,2 enter the switch in x-th. time slot.

Fig. 6. Packet P1,4 enter the switch in (x+6)-th. time slot.

Fig. 7. Both packets leave buffering stage at the same time slot and packet contention appears on the input of the third QD-SOA

To overcome this problem we propose the following solutions. One of them is to use more internal wavelengths (hardware dependent); the second one is more sophisticated and will be described below.

We assume that packets are of fixed size and their duration is one time slot. Every input has its own array, where the proper delay is computed. When the packet enters the switch and its delay is set, it is marked by “X” in a relevant time slot of the array. At the same time we should prevent packet contention from the same input, so we mark “F” in all other cells corresponding to this time slot. Next, we are searching for the next free

time slot, which we can sent packet to this output and mark it by “P”. Then we mark that this time slot to given output is busy now and shouldn`t be used by other inputs Appropriate pointers are set on the next empty field. At the beginning of the next time slot, all values are moved one step left. Fifteen time slots array for the first and the second input in some x-th. time slot is shown in Tab. 2 and Tab. 3, respectively.

Output/TS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

1 B F F X B B P

2 P F F F

3 F X F P

4 X F F P

Tab. 2. Time slot occupancy for the first input

Output/TS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15

1 X B F B X B P

2 F P F F F

3 F P _{B F} F

4 F B X X F P

Tab. 3. Time slot occupancy for the second input

X – in this time slot, a packet leaves the buffer

F – this time slot is forbidden for this input because another packet from this input leaves the switch.

B – indicates that some other input uses this time slot

P – points to the first time slot in which we can sent packet to relevant output

The parallel buffer architecture has many advantages. First of all, we can implement 15 time slots buffer using limited number of QD-SOA sections. This is very important in optical domain systems because of optical signal to noise ratio. Total number of QD-SOA is 5 but signal has to go only through 2 QD-SOA stages. We have assumed that an input signal consist on w = 4 different wavelengths. It is worth noticing that the number of input wavelengths depends on QD-SOAs and will be higher as technology will be more

mature. The total size of the buffer depends on w and is equal to w2-1. Presented buffer

architecture could be more cascaded. An example of the buffer of size 31 is depicted in Fig. 8.

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Fig. 8. Switch architecture with parallel, optical buffer, b=31