Synchronous Systems

In the design phase, we have determined the location of the partial area onto the FPGA fabric. We have to define this location in GoAhead. This can be done by using the GUI or scripting language. If the scripting language is used, we can use the standard selection commands, as in Listing 5.3.

After we specified the location of the partial area in GoAhead, we connect the BELs within the partial that contain a clock pin to the clock network. This way, we can run synchronous circuits within the partial area. The way we implement the clock routing towards the partial area is similar as in [1]. All the BELs that contain a clock pin in the partial area are connected to the clock network. By doing this, we make sure that all the clock paths towards all the BELs in the partial area are routed in the static area.

The CommandConnectClockPins

The command that we use in GoAhead to connect all the BELs in the partial area is ConnectClockPins. In Listing 5.5, the syntax of this command is shown. In the following, the parameters of the commandConnectClockPinsare described.

• ClockPin: This parameter specifies the name of the clock pin.

• BELs: This parameter specifies the names of the BELs that must be connected to the clock net. The names of the BELs are specified in regular expression format.

• ClockNetName: This parameter specifies the name of the clock net. The clock pins will be connected to this clock net.

The command ConnectClockPins connects only the BELs in the currently se- lected area. Therefore, we first have to select the tiles that belong to the partial area before usingConnectClockPinscommand, as illustrated in Listing 5.5.

The TCL Commands

The command ConnectClockPins generates a TCL script that connects the clock pins to the clock net. In Listing 5.4, the TCL commands are shown that connects the

56 CHAPTER 5. IMPLEMENTATION clock pin from a single FF to the clock net. The command create cell instantiates one or multiple cells in the current design [33]. We instantiate an existing cell from the library. The library cell of a FF is named FDRE. FDRE is a D-type FF. These types of FFs have data, clock enable, and synchronous reset inputs and data output. We can place a cell on the FPGA fabric with the commandplace cell. Once we have placed the cell, we have to define the clock pin on the cell. We can define a pin on a particular cell with the commandcreate pin. Finally, we connect the clock net to the defined clock pin with the command connect net. These four TCL commands are repeated for all the BELs that match the regular expression of the parameterBELs in the command ConnectClockPins. For example, in Listing 5.5, all the FFs in the partial area are connected to the clock net.

1 # c o n n e c t c l o c k pin to c l o c k net 2 c r e a t e _ c e l l -r e f e r e n c e F D R E S L I C E _ X 5 6 Y 4 9 _ D F F 3 p l a c e _ c e l l S L I C E _ X 5 6 Y 4 9 _ D F F S L I C E _ X 5 6 Y 4 9 / DFF 4 c r e a t e _ p i n -d i r e c t i o n IN S L I C E _ X 5 6 Y 4 9 _ D F F / C 5 c o n n e c t _ n e t -h i e r -net c l o c k _ 5 0 M H z 6 -o b j e c t s { S L I C E _ X 5 6 Y 4 9 _ D F F / C }

Listing 5.4: The TCL commands to connect the clock net to the clock pin.

1 # s e l e c t the p a r t i a l a r e a 2 C l e a r S e l e c t i o n; 3 S e l e c t U s e r S e l e c t i o n U s e r S e l e c t i o n T y p e= P a r t i a l A r e a ; 4 5 # c o n n e c t c l o c k p i n s in the c u r r e n t s e l e c t e d t i l e s 6 C o n n e c t C l o c k P i n s 7 C l o c k P i n= C 8 B E L s=[ A - D ] FF 9 C l o c k N e t N a m e= c l o c k _ 5 0 M H z 10 F i l e N a m e= s t a t i c _ c o n n e c t _ c l o c k p i n s . tcl 11 A p p e n d= F a l s e 12 C r e a t e B a c k u p F i l e= T r u e ;

Listing 5.5: In GoAhead, the command ConnectClockPins is used to connect all the clock pins of the BELs to the clock net in the partial area.

5.2. IMPLEMENTING THE STATICSYSTEM 57