System Bus Clocking

To establ ish the 25 -ns bus cycle time, analog models of the interconnect were developed and analyzed for 5.0-V CMOS transceivers. Assuming an edge- to­ edge data transfer scheme, the modelers evaluated the timing from a driver transition to its settled sig­ nal, including clock input to driver delay, receiver setup time, and module-to-module clock skew. The cycle time and the data transfer width were com­ bined to determine compliance with l ow latency and bandwidth. Further analysis revealed that the second-level cache access timing was critical for performing shared-memory state lookups from the bus. One solution to this problem was to store duplicate tag values of the second- level cache. This was evaluated and found to be too expensive to implement. However, the study d id show that a duplicate tag store of the CPU's primary data cache had a performance advantage and was affordable if implemented in the CPU module's bus interface unit (BIU) chips.

To evaluate second-level cache access timing, a survey of SRAM access times, density, availabil­ ity, and cost was taken. Results showed that a I MB

cache using 12-ns access time SRAMs was optimal. With a 12-ns access time SRAI\1, the critical timing could be managed through the design of the BIU

chips. The SRA!vl survey also showed that a 4MB second- level cache could be planned as a fol low-on boost to performance, as SRAM prices decl ined . Trace-based performance simulations proved that these cache sizes satisfied performance goals of 125 VUPs. This clock rate requ ired a bus stall mecha­ nism to accom modate current DRAI\1 access times in the memory subsystem, which will enable future enhancements as access times are reduced .

The system bus clocks are distribu ted as posit ive emitter-coupled level (PECL) d ifferential signals; four single-phase clocks are available to each slot. Each module receives, terminates, and capacitively couples the clock signals into noninverting and inverting PECL-to-CMOS level converters to provide four edges per 25-ns clock cycle. System bus hand­ shake and data transfers occur from clock edge to

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FUTUREBUS+ B R I D G E

BUFFER BUFFER

MAI LBOX MAILBOX

BIU CPU 2 MODULE NVRAM MICROCONTROLLER 32KB DECCH I P S E RIAL 2 1 064 CPU PROM BACKUP CACHE 1 46 BIU CPU 1 MODULE NVRAM MICROCONTROLLER 32KB DECC H I P SERIAL 21 064 CPU PROM BACKUP CACHE 1 46 Bus CLOCKS B I U MEMORY MODULE 1 DRAMS 280 DRAM CONTROL BIU MEMORY MODULE 2 DRAMS 280 DRAM CONTROL BIU MEMORY MODULE 3 DRAMS 280 DRAM CONTROL BIU

Figure 3 DEC 4000 AXP System Bus

M E MORY MODULE 4 DRAMS 280 DRAM CONTROL B I U ...J 20 MM ifJ

clock edge and utilize o ne of two system bus clocks. A custom clock chip was implemented to provide p rocess, voltage, temperature, and load (PYTL) regulation to the pair of application-specific i ntegrated circu it (ASJC) chips that compose each Blli. The clock chip achieves module- to-module skews of less than 1 _ns.

Our search for a clock repeater chip that could

m inim ize module-to-module skew and c h ip - to­ chip s kew on a module, and yet d irectly drive high

fan-out ASIC chips with Ci\'lOS- level clocks, led us to Digital's Semiconductor Operations <_;roup. Such

a chip was in design ; however, it was tailored for use at the DEC _{6000 system} bus frequency The Semiconductor Operations Group agreed to change the ch ip to accommodate the DEC _{4000 AXP}

system bus frequency

1/0 Bus TeclJnology

Because of technology obsolescence, l/0 b uses have a 21-year l i fe cycle divided into 3 phases. During t he first 7 years of acceptance, peripherals and appl ications are developed and supported. Sustained acceptance takes hold in the next 7 years as peripherals and applications are enhanced . In the l ast 7 _{years, a phase out or migration of periph­} erals and appl ications occurs. For the DEC ₄₀₀₀ AXP

systems, our first priority was selection of a n open expansion 1/0 bus in the fi rst third of its l i fe cycle. In addition, we wanted to select an open I EEE _stan­

dard bus that wou ld attract third-party developers to provide 1/0 solu tions to customers. The fol low­ ing prioritized criteria were established for the selection of a new I/0 bus:

I. Open bus that is an accepted i ncJu ' try standard in the beginning third of its life cycle

2. Compatibil ity with Alpha AXP architecture

3. Minimum data rate of l00Ml3/s

4. Scalable features that are ten­

sible through arch i tecture (e.g., bus width) , and/or through technology improvements (e.g. , semico nductor device perfor m ance and integration)

5. Minimum 64-bit data path

6. Support of bridges to other 1/0 buses

7. Minimal interoperabil i t y problems between devices from different vendors

After examination of several I/0 buses that satis­ fied these criteria, the Futurebus+ was selected . At the time of our invest igation, however, the

Futurebus+ specification was in development by

the IEEE _{and a wide range of interest was evident}

throughout the indust ry. By p roviding t he right sup­ port to the Futurebus+ commit tee, Digital was in a p osition to help stab i l i ze and bring the speci fica­ tion to com plction.

A D igital team represented the project's i nterests

on the IEEE _{PH96.2 Specification Committee and}

proposed standards as the DEC 4000 AXP system design evolved. This team ach ieved its goa l by help­ i ng the ! EE L Committee define a profile that enabled Futurebus+ to operate as a high-perfor­ mance I/0 expansion bus. To m itigate sched u le i mpact due to instability of the Fu turebus+ specifi­ cations, t he I/O module·s Futurebus+ interface was

cted to accommodate changes tl1rough a more d iscrete, rather t han a highly i n tegrated implementation. Compliance with the Futurebus+ specifications influenced most mechanical aspects of the module compartment design, as is evident from the centerplane, card cage, modu le construc­

tion and size, and po\vtr supply voltage specifica­

tions and implementations.