Miniaturization of electronics and increase of its complexity brings into focus an option of vertical integ- ration using 3D interconnection technologies. A parasitic resistance and capacitance of the conductive interconnecting paths do not decrease with the transistor dimensions. Many commercial applications (typically smart-phones) require a fast interconnection between the complex digital blocks as for ex- ample CPU and a memory. A solution coming from industry is 2.5D or 3D integration - vertical integra- tion of the integrated circuits. The 2.5D technology uses the interconnection technology for expanding the high density interconnection arrays using silicon interposers. One example of a 2.5D vertical chip integration is shown in Figure4.10.
Figure 4.10: An example of a 2.5D vertical chip integration used in a commercial high performance FPGA [58]. A dense array of IO pads of a complex digital chip is expanded using a silicon interposer. The entire assembly can be finally connected to a PCB by a cheap BGA technology.
The integration of many functional layers in one assembly for a relatively low cost by vertical integ- ration represents an attractive option not only for industry, but also for HEP experiments. One possible implementation of this technology in the pixel FE chips is separating the analog and the digital part of the pixel and integrating them vertically. The same procedure can in principle be used for other com- ponents of a pixel module like opto-module or cooling capilars as shown in Figure4.11. Apart from reducing the pixel size, this solution brings additional benefits. Since the sensitive analog part is integ- rated on a physically different silicon chip than the noisy digital part, the crosstalk between these two parts will be minimized. It allows the fabrication of different tiers at different foundries and possibly in different technologies. In an extreme case, the analog pixel can be fabricated in cheaper 130 nm technology, but the digital part can be made in 65 nm technology.
4.3.1 Aspects of vertical integration
In spite of the simplicity of the idea of vertical integration, a practical implementation is rather difficult. Vertical integration of the integrated circuits involves non-standard processing steps. One of the critical steps is electrical connection from the top side of the chip to the bottom side, which is implemented by a Through Silicon Vias (TSV).
4.3 Vertical integration
Figure 4.11: An idealistic picture of a 3D integration of various layers of pixel detector.
TSV can be formed in two ways:
Via first - TSV is processed on a blank silicon wafer within first few steps of the CMOS process. High temperature operations can be used to make the TSV. A via first TSV technology must be compat- ible with the CMOS process and therefore it can only been done in several silicon foundries.
Via last - TSV is made after a full CMOS processing. In the pixel FE chips, it is often needed to transfer just a few (1 or 2) conductive paths from the top to the bottom side of the chip. The TSV pitch is therefore relaxed and the TSV can be produced at a different factory than in which the electronics has been fabricated.
Vertical integration of the pixel electronics requires a high density interconnection technology. Inter- connection is usually done by thermocompression. The thermocompression interconnection technology involves deposition of metallic (Cu) pads on both wafers to be interconnected. The connection is es- tablished by bringing the wafers together and applying a pressure at high temperature. The wafers are then connected at the exposed Cu pads by thermal vibrations of the Cu atoms. This connection has a very small resistivity (comparable with Cu) and a small pitch of the order of a fewµm can be achieved. Unlike the bump-bonding technology, once the chip assembly is interconnected, it can not be reworked if needed.
Fabrication of large silicon chips routinely achieves a yield of 50-80% (depending on complexity). When two tiers are fabricated with a non-standard process (including TSV) and are interconnected, the yield can easily drop to very low levels. Yield optimization and design for testing is of the central importance in the design of the 3D electronics. Complex integrated circuits consume and also dissipate large power. The ability to dissipate heat is proportional to the surface area of the silicon chip. When integrating several tiers on top of each other, the dissipated heat can easily increase several times, while the surface area radiating heat remains constant. An unequal power consumption between different tiers can lead to a thermal stress, which can eventually break the connections between the tiers.
To summarize, the design of 3D electronics requires to pay an increased attention at: • Yield optimization of each tier
• DFT (Design For Testing)
• Equal power consumption between tiers to minimize thermal stress • Minimization of power consumption
4.3.2 FE-TC4
FE-TC4 is a prototype chip designed in 130 nm technology allowing vertical integration. The design of this chip is based on the design of the FE-I4 and has been submitted in April 2009 within a MPW run organized by the HEP 3D consortium [59], lead by Fermilab. A micrograph of one reticle of the silicon wafer with multiple designs is shown in Figure4.12(a).
Figure 4.12: A micrograph of a silicon wafer (a) shows one reticle containing multiple designs. Red rectangles mark designs belonging to the FE-TC4 project. A concept of vertical integration of analog and digital tier of the FE-TC4 chip is show in Figure (b).
Analog and digital parts of the pixels are located on different silicon dies designed to be vertically integrated after the electronics is processed as shown in Figure4.12(b). Both tiers were processed on the same wafer in the way that they can be combined with their counterparts from another wafer. This particular technology uses the via first TSV with the via diameter of 1.2µm and via pitch of 2.5 µm, and depth of about 10µm. Both tiers have been tested separately (before interconnection). Their electrical parameters are comparable with the FE electronics integrated on the FE-I4. However, certain difficulties have been faced in order to produce a full 3D assembly, which has been finally delivered for testing in late 2012. More details about the FE-TC4 can be found in [60], [61].