Each transfer to or from an off-board address causes a VMEbus access cycle. The VMEbus defines an arbitration mechanism to arbitrate for bus mastership. The CPU board includes
• a VMEbus arbiter so that it may act as slot-1 system controller; • a VMEbus requester so that it may access external VMEbus resources.
3.16.1 Single-Level VMEbus Arbiter
The CPU board contains a single level arbiter which can be enabled or disabled by software (see the FORCE Gate Array FGA-002 User’s Man-
ual). No additional control of the arbiter is required.
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IMPORTANT • The arbiter of the FGA-002 will not be set automatically by hardware when detecting slot-1 by switch setting or auto-detection. It must be enabled by software if the CPU board is system controller (e.g., FGA Boot enables the arbiter automatically). For more information on the FGA-002 arbiter, please see the FORCE Gate Array FGA-002 User’s
Manual.
• In accordance with the VMEbus specification, the arbiter must be enabled if the CPU board is located in the slot 1 of the VMEbus back- plane. It must be disabled if the CPU board is located in any other slot. • When the on-board single-level VMEbus arbiter is enabled, all other VMEbus masters (if any) must request VMEbus mastership using only bus request level 3 (BR3* signal). Otherwise, they are not recognized by the SYS68K/CPU-60.
3.16.2 VMEbus Requester
The SYS68K/CPU-60 includes a VMEbus requester so that it may access external VMEbus resources.
Request (arbitration) level selection
The request level is either selected automatically or by switch setting: • If the SYS68K/CPU-60 detects slot 1, the request level 3 will automat-
ically be used.
• If the SYS68K/CPU-60 does not detect slot 1, the request level is switch selectable (by SW6-3 and SW6-4: default “OFF OFF = level 3 (BR3*)”, see page 12).
For a detailed description of the slot-1 detection, see section 3.17 “VME- bus Slot-1” on page 86.
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IMPORTANT Note that the selection of the VMEbus request level has no effect upon the VMEbus arbiter located in the FGA-002.
3.16.3 VMEbus Release Modes
The CPU board provides several software-selectable VMEbus release modes to release VMEbus mastership. The bus release operation is inde- pendent of the fact whether the on-board VMEbus arbiter is enabled and independent of the VMEbus arbitration level. Easy handling and use of the VMEbus release modes is provided by the FGA-002.
Before the bus is released a read-modify-write (RMW) cycle in progress is always completed.
VMEPROM The VMEPROM ARB command sets the VMEbus release modes (see section 6.5.1 “ARB – Set the Arbiter of the CPU Board” on page 136). Each row of the following table lists which of the VMEbus release modes described below can be used simultaneously (ROR and RAT are always enabled):
Table 48 Valid configurations for VMEbus release modes
Config.
Release
mode Enabled VME is released
1. REC, ROR, RAT, RBCLR Yes Always Always Don’t care Every cycle 2. REC ROR RAT RBCLR No Always Always No
On BRx* active or after timeout
3. REC ROR RAT RBCLR No Always Always Yes
On BRx* active, after timeout or on BCLR* active
Hardware VMEbus Arbitration
Release Every Cycle (REC)
The REC mode causes a release of VMEbus mastership after every VMEbus transfer cycle has been completed. A normal read or write cycle is terminated after the address and data strobes are driven high (inactive state). A read-modify-write cycle (RMW) is terminated after the write cy- cle is completed by the CPU, through deactivation of the address and data strobes. If the REC mode is enabled, all other bus release functions have no impact ("don’t care").
The REC mode is only for CPU cycles with accesses to the VMEbus and not for cycles initiated by the on-board DMA controller.
Programming of the REC mode is described in the FORCE Gate Array
FGA-002 User’s Manual.
Release on Request (ROR)
The ROR mode applies only to CPU cycles to the VMEbus and not for cycles initiated by the FGA-002 DMA controller.
In these cases bus mastership is released when another VMEbus board re- quests bus mastership while the CPU board is the current bus master. For these purposes, the FGA-002 DMA controller can also be the requester causing such a bus release.
The ROR mode cannot be disabled, but it is programmable how long the CPU stays VMEbus master in spite of a pending bus request.
Programming of the ROR mode is described in the FORCE Gate Array
FGA-002 User’s Manual.
Release After Timeout (RAT)
After every VMEbus access, a 100 µs timer within the FGA-002 starts running. When the timer runs out the CPU board automatically releases its VMEbus mastership. The purpose of the timer is to hold the VMEbus for a short time after every VMEbus transfer, so that the overhead of VMEbus arbitration will be avoided if the CPU makes another VMEbus request within this time period.
The timer is only effective for CPU cycles to the VMEbus and not for cy- cles initiated by the FGA-002 DMA controller. In these cases it is restart- ed after every VMEbus access, but not before the ROR timer has expired. Therefore, the actual time in which the CPU board holds the bus is ap- proximately equal to the programmed ROR delay time (see above) plus 100µs. This function cannot be disabled.
Programming of the RAT mode is described in the FORCE Gate Array
FGA-002 User’s Manual.
Release on Bus Clear (RBCLR)
The RBCLR mode is only effective for CPU cycles to the VMEbus and not for cycles initiated by the FGA-002 DMA controller.
The RBCLR function allows the VMEbus mastership release if an exter- nal arbiter asserts the BCLR* signal of the VMEbus. This function then overrides the ROR function timing limitations.
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Programming of the RBCLR mode is described in the FORCE Gate Ar-
ray FGA-002 User’s Manual.
Release When Done (RWD)
The DMA controller within the FGA-002 can also become VMEbus mas- ter. It always operates in transfer bursts (maximum 32 transfers). The bus is always released after completion of such a transfer burst. The other bus release functions are for CPU mastership to the VMEbus only.
Release on ACFAIL (ACFAIL)
If the CPU board is programmed to be the ACFAIL handler for the VME- bus system and if the ACFAIL* signal from the VMEbus is asserted, the CPU will not release the VMEbus if it is already the VMEbus master. That is, REC, ROR, RAT, and RBCLR do not operate in this case. If the board is not ACFAIL handler and the ACFAIL* signal is asserted, the board will release the VMEbus immediately.
3.16.4 VMEbus Grant Driver
If the CPU board detects itself being plugged in slot 1 (see below), it will automatically use bus grant level 3 (BG3*) and drive the 3 remaining bus grant signals (BG0*, BG1*, and BG2*) to a high level.