Wire model?

Today, the longest wire on a VLSI chip might be 2cm Today, the longest wire on a VLSI chip might be 2cm Today, the longest wire on a VLSI chip might be 2cm Today, the longest wire on a VLSI chip might be 2cm which has “time of flight” of ~130ps assuming

which has “time of flight” of ~130ps assuming which has “time of flight” of ~130ps assuming

which has “time of flight” of ~130ps assuming εεεε_SiO_SiO_SiO_SiO2222

= 3.9

= 3.9 = 3.9

= 3.9 εεεε₀₀₀₀

If the signal rise/fall time is longer than the time of If the signal rise/fall time is longer than the time of If the signal rise/fall time is longer than the time of If the signal rise/fall time is longer than the time of flight we can model wires as a distributed RC network.

flight we can model wires as a distributed RC network. flight we can model wires as a distributed RC network.

flight we can model wires as a distributed RC network.

Longer wires or shorter rise/fall times require the wire Longer wires or shorter rise/fall times require the wire Longer wires or shorter rise/fall times require the wire Longer wires or shorter rise/fall times require the wire to be modelled as a

to be modelled as a to be modelled as a

to be modelled as a transmission linetransmission linetransmission linetransmission line....

For short wires, a lumped RC model is sufficient. For For short wires, a lumped RC model is sufficient. For For short wires, a lumped RC model is sufficient. For For short wires, a lumped RC model is sufficient. For longer wires, we use the distributed RC model where longer wires, we use the distributed RC model where longer wires, we use the distributed RC model where longer wires, we use the distributed RC model where signal propagation can be shown to obey the

signal propagation can be shown to obey the signal propagation can be shown to obey the

signal propagation can be shown to obey the diffusion diffusion diffusion diffusion equation

C/unit length distance from driverdistance from driverdistance from driverdistance from driver

Which means the prop time Which means the prop time Which means the prop time

Which means the prop time tttt_xxxx = kx= kx= kx= kx²²²²with thewith thewith thewith the signal “edge” becoming dispersed with

signal “edge” becoming dispersed with signal “edge” becoming dispersed with signal “edge” becoming dispersed with increasing x.

MicroLab, VLSI-4 (25/29)

Diffusion Diffusion Diffusion

Diffusion Eq Eq Eq Eq. in “real life” . in “real life” . in “real life” . in “real life”

Weste Weste Weste

Weste, , , , EqEqEq. 4.28, Eq. 4.28, . 4.28, . 4.28,

but 10% to 90% rise/fall time but 10% to 90% rise/fall time but 10% to 90% rise/fall time but 10% to 90% rise/fall time

Ex vlsi4.3:

Ex vlsi4.3: clock with 50pf load distributedclock with 50pf load distributedclock with 50pf load distributedclock with 50pf load distributed by 1by 1

by 1by 1µµµµ----wide metal wire running from clockwide metal wire running from clockwide metal wire running from clockwide metal wire running from clock buffer in corner of 10mm x 10mm chip.

buffer in corner of 10mm x 10mm chip.

r = 0.05 ohm/square r = 0.05 ohm/square r = 0.05 ohm/square r = 0.05 ohm/square c = 50pf/20mm

Fix: drive clock from central location to Fix: drive clock from central location to Fix: drive clock from central location to Fix: drive clock from central location to decrease l and widen clock wire to 20 decrease l and widen clock wire to 20 decrease l and widen clock wire to 20 decrease l and widen clock wire to 20µµµµ::::

r = 0.0025 ohm/square r = 0.0025 ohm/square r = 0.0025 ohm/square r = 0.0025 ohm/square c = 50pf/10mm

Inductance Inductance Inductance Inductance

BondBondBondBond----wire inductance can cause deleterious effects wire inductance can cause deleterious effects wire inductance can cause deleterious effects wire inductance can cause deleterious effects in large, high speed I/O buffers

in large, high speed I/O buffers in large, high speed I/O buffers in large, high speed I/O buffers

package inductance: 3 .. 15 package inductance: 3 .. 15 package inductance: 3 .. 15 package inductance: 3 .. 15 nHnHnHnH

with process shrinking onwith process shrinking onwith process shrinking onwith process shrinking on----chip inductance has to be chip inductance has to be chip inductance has to be chip inductance has to be taken into account

taken into account taken into account taken into account

onononon----chip inductance: 10 .. 50pH/mmchip inductance: 10 .. 50pH/mmchip inductance: 10 .. 50pH/mmchip inductance: 10 .. 50pH/mm

design techniques:design techniques:design techniques:design techniques:

9 separate power pins for I/O pads and chip coreseparate power pins for I/O pads and chip coreseparate power pins for I/O pads and chip coreseparate power pins for I/O pads and chip core 9 multiple power and ground pinsmultiple power and ground pinsmultiple power and ground pinsmultiple power and ground pins

9 careful selection of the position of the power and careful selection of the position of the power and careful selection of the position of the power and careful selection of the position of the power and ground pins on the package

ground pins on the package ground pins on the package ground pins on the package

9 adding decoupling capacitances on the boardadding decoupling capacitances on the boardadding decoupling capacitances on the boardadding decoupling capacitances on the board 9 increase the rise and fall timesincrease the rise and fall timesincrease the rise and fall timesincrease the rise and fall times

9 use advanced package technologies (SMD, etc)use advanced package technologies (SMD, etc)use advanced package technologies (SMD, etc)use advanced package technologies (SMD, etc) dt

dtdt dt dIdIdI LLLL dI dV

dV dV

dV ==== î(t)î(t)î(t)î(t)

LLLL

LLLL VVVV_dd_dd_dd_dd

MicroLab, VLSI-4 (27/29)

Coming Up...

Next topic…

Combinational logic: series/parallel switch Combinational logic: series/parallel switch Combinational logic: series/parallel switch Combinational logic: series/parallel switch networks, transmission gates. Performance networks, transmission gates. Performance networks, transmission gates. Performance networks, transmission gates. Performance optimi

optimi optimi

optimissssationationationation....

Readings for next time…

W W

WWesteesteeste: este: : :

4.4 (inductance)4.4 (inductance)4.4 (inductance)4.4 (inductance)

4.3.6, and 4.5 thru 4.5.1, and 4.5.4 thru 4.5.5 except 4.3.6, and 4.5 thru 4.5.1, and 4.5.4 thru 4.5.5 except 4.3.6, and 4.5 thru 4.5.1, and 4.5.4 thru 4.5.5 except 4.3.6, and 4.5 thru 4.5.1, and 4.5.4 thru 4.5.5 except 4.5.4.4, and 4.6.3 (delay modelling)

4.5.4.4, and 4.6.3 (delay modelling) 4.5.4.4, and 4.6.3 (delay modelling) 4.5.4.4, and 4.6.3 (delay modelling)

4.7 (power consumption)4.7 (power consumption)4.7 (power consumption)4.7 (power consumption)

4.8 (sizing routing conductors)4.8 (sizing routing conductors)4.8 (sizing routing conductors)4.8 (sizing routing conductors)

You should read the rest of chapter 4 when you get You should read the rest of chapter 4 when you get You should read the rest of chapter 4 when you get You should read the rest of chapter 4 when you get the chance ...

the chance ...

In document VLSI system design (Page 90-94)