VLSI system design

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MicroLab, VLSI-1 (1/28)

VLSI System Design

Overview of VLSI Design Issues Overview of VLSI Design Issues Overview of VLSI Design Issues Overview of VLSI Design Issues

Overview Overview Overview Overview

Microelectronic historyMicroelectronic historyMicroelectronic historyMicroelectronic history

the complexity of microelectronicsthe complexity of microelectronicsthe complexity of microelectronicsthe complexity of microelectronics design stepsdesign stepsdesign stepsdesign steps

Goal: Goal: Goal:

Goal: You are familiar with the microelectronics history,You are familiar with the microelectronics history,You are familiar with the microelectronics history,You are familiar with the microelectronics history, have an idea about the microelectronics complexity and have an idea about the microelectronics complexity and have an idea about the microelectronics complexity and have an idea about the microelectronics complexity and you have an overview of the VLSI design steps.

you have an overview of the VLSI design steps. you have an overview of the VLSI design steps. you have an overview of the VLSI design steps.

Professor: Dr. Marcel Jacomet (based on transparencies designed Professor: Dr. Marcel Jacomet (based on transparencies designed Professor: Dr. Marcel Jacomet (based on transparencies designed

Professor: Dr. Marcel Jacomet (based on transparencies designed by by by by

Chris Chris Chris

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What’s expected of you

Readings from a Starter Guide to Readings from a Starter Guide to Readings from a Starter Guide to Readings from a Starter Guide to VHDL and some articles. Some VHDL and some articles. Some VHDL and some articles. Some VHDL and some articles. Some

problems to be worked at home. Self problems to be worked at home. Selfproblems to be worked at home. Self problems to be worked at home. Self----study of the VHDL language with help study of the VHDL language with help study of the VHDL language with help study of the VHDL language with help of the CBT CD from

of the CBT CD from of the CBT CD from

of the CBT CD from DoulouseDoulouseDoulouseDoulouse....

Some design exercises to be done in Some design exercises to be done in Some design exercises to be done in Some design exercises to be done in the lab. Specify, design and simulate the lab. Specify, design and simulate the lab. Specify, design and simulate the lab. Specify, design and simulate a small VHDL design project using a a small VHDL design project using a a small VHDL design project using a a small VHDL design project using a data

datadata

data----path / path / path / finitpath / finitfinitfinit state machine. state machine. state machine. state machine. Place & route it on a FPGA target Place & route it on a FPGA target Place & route it on a FPGA target Place & route it on a FPGA target technology (due date: July 19

technology (due date: July 19technology (due date: July 19

technology (due date: July 19thththth _at_at_at_at

13h00, 2002) 13h00, 2002) 13h00, 2002) 13h00, 2002) One 70 minute in One 70 minute in One 70 minute in

One 70 minute in----class test. Meant class test. Meant class test. Meant class test. Meant to be duck soup if you’ve been

to be duck soup if you’ve been to be duck soup if you’ve been to be duck soup if you’ve been

coming to lectures and doing the lab coming to lectures and doing the lab coming to lectures and doing the lab coming to lectures and doing the lab and homework (date: Friday July 12 and homework (date: Friday July 12 and homework (date: Friday July 12 and homework (date: Friday July 12thththth_{, , , ,}

2002). 2002).2002). 2002). Class/Homework Class/Homework Class/Homework Class/Homework 50% in class 50% in class 50% in class 50% in class 50% homework 50% homework 50% homework 50% homework Project Project Project Project 40% of final grade 40% of final grade40% of final grade 40% of final grade Test Test Test Test 60% of final grade 60% of final grade 60% of final grade 60% of final grade

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Timetable 4th Semester:

Introduction to VLSI System Design

Date Date Date

Date TopicTopicTopicTopic SelfSelfSelfSelf----StudyStudyStudyStudy 11111111----15.3.15.3.15.3.15.3. vlsi1: history & complexityvlsi1: history & complexityvlsi1: history & complexityvlsi1: history & complexity A VLSI A VLSI A VLSI A VLSI tutorialtutorialtutorialtutorial 18

18 18

18----22.3.22.3.22.3.22.3. vlsi8: micro technologies vlsi8: micro technologies vlsi8: micro technologies vlsi8: micro technologies How a a a a silicon HowHowHow silicon silicon silicon int.int.int.int. 25

25 25

25----29.3.29.3.29.3.29.3. ---

--11111111----19.4.19.4.19.4.19.4. vlsi8: micro technologies vlsi8: micro technologies vlsi8: micro technologies vlsi8: micro technologies article Hoffarticle Hoffarticle Hoffarticle Hoff 22

22 22

22----26.4.26.4.26.4.26.4. vlsi21: topvlsi21: topvlsi21: top----down design, VHDLvlsi21: top down design, VHDLdown design, VHDLdown design, VHDL VHDL/CBTVHDL/CBTVHDL/CBTVHDL/CBT 29.4

29.4 29.4

29.4----3.5.3.5.3.5.3.5. Ex400, 401Ex400, 401Ex400, 401Ex400, 401 VHDL/CBTVHDL/CBTVHDL/CBTVHDL/CBT 6666----10.5.10.5.10.5.10.5. --- VHDL/CBTVHDL/CBTVHDL/CBTVHDL/CBT 13

13 13

13----17.5.17.5.17.5.17.5. vlsi21 & Ex402vlsi21 & Ex402vlsi21 & Ex402vlsi21 & Ex402 VHDLVHDLVHDLVHDL 20

20 20

20----24.5.24.5.24.5.24.5. vlsi21 & Ex404,405 vlsi21 & Ex404,405 vlsi21 & Ex404,405 vlsi21 & Ex404,405 VHDLVHDLVHDLVHDL 27

27 27

27----31.5.31.5.31.5.31.5. vlsi21 & Ex406vlsi21 & Ex406vlsi21 & Ex406----408 vlsi21 & Ex406 408 408 VHDL408 VHDLVHDLVHDL 3333----7.6.7.6.7.6.7.6. vlsi21 & Ex409vlsi21 & Ex409vlsi21 & Ex409vlsi21 & Ex409 chapter 5chapter 5chapter 5chapter 5 10

10 10

10----14.6.14.6.14.6. vlsi21: & Ex41014.6. vlsi21: & Ex410vlsi21: & Ex410vlsi21: & Ex410 VHDL finishVHDL finishVHDL finishVHDL finish 17

17 17

17----21.6. 21.6. 21.6. Ex45021.6. Ex450Ex450Ex450 projectprojectprojectproject 24

24 24

24----28.628.628.628.6 Ex451Ex451Ex451Ex451 projectprojectprojectproject 1111----5.7.5.7.5.7.5.7. Ex452Ex452Ex452Ex452 projectprojectprojectproject 8888----12.6.12.6.12.6.12.6. TestTestTestTest projectprojectprojectproject 15

15 15

15----19. 619. 619. 619. 6 test discussion and outlooktest discussion and outlooktest discussion and outlooktest discussion and outlook projectprojectprojectproject

19.6. 19.6. 19.6.

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So, what’s VLSI Systems Design

all about?

You’ll get a bottom You’ll get a bottomYou’ll get a bottom

You’ll get a bottom----up tour of how integrated up tour of how integrated up tour of how integrated up tour of how integrated circuits are engineered. We’ll talk about

circuits are engineered. We’ll talk aboutcircuits are engineered. We’ll talk about circuits are engineered. We’ll talk about

fieldfieldfieldfield----effect transistors: how they work, how they’re effect transistors: how they work, how they’re effect transistors: how they work, how they’re effect transistors: how they work, how they’re built, effects of new technologies

built, effects of new technologiesbuilt, effects of new technologies built, effects of new technologies

various design and layout techniques, from the various design and layout techniques, from the various design and layout techniques, from the various design and layout techniques, from the ordinary to the bizarre, for creating combinational ordinary to the bizarre, for creating combinational ordinary to the bizarre, for creating combinational ordinary to the bizarre, for creating combinational and sequential circuits,

and sequential circuits, and sequential circuits,

and sequential circuits, datapathsdatapathsdatapathsdatapaths, memories, , memories, , memories, , memories, buffers, regular logic structures, …

buffers, regular logic structures, …buffers, regular logic structures, … buffers, regular logic structures, …

how you tackle the problem of designing circuits how you tackle the problem of designing circuits how you tackle the problem of designing circuits how you tackle the problem of designing circuits with 1,000,000 gates

with 1,000,000 gates with 1,000,000 gates

with 1,000,000 gates --- you’re not in Digital you’re not in Digital you’re not in Digital you’re not in Digital Technique anymore!

Technique anymore!Technique anymore! Technique anymore!

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Key Technology Microelectronics

microelectronics is a key technology of the world microelectronics is a key technology of the world microelectronics is a key technology of the world microelectronics is a key technology of the world economy economy economy economy

technology development is extremely aggressivetechnology development is extremely aggressivetechnology development is extremely aggressivetechnology development is extremely aggressive

postpostpostpost----grade engineering education is importantgrade engineering education is importantgrade engineering education is importantgrade engineering education is important

influence of other technologies like software influence of other technologies like software influence of other technologies like software influence of other technologies like software engineering engineering engineering engineering

key technologies may be used as weapons. 1991 key technologies may be used as weapons. 1991 key technologies may be used as weapons. 1991 key technologies may be used as weapons. 1991 Japan hold 80% share of the world production of Japan hold 80% share of the world production of Japan hold 80% share of the world production of Japan hold 80% share of the world production of 4MB

4MB 4MB

4MB DRAMsDRAMsDRAMsDRAMs. Artificial raw material shortage are . Artificial raw material shortage are . Artificial raw material shortage are . Artificial raw material shortage are disastrous. disastrous. disastrous. disastrous.

very few Swiss chip very few Swiss chip very few Swiss chip very few Swiss chip fabsfabsfabs. Our raw material is the fabs. Our raw material is the . Our raw material is the . Our raw material is the high education standard, that means

high education standard, that means high education standard, that means

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What is a VLSI Circuit?

VERY LARGE SCALE INTEGRATED CIRCUIT VERY LARGE SCALE INTEGRATED CIRCUITVERY LARGE SCALE INTEGRATED CIRCUIT VERY LARGE SCALE INTEGRATED CIRCUIT

Technique where many circuit components and Technique where many circuit components and Technique where many circuit components and Technique where many circuit components and the wiring that connects them are manufactured the wiring that connects them are manufactured the wiring that connects them are manufactured the wiring that connects them are manufactured simultaneously into a compact, reliable and simultaneously into a compact, reliable and simultaneously into a compact, reliable and simultaneously into a compact, reliable and inexpensive chip.

inexpensive chip. inexpensive chip. inexpensive chip.

Early (circa 1977) characterization of circuit Early (circa 1977) characterization of circuit Early (circa 1977) characterization of circuit Early (circa 1977) characterization of circuit “size” before people realized that the number of “size” before people realized that the number of “size” before people realized that the number of “size” before people realized that the number of components per chip was quadrupling every 24 components per chip was quadrupling every 24 components per chip was quadrupling every 24 components per chip was quadrupling every 24 months (

months ( months (

months (Moore’sMoore’sMoore’s Law)! This growth rate has Moore’s Law)! This growth rate has Law)! This growth rate has Law)! This growth rate has slowed in recent years… can you guess why? slowed in recent years… can you guess why? slowed in recent years… can you guess why? slowed in recent years… can you guess why?

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Course Outline/Brief history

Bell Labs lays the groundwork: Bell Labs lays the groundwork: Bell Labs lays the groundwork: Bell Labs lays the groundwork: 1940:

1940: 1940:

1940: OhlOhlOhlOhl develops PN junctiondevelops PN junctiondevelops PN junctiondevelops PN junction 1945: Shockley’s lab established 1945: Shockley’s lab established 1945: Shockley’s lab established 1945: Shockley’s lab established 1947:

1947: 1947:

1947: BardeenBardeenBardeen and Bardeenand and Brattainand BrattainBrattain createBrattain createcreatecreate point

point point

point----contact transistor withcontact transistor withcontact transistor withcontact transistor with two PN junctions. Gain = 18. two PN junctions. Gain = 18. two PN junctions. Gain = 18. two PN junctions. Gain = 18.

1951: Shockley develops junction 1951: Shockley develops junction 1951: Shockley develops junction 1951: Shockley develops junction

transistor which can be transistor which can betransistor which can be transistor which can be manufactured in quantity. manufactured in quantity.manufactured in quantity. manufactured in quantity. 1952:

1952: 1952:

1952: DummerDummerDummerDummer forecasts “solidforecasts “solidforecasts “solidforecasts “solid block [with] layers of block [with] layers of block [with] layers of block [with] layers of insulating, conducting and insulating, conducting and insulating, conducting and insulating, conducting and amplifying materials” amplifying materials” amplifying materials” amplifying materials” 1954: The first transistor radio! 1954: The first transistor radio! 1954: The first transistor radio! 1954: The first transistor radio!

Also, TI makes first silicon Also, TI makes first silicon Also, TI makes first silicon Also, TI makes first silicon transistor (price $2.50) transistor (price $2.50) transistor (price $2.50) transistor (price $2.50)

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Early integration

Jack Jack Jack

Jack KilbyKilbyKilbyKilby, working at Texas Instruments, first dreamed up the idea , working at Texas Instruments, first dreamed up the idea , working at Texas Instruments, first dreamed up the idea , working at Texas Instruments, first dreamed up the idea of a monolithic “integrated circuit” in July 1959. By the end o of a monolithic “integrated circuit” in July 1959. By the end o of a monolithic “integrated circuit” in July 1959. By the end o of a monolithic “integrated circuit” in July 1959. By the end of the f the f the f the year, he had constructed several examples, including the flip

year, he had constructed several examples, including the flip year, he had constructed several examples, including the flip year, he had constructed several examples, including the flip----flop flop flop flop shown in the patent drawing above. Components are connected by shown in the patent drawing above. Components are connected by shown in the patent drawing above. Components are connected by shown in the patent drawing above. Components are connected by hand

hand hand

hand----soldered wires and isolated by “shaping” and soldered wires and isolated by “shaping” and soldered wires and isolated by “shaping” and pnsoldered wires and isolated by “shaping” and pnpnpn diodes used as diodes used as diodes used as diodes used as resistors. resistors. resistors. resistors. Robert Robert Robert

Robert NoyceNoyceNoyce experimented in the late 40’s withNoyce experimented in the late 40’s withexperimented in the late 40’s withexperimented in the late 40’s with

transistors while a physics major at college. He went to MIT wh transistors while a physics major at college. He went to MIT wh transistors while a physics major at college. He went to MIT wh transistors while a physics major at college. He went to MIT where ere ere ere “much to his surprise, few people had even heard about the

“much to his surprise, few people had even heard about the “much to his surprise, few people had even heard about the “much to his surprise, few people had even heard about the transistor.” After getting his PhD in 1953, he worked in indust transistor.” After getting his PhD in 1953, he worked in indust transistor.” After getting his PhD in 1953, he worked in indust transistor.” After getting his PhD in 1953, he worked in industry, ry, ry, ry, finally arriving at Mountain View, CA and Shockley Semiconductor finally arriving at Mountain View, CA and Shockley Semiconductor finally arriving at Mountain View, CA and Shockley Semiconductor finally arriving at Mountain View, CA and Shockley Semiconductor Labs in 1955.

Labs in 1955. Labs in 1955. Labs in 1955.

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“ “

In 1957, In 1957, In 1957,

In 1957, NoyceNoyceNoyce left Shockley’sNoyce left Shockley’sleft Shockley’sleft Shockley’s lab to form Fairchild Semi lab to form Fairchild Semi lab to form Fairchild Semi lab to form Fairchild Semi----conductor with Jean

conductor with Jean conductor with Jean

conductor with Jean HoerniHoerniHoerni....Hoerni Gordon Moore is another Gordon Moore is another Gordon Moore is another Gordon Moore is another founder. founder. founder. founder. In early 1958, In early 1958, In early 1958,

In early 1958, HoerniHoerniHoerni invents Hoerni invents invents invents technique for diffusing impurities technique for diffusing impurities technique for diffusing impurities technique for diffusing impurities intointointointo the silicon to build planar transistors the silicon to build planar transistors the silicon to build planar transistors the silicon to build planar transistors and then using a SiO2 insulator. and then using a SiO2 insulator. and then using a SiO2 insulator. and then using a SiO2 insulator.

In mid 1959, In mid 1959, In mid 1959,

In mid 1959, NoyceNoyceNoyce developsNoyce developsdevelopsdevelops

first true IC using planar transistors, first true IC using planar transistors, first true IC using planar transistors, first true IC using planar transistors, back

back back

back----totototo----back back back back pnpnpnpn junctions for junctions for junctions for junctions for isolation, diode

isolation, diode isolation, diode

isolation, diode----isolated silicon isolated silicon isolated silicon isolated silicon resistors and SiO2 insulation with resistors and SiO2 insulation with resistors and SiO2 insulation with resistors and SiO2 insulation with evaporated metal wiring on top. evaporated metal wiring on top. evaporated metal wiring on top. evaporated metal wiring on top.

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Practice makes perfect...

1968: 1968: 1968:

1968: NoyceNoyceNoyceNoyce and Moore leaveand Moore leaveand Moore leaveand Moore leave Fairchild and found Intel. No Fairchild and found Intel. No Fairchild and found Intel. No Fairchild and found Intel. No business plan, just a promise business plan, just a promise business plan, just a promise business plan, just a promise to specialize in memory chips. to specialize in memory chips. to specialize in memory chips. to specialize in memory chips. They raise $3M in two days They raise $3M in two days They raise $3M in two days They raise $3M in two days and move to Santa Clara. By and move to Santa Clara. By and move to Santa Clara. By and move to Santa Clara. By 1971 Intel had 500 employees; 1971 Intel had 500 employees; 1971 Intel had 500 employees; 1971 Intel had 500 employees; by 1983 it had 21,500

by 1983 it had 21,500 by 1983 it had 21,500 by 1983 it had 21,500

employees and $1100M in sales. employees and $1100M in sales. employees and $1100M in sales. employees and $1100M in sales. 1961: TI and Fairchild introduced 1961: TI and Fairchild introduced 1961: TI and Fairchild introduced 1961: TI and Fairchild introduced the first logic IC’s (cost ~$50 in the first logic IC’s (cost ~$50 in the first logic IC’s (cost ~$50 in the first logic IC’s (cost ~$50 in quantity!). This is a dual flip

quantity!). This is a dual flip quantity!). This is a dual flip

quantity!). This is a dual flip----flop with 4 flop with 4 flop with 4 flop with 4 transistors.

transistors. transistors. transistors.

1963: Densities and yields are improving. 1963: Densities and yields are improving. 1963: Densities and yields are improving. 1963: Densities and yields are improving. This circuit has four flip flops.

This circuit has four flip flops. This circuit has four flip flops. This circuit has four flip flops.

1.5 mm 1.5 mm 1.5 mm 1.5 mm 0.97 mm 0.97 mm 0.97 mm 0.97 mm 3.81 mm 3.81 mm 3.81 mm 3.81 mm

1967: Fairchild markets the semi 1967: Fairchild markets the semi 1967: Fairchild markets the semi

1967: Fairchild markets the semi----custom custom custom custom chip shown below. Transistors (organized in chip shown below. Transistors (organized in chip shown below. Transistors (organized in chip shown below. Transistors (organized in columns) could be easily rewired using a columns) could be easily rewired using a columns) could be easily rewired using a columns) could be easily rewired using a two

two two

two----layer interconnect to create different layer interconnect to create different layer interconnect to create different layer interconnect to create different circuits. This circuit contains ~150 logic circuits. This circuit contains ~150 logic circuits. This circuit contains ~150 logic circuits. This circuit contains ~150 logic gates.

gates. gates. gates.

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The Big Bang

In 1971 Intel introduces the first In 1971 Intel introduces the first In 1971 Intel introduces the first In 1971 Intel introduces the first microprocessor, designed by Ted microprocessor, designed by Ted microprocessor, designed by Ted microprocessor, designed by Ted Hoff. The 4004 had 4

Hoff. The 4004 had 4 Hoff. The 4004 had 4

Hoff. The 4004 had 4----bit buses and bit buses and bit buses and bit buses and a clock rate of 108KHz. It had 2300 a clock rate of 108KHz. It had 2300 a clock rate of 108KHz. It had 2300 a clock rate of 108KHz. It had 2300 transistors and was built in a 10um transistors and was built in a 10um transistors and was built in a 10um transistors and was built in a 10um process. It never captured much process. It never captured much process. It never captured much process. It never captured much interest in the market and was soon interest in the market and was soon interest in the market and was soon interest in the market and was soon eclipsed by its more capable brothers. eclipsed by its more capable brothers. eclipsed by its more capable brothers. eclipsed by its more capable brothers.

2.87 mm 2.87 mm 2.87 mm 2.87 mm In 1970, making good on In 1970, making good on In 1970, making good on In 1970, making good on its promise to its investors Intel its promise to its investors Intel its promise to its investors Intel its promise to its investors Intel starts selling a 1K bit RAM, the starts selling a 1K bit RAM, the starts selling a 1K bit RAM, the starts selling a 1K bit RAM, the 1103. It was a bear to interface to, 1103. It was a bear to interface to, 1103. It was a bear to interface to, 1103. It was a bear to interface to, but its density and cost make it the but its density and cost make it the but its density and cost make it the but its density and cost make it the only game it town. only game it town. only game it town. only game it town.

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Exponential Growth

Introduced in 1972, the 8008 had 3,500 Introduced in 1972, the 8008 had 3,500 Introduced in 1972, the 8008 had 3,500 Introduced in 1972, the 8008 had 3,500 transistors supporting a byte

transistors supporting a byte transistors supporting a byte

transistors supporting a byte----wide data path. wide data path. wide data path. wide data path. Despite its limitations, the 8008 was the first Despite its limitations, the 8008 was the first Despite its limitations, the 8008 was the first Despite its limitations, the 8008 was the first microprocessor capable of playing the role of microprocessor capable of playing the role of microprocessor capable of playing the role of microprocessor capable of playing the role of computer CPU as demonstrated on the cover of computer CPU as demonstrated on the cover of computer CPU as demonstrated on the cover of computer CPU as demonstrated on the cover of the July ‘74 issue of

the July ‘74 issue of the July ‘74 issue of

the July ‘74 issue of RadioRadioRadioRadio----ElectronicsElectronicsElectronicsElectronics....

Last, but not least, on our tour is the Last, but not least, on our tour is the Last, but not least, on our tour is the Last, but not least, on our tour is the 8080. Introduced in 1974, the 8080 8080. Introduced in 1974, the 8080 8080. Introduced in 1974, the 8080 8080. Introduced in 1974, the 8080 had 6,000 transistors

had 6,000 transistors had 6,000 transistors

had 6,000 transistors fab’edfab’edfab’edfab’ed in a 6um in a 6um in a 6um in a 6um process. The clock rate was 2Mhz, more process. The clock rate was 2Mhz, more process. The clock rate was 2Mhz, more process. The clock rate was 2Mhz, more than enough to ignite the personal than enough to ignite the personal than enough to ignite the personal than enough to ignite the personal computer industry. At least Paul Allen computer industry. At least Paul Allen computer industry. At least Paul Allen computer industry. At least Paul Allen and his partner thought so when they and his partner thought so when they and his partner thought so when they and his partner thought so when they wrote a BASIC interpreter for the 8080 wrote a BASIC interpreter for the 8080 wrote a BASIC interpreter for the 8080 wrote a BASIC interpreter for the 8080 in 1975. They would later collaborate in in 1975. They would later collaborate in in 1975. They would later collaborate in in 1975. They would later collaborate in another, more profitable, venture... another, more profitable, venture...another, more profitable, venture... another, more profitable, venture...

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Today

Many disciplines have contributed to the current state of the ar Many disciplines have contributed to the current state of the ar Many disciplines have contributed to the current state of the ar Many disciplines have contributed to the current state of the art t t t in VLSI design: in VLSI design: in VLSI design: in VLSI design:

solidsolid----state physicssolidsolid state physicsstate physicsstate physics

materials sciencematerials sciencematerials sciencematerials science

lithography and lithography and lithography and lithography and fabfabfabfab

architecturearchitecturearchitecturearchitecture

algorithmsalgorithmsalgorithmsalgorithms

CAD toolsCAD toolsCAD toolsCAD tools

AVP AVP AVP

AVP----III Video III Video III Video III Video CodecCodecCodec from Lucent TechnologiesCodecfrom Lucent Technologiesfrom Lucent Technologiesfrom Lucent Technologies

We’ll be concentrating on the right We’ll be concentrating on the rightWe’ll be concentrating on the right

We’ll be concentrating on the right----hand columnhand columnhand columnhand column

circuit design & layoutcircuit design & layoutcircuit design & layoutcircuit design & layout

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CAD Tools #1

“Computer “Computer“Computer “Computer----Aided AidedAided Aided Design” Design”Design” Design”

Tools to do the tedious, repetitive work such as Tools to do the tedious, repetitive work such as Tools to do the tedious, repetitive work such as Tools to do the tedious, repetitive work such as routing,“tiling” a mosaic of building

routing,“tiling” a mosaic of building routing,“tiling” a mosaic of building

routing,“tiling” a mosaic of building----block cells, orblock cells, orblock cells, orblock cells, or verifying that the layout and schematic match. verifying that the layout and schematic match. verifying that the layout and schematic match. verifying that the layout and schematic match.

Circuit analysis programs predict circuit behavior at Circuit analysis programs predict circuit behavior at Circuit analysis programs predict circuit behavior at Circuit analysis programs predict circuit behavior at all the process corners. Gate

all the process corners. Gate all the process corners. Gate

all the process corners. Gate----level and behavioral level and behavioral level and behavioral level and behavioral simulators help you get it right the first time! simulators help you get it right the first time! simulators help you get it right the first time! simulators help you get it right the first time! Symbolic layout tools to Symbolic layout tools to Symbolic layout tools to Symbolic layout tools to ease the task of physical ease the task of physical ease the task of physical ease the task of physical design; mask verification design; mask verification design; mask verification design; mask verification to ensure manufacturability. to ensure manufacturability. to ensure manufacturability. to ensure manufacturability. Standard Standard Standard

Standard----cell placecell placecell placecell place and route for “random” and route for “random” and route for “random” and route for “random” logic. logic. logic. logic.

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CAD Tools #2

Problem: Problem: Problem: Problem:

designing highly complex VLSI circuits designing highly complex VLSI circuits designing highly complex VLSI circuits designing highly complex VLSI circuits (100K to

(100K to (100K to

(100K to xM fetsxM fetsxM fetsxM fets))))

classical, iterative procedures are unsuitableclassical, iterative procedures are unsuitableclassical, iterative procedures are unsuitableclassical, iterative procedures are unsuitable

precise transistor models are necessary for precise transistor models are necessary for precise transistor models are necessary for precise transistor models are necessary for reliable predictions

reliable predictions reliable predictions

reliable predictions ÆÆÆÆ data inflationdata inflationdata inflationdata inflation

Solution: Solution: Solution: Solution:

new design methodologiesnew design methodologiesnew design methodologiesnew design methodologies

powerful design toolspowerful design toolspowerful design toolspowerful design tools

high level design languageshigh level design languageshigh level design languageshigh level design languages

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VLSI Design Challenge

Goal: Goal: Goal: Goal:

designing circuits with increasing complexity in designing circuits with increasing complexity in designing circuits with increasing complexity in designing circuits with increasing complexity in always shorter times

always shorter times always shorter times always shorter times

computer has to take over routine workcomputer has to take over routine workcomputer has to take over routine workcomputer has to take over routine work

deliberate the designer from unnecessary low deliberate the designer from unnecessary low deliberate the designer from unnecessary low deliberate the designer from unnecessary low qualification work qualification work qualification work qualification work

shift of design activities to higher level abstract shift of design activities to higher level abstract shift of design activities to higher level abstract shift of design activities to higher level abstract work work work work

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Chip Complexity #1

Chip classification according to number of active Chip classification according to number of active Chip classification according to number of active Chip classification according to number of active elements and minimal feature size:

elements and minimal feature size: elements and minimal feature size: elements and minimal feature size: classification

classification classification

classification #transistors#transistors#transistors#transistors exampleexampleexampleexample SSI

SSI SSI

SSI 1 1 1 1 ---- 100100100100 gatesgatesgatesgates MSI

MSI MSI

MSI 100 100 100 100 ---- 1k1k1k1k registersregistersregistersregisters LSI LSI LSI LSI 1k 1k 1k 1k ---- 100k100k100k100k uPuPuPuP VLSI VLSI VLSI

VLSI 100K 100K 100K 100K ---- RAM, sig. proc.RAM, sig. proc.RAM, sig. proc.RAM, sig. proc. ULSI ULSI ULSI ULSI ???? year year year

year minimal channel lengthminimal channel lengthminimal channel lengthminimal channel length 1970 1970 1970 1970 10101010_µµµµmmmm 1980 1980 1980 1980 5555_µµµµmmmm 1985 1985 1985 1985 2222µµµµmmmm 1992 1992 1992 1992 0.50.50.50.5_µµµµmmmm 200 200 200 2002222 0.10.10.10.13333_µµµµmmmm 2010 2010 2010 2010 ????

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Chip Complexity #2

can you really imagine the chip complexity of can you really imagine the chip complexity of can you really imagine the chip complexity of can you really imagine the chip complexity of

today's VLSI chips and not just express it as a mere today's VLSI chips and not just express it as a mere today's VLSI chips and not just express it as a mere today's VLSI chips and not just express it as a mere number

number number number

street map image street map image street map image street map image year

year year

year feature feature feature feature blockblockblockblock chip chip chip chip towntowntowntown 1970

1970 1970

1970 10x1010x1010x1010x10_{µµµµmmmm200m}200m200m200m 2mm2mm2mm2mm BielBielBielBiel 1980

1980 1980

1980 10x510x510x510x5_{µµµµmmmm 200m}200m200m200m 5mm5mm5mm5mm ParisParisParisParis 1992

1992 1992

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Architecture

(Multiple choice) (Multiple choice) (Multiple choice) (Multiple choice) This is a picture of This is a picture of This is a picture of This is a picture of

(A) a programmable general purpose ASIC with 1/4 million (A) a programmable general purpose ASIC with 1/4 million (A) a programmable general purpose ASIC with 1/4 million (A) a programmable general purpose ASIC with 1/4 million

transistors on a 40mm transistors on a 40mm transistors on a 40mm

transistors on a 40mm2222 _{designed in a 0.7}_{designed in a 0.7}_{designed in a 0.7}_{designed in a 0.7}_{µµµµm CMOS}_{m CMOS}_{m CMOS}_{m CMOS}

full custom technology. full custom technology. full custom technology. full custom technology.

(B) a processor able to execute 64 knowledge based rules (B) a processor able to execute 64 knowledge based rules (B) a processor able to execute 64 knowledge based rules (B) a processor able to execute 64 knowledge based rules in parallel due to a 3 stage pipelined architecture with in parallel due to a 3 stage pipelined architecture with in parallel due to a 3 stage pipelined architecture with in parallel due to a 3 stage pipelined architecture with hard

hard hard

hard----coded adder, multiplier, divider architecture.coded adder, multiplier, divider architecture.coded adder, multiplier, divider architecture.coded adder, multiplier, divider architecture. (C) the fastest fuzzy processor in the world, designed (C) the fastest fuzzy processor in the world, designed (C) the fastest fuzzy processor in the world, designed (C) the fastest fuzzy processor in the world, designed

by by by

by MicroLabMicroLabMicroLabMicroLab----I3S and presented at the international I3S and presented at the international I3S and presented at the international I3S and presented at the international FUZZ‘98 conference in New Orleans

FUZZ‘98 conference in New Orleans FUZZ‘98 conference in New Orleans FUZZ‘98 conference in New Orleans

ANSWER: _________ ANSWER: _________ ANSWER: _________ ANSWER: _________

(20)

Circuit Design & Layout

Standard cell

Standard cell Standard cell

Standard cell Full customFull customFull customFull custom

RAM Generator RAM Generator RAM Generator RAM Generator

Q: Which engineer drew the most Q: Which engineer drew the most Q: Which engineer drew the most

(21)

VLSI: The Ideal Implementation

Medium?

VLSI VLSI VLSI VLSI

gives the designer control over almost everything: gives the designer control over almost everything: gives the designer control over almost everything: gives the designer control over almost everything: architecture, logic design, speed, area, power, … architecture, logic design, speed, area, power, … architecture, logic design, speed, area, power, … architecture, logic design, speed, area, power, …

densities are increasing, costs decreasing with each densities are increasing, costs decreasing with each densities are increasing, costs decreasing with each densities are increasing, costs decreasing with each passing year passing year passing year passing year

is used by almost everyone: is used by almost everyone: is used by almost everyone: is used by almost everyone: “No one gets fired for “No one gets fired for “No one gets fired for “No one gets fired for building an ASIC” building an ASIC” building an ASIC” building an ASIC”

was the enabling technology for much of the was the enabling technology for much of the was the enabling technology for much of the was the enabling technology for much of the

economic growth of the 80’s and 90’s. It will no economic growth of the 80’s and 90’s. It will no economic growth of the 80’s and 90’s. It will no economic growth of the 80’s and 90’s. It will no doubt continue in its starring role for some time doubt continue in its starring role for some time doubt continue in its starring role for some time doubt continue in its starring role for some time come.

come. come. come.

Is life really a bowl of cherries? Is life really a bowl of cherries? Is life really a bowl of cherries? Is life really a bowl of cherries?

(22)

VLSI Fact

VLSI Fact----of

ofof

of----Life #1:

Life #1:

“So much to do, so little time”

budget ($, speed, area, power, schedule, risk)budget ($, speed, area, power, schedule, risk)budget ($, speed, area, power, schedule, risk)budget ($, speed, area, power, schedule, risk)

lowlowlowlow----level building blocks,level building blocks,level building blocks,level building blocks, high

high high

high----level architecturelevel architecturelevel architecturelevel architecture

behaviouralbehavioural design, verificationbehaviouralbehavioural design, verificationdesign, verificationdesign, verification

logic design, verificationlogic design, verificationlogic design, verificationlogic design, verification

layout, verificationlayout, verificationlayout, verificationlayout, verification You need a

You need a You need a

(23)

VLSI Fact

VLSI Fact----of

ofof

of----Life #2:

Life #2:

“You can’t reach in and fix it”

Notice that the word Notice that the word Notice that the word

Notice that the word ““““verificationverificationverificationverification”””” kept appearing in kept appearing in kept appearing in kept appearing in the previous slide.

the previous slide. the previous slide. the previous slide. Mistakes can be costly: Mistakes can be costly: Mistakes can be costly: Mistakes can be costly:

find bug(s) find bug(s) find bug(s) find bug(s) ???? ???? reverify reverify reverify

reverify 1 week1 week1 week1 week EcuEcuEcuEcu 10k10k10k10k new masks

new masks new masks

new masks 3 days3 days3 days3 days EcuEcuEcuEcu 25k25k25k25k fab

fab fab

fab runrunrunrun 12 weeks12 weeks12 weeks12 weeks EcuEcuEcuEcu 1k/wafer1k/wafer1k/wafer1k/wafer slip ship date

slip ship date slip ship date

slip ship date Ecu Ecu EcuEcu Ecu EcuEcu Ecu EcuEcu Ecu Ecu There’s a lot that needs checking:

There’s a lot that needs checking: There’s a lot that needs checking: There’s a lot that needs checking:

circuit must operate at all “corners”circuit must operate at all “corners”circuit must operate at all “corners”circuit must operate at all “corners” verified at building block level verified at building block level verified at building block level verified at building block level

logic must be correct, operate reliablylogic must be correct, operate reliablylogic must be correct, operate reliablylogic must be correct, operate reliably verified at RTL/gate level

verified at RTL/gate level verified at RTL/gate level verified at RTL/gate level

chip has to interoperate with systemchip has to interoperate with systemchip has to interoperate with systemchip has to interoperate with system verified at behavioral level

verified at behavioral level verified at behavioral level verified at behavioral level

chip has to be chip has to be chip has to be chip has to be manufacturabmanufacturabmanufacturabmanufacturable le le le verified at mask level, at tester

verified at mask level, at tester verified at mask level, at tester verified at mask level, at tester

(24)

VLSI Fact

VLSI Fact----of

ofof

of----Life #3:

Life #3:

“Verification is a tedious task”

(25)

VLSI Fact

VLSI Fact----of

ofof

of----Life #4:

Life #4:

“You can’t

“You can’t find

find

find all the bugs”

all the bugs”

The key word here is “find”: The key word here is “find”: The key word here is “find”: The key word here is “find”:

one can’t explore the one can’t explore the behaviourone can’t explore the one can’t explore the behaviourbehaviourbehaviour of the circuit under all of the circuit under all of the circuit under all of the circuit under all possible conditions possible conditions possible conditions possible conditions

some of the bugs arise from unanticipated interactions some of the bugs arise from unanticipated interactions some of the bugs arise from unanticipated interactions some of the bugs arise from unanticipated interactions which, by definition, one never thinks of testing

which, by definition, one never thinks of testing which, by definition, one never thinks of testing which, by definition, one never thinks of testing

it’s not clear when one is “done” looking for bugs! it’s not clear when one is “done” looking for bugs! it’s not clear when one is “done” looking for bugs! it’s not clear when one is “done” looking for bugs! Time pressures mean that most searches stop too soon. Time pressures mean that most searches stop too soon. Time pressures mean that most searches stop too soon. Time pressures mean that most searches stop too soon.

The trick is to choose some implementation rules that The trick is to choose some implementation rules that The trick is to choose some implementation rules that The trick is to choose some implementation rules that result in a circuit that is

result in a circuit that is result in a circuit that is

result in a circuit that is correct by construction*correct by construction*correct by construction*correct by construction*. For . For . For . For example: example: example: example:

choose a simple clocking schemechoose a simple clocking schemechoose a simple clocking schemechoose a simple clocking scheme

module inputs must go only to module inputs must go only to module inputs must go only to module inputs must go only to fetfetfet gatesfet gatesgatesgates

disallow disallow disallow disallow unclockedunclockedunclockedunclocked feedbackfeedbackfeedbackfeedback

make register t(make register t(make register t(make register t(clkclkclk----toclk tototo----Q) > t(hold)+skewQ) > t(hold)+skewQ) > t(hold)+skewQ) > t(hold)+skew

use poly only for local interconnectuse poly only for local interconnectuse poly only for local interconnectuse poly only for local interconnect

no diffusion wiresno diffusion wiresno diffusion wiresno diffusion wires

etc., etc., etc.etc., etc., etc.etc., etc., etc.etc., etc., etc.

* or at least avoid as many problems as possible! * or at least avoid as many problems as possible! * or at least avoid as many problems as possible! * or at least avoid as many problems as possible!

(26)

VLSI Fact

VLSI Fact----of

ofof

of----Life #5:

Life #5:

“Nobody’s perfect”

Plan for what happens after you turn it on and Plan for what happens after you turn it on and Plan for what happens after you turn it on and Plan for what happens after you turn it on and nothing happens. nothing happens. nothing happens. nothing happens.

provide lot’s of provide lot’s of provide lot’s of provide lot’s of observabilityobservabilityobservabilityobservability and and and and controlabilitycontrolabilitycontrolabilitycontrolability. . . . You’ll need to localize and then find the bug.

You’ll need to localize and then find the bug. You’ll need to localize and then find the bug. You’ll need to localize and then find the bug.

have a way to run the chip slowly and/or stop it have a way to run the chip slowly and/or stop it have a way to run the chip slowly and/or stop it have a way to run the chip slowly and/or stop it without it burning up or loosing bits.

without it burning up or loosing bits. without it burning up or loosing bits. without it burning up or loosing bits.

figure out how to track down performance figure out how to track down performance figure out how to track down performance figure out how to track down performance

problems without relying on fast I/O (tester pins problems without relying on fast I/O (tester pins problems without relying on fast I/O (tester pins problems without relying on fast I/O (tester pins are slow!) are slow!) are slow!) are slow!)

leave room in the budgetleave room in the budgetleave room in the budgetleave room in the budget (time,

(time, (time,

(time, EcuEcuEcuEcu) for debugging.) for debugging.) for debugging.) for debugging.

write and run yourwrite and run yourwrite and run yourwrite and run your manufacturing tests manufacturing tests manufacturing tests manufacturing tests before before before

(27)

Microelectronics in 4th Semester

history & history & history & history & complexity complexity complexity complexity microelectronic microelectronic microelectronic microelectronic technologies technologies technologies technologies VHDL VHDL VHDL VHDL exercises with exercises with exercises with exercises with CAD tools CAD tools CAD tools CAD tools design flow design flow design flow design flow EXPERIENCE EXPERIENCEEXPERIENCE EXPERIENCE data path / data path / data path / data path / fsmfsmfsmfsm project projectproject project synthesis synthesis synthesis synthesis Course material Course material Course material Course material

Textbook fromTextbook fromTextbook from WesteTextbook from WesteWeste & Weste & Eshraghian& & EshraghianEshraghian for Eshraghian for for for

4th and 5th semester (voluntary) 4th and 5th semester (voluntary) 4th and 5th semester (voluntary) 4th and 5th semester (voluntary)

Copy of transparencies (placeholder for private notes)Copy of transparencies (placeholder for private notes)Copy of transparencies (placeholder for private notes)Copy of transparencies (placeholder for private notes) VHDL VHDL VHDL VHDL StarterStarterStarter (recommended)Starter (recommended)(recommended)(recommended)

CAD Exercises on the CAD Exercises on the CAD Exercises on the CAD Exercises on the MicroLabMicroLabMicroLabMicroLab web pagesweb pagesweb pagesweb pages

CBT CD on VHDL for your PC (lending CBT CD on VHDL for your PC (lending CBT CD on VHDL for your PC (lending CBT CD on VHDL for your PC (lending

from from from

(28)

Coming Up...

We’ll be traveling top We’ll be traveling top We’ll be traveling top

We’ll be traveling top----down in 4th semester and down in 4th semester and down in 4th semester and down in 4th semester and bottom

bottom bottom

bottom----up in 5 & 6 semester:up in 5 & 6 semester:up in 5 & 6 semester:up in 5 & 6 semester: Next topic…

Next topic… Next topic… Next topic…

Microelectronic technologies like standard cell, Microelectronic technologies like standard cell, Microelectronic technologies like standard cell, Microelectronic technologies like standard cell, gate array, sea

gate array, sea gate array, sea

gate array, sea----ofofofof----gates, macro cell, FPGA, tiny gates, macro cell, FPGA, tiny gates, macro cell, FPGA, tiny gates, macro cell, FPGA, tiny micro

micro micro

micro----controllers.controllers.controllers.controllers.

Readings for next time… Readings for next time… Readings for next time… Readings for next time… web CBT tutorials see on web CBT tutorials see on web CBT tutorials see on web CBT tutorials see on

http://www. http://www. http://www.

http://www.microlabmicrolabmicrolabmicrolab....chchchch/academics/courses/academics/courses/academics/courses/academics/courses

How a silicon integrated circuit is made (web CBT)How a silicon integrated circuit is made (web CBT)How a silicon integrated circuit is made (web CBT)How a silicon integrated circuit is made (web CBT) A VLSI Tutorial up to chapter with NAND/NOR A VLSI Tutorial up to chapter with NAND/NOR A VLSI Tutorial up to chapter with NAND/NOR A VLSI Tutorial up to chapter with NAND/NOR

(web CBT from (web CBT from (web CBT from

(web CBT from UniUniUni Manchester)Uni Manchester)Manchester)Manchester)

T. HoffT. HoffT. HoffT. Hoff: Article about the : Article about the : Article about the : Article about the µµµµPPPP History (GHistory (GHistory (GermanHistory (Germanermanerman)))) To learn more about Intel’s early days and to ogle To learn more about Intel’s early days and to ogle To learn more about Intel’s early days and to ogle To learn more about Intel’s early days and to ogle

some die photos of oldie some die photos of oldie some die photos of oldie

some die photos of oldie----butbutbutbut----goodie chips browse goodie chips browse goodie chips browse goodie chips browse at the Intel link of the

at the Intel link of the at the Intel link of the

at the Intel link of the MicroLabMicroLabMicroLab VLSI course web MicroLab VLSI course web VLSI course web VLSI course web page.

page. page. page.

(29)

VLSI Design I

The MOSFET model The MOSFET modelThe MOSFET model

The MOSFET model Wow !Wow !Wow !Wow !

Are device models as Are device models asAre device models as Are device models as

nice as Cindy ? nice as Cindy ? nice as Cindy ? nice as Cindy ? Overview Overview Overview Overview

The large signal MOSFET model and second order The large signal MOSFET model and second order The large signal MOSFET model and second order The large signal MOSFET model and second order

effects. MOSFET capacitances. effects. MOSFET capacitances. effects. MOSFET capacitances. effects. MOSFET capacitances. Introduction in

Introduction in Introduction in

Introduction in fet fet fet process technologyfet process technologyprocess technologyprocess technology Goal:

Goal: Goal:

Goal: You can use the large signal equivalent MOS You can use the large signal equivalent MOS You can use the large signal equivalent MOS You can use the large signal equivalent MOS device equation. You are familiar with second order device equation. You are familiar with second order device equation. You are familiar with second order device equation. You are familiar with second order effects like body effect, channel length modulation. effects like body effect, channel length modulation. effects like body effect, channel length modulation. effects like body effect, channel length modulation. You know the MOS capacitances. You know the

You know the MOS capacitances. You know the You know the MOS capacitances. You know the You know the MOS capacitances. You know the basic steps in MOS fabrication.

basic steps in MOS fabrication. basic steps in MOS fabrication. basic steps in MOS fabrication.

(30)

Let’s build a MOSFET

There are lots of different recipes to choose from. There are lots of different recipes to choose from. There are lots of different recipes to choose from. There are lots of different recipes to choose from. Like most things in life, you get what you pay for: Like most things in life, you get what you pay for: Like most things in life, you get what you pay for: Like most things in life, you get what you pay for: the ability to have good bipolar devices, radiation the ability to have good bipolar devices, radiation the ability to have good bipolar devices, radiation the ability to have good bipolar devices, radiation hardness, reduced latch

hardness, reduced latch hardness, reduced latch

hardness, reduced latch----up and substrate noise, … up and substrate noise, … up and substrate noise, … up and substrate noise, … are all extra cost options. We’ll consider a general are all extra cost options. We’ll consider a general are all extra cost options. We’ll consider a general are all extra cost options. We’ll consider a general process: bulk CMOS with a p

process: bulk CMOS with a p process: bulk CMOS with a p

process: bulk CMOS with a p----type substrate:type substrate:type substrate:type substrate:

pppp----typetypetypetype

500um slice of a silicon ingot that has been 500um slice of a silicon ingot that has been 500um slice of a silicon ingot that has been 500um slice of a silicon ingot that has been doped with an acceptor (typically boron) to doped with an acceptor (typically boron) to doped with an acceptor (typically boron) to doped with an acceptor (typically boron) to increase the concentration of holes to 10 increase the concentration of holes to 10 increase the concentration of holes to 10

increase the concentration of holes to 1014141414_/cm_/cm_/cm_/cm3333

---- 1010101018181818_/cm_/cm_/cm_/cm3333_....

Back is meta Back is meta Back is meta

Back is metalllllilililizzzzed to provideed to provideed to provideed to provide a good ground connection. a good ground connection. a good ground connection. a good ground connection.

Good for n Good for n Good for n

Good for n----channel channel channel channel fetsfetsfetsfets, but p, but p, but p----channel, but p channelchannelchannel fets

fets fets

fets will need a nwill need a nwill need a n----type “well” (or tub) towill need a n type “well” (or tub) totype “well” (or tub) totype “well” (or tub) to live in! live in! live in! live in! Use <100> surface Use <100> surface Use <100> surface Use <100> surface to minimize surface to minimize surface to minimize surface to minimize surface charge charge charge charge

(31)

Next, a “thick” (0.4um) layer of silicon dioxide, called Next, a “thick” (0.4um) layer of silicon dioxide, called Next, a “thick” (0.4um) layer of silicon dioxide, called Next, a “thick” (0.4um) layer of silicon dioxide, called field oxide

field oxide field oxide

field oxide, is formed on the surface by oxidation in wet , is formed on the surface by oxidation in wet , is formed on the surface by oxidation in wet , is formed on the surface by oxidation in wet oxygen. This is then etched to expose surface where we oxygen. This is then etched to expose surface where we oxygen. This is then etched to expose surface where we oxygen. This is then etched to expose surface where we want to make a

want to make a want to make a

want to make a mosfetmosfetmosfet::::mosfet

pppp

Now grow a “thin” (0.01um = 100 Å) layer of silicon Now grow a “thin” (0.01um = 100 Å) layer of silicon Now grow a “thin” (0.01um = 100 Å) layer of silicon Now grow a “thin” (0.01um = 100 Å) layer of silicon dioxide, called gate oxide, on the surface by exposing the dioxide, called gate oxide, on the surface by exposing the dioxide, called gate oxide, on the surface by exposing the dioxide, called gate oxide, on the surface by exposing the wafer to dry oxygen.

wafer to dry oxygen. wafer to dry oxygen. wafer to dry oxygen.

pppp

The gate oxide needs to be of high quality: uniform The gate oxide needs to be of high quality: uniform The gate oxide needs to be of high quality: uniform The gate oxide needs to be of high quality: uniform thickness, no defects! The thinner the gate oxide, the thickness, no defects! The thinner the gate oxide, the thickness, no defects! The thinner the gate oxide, the thickness, no defects! The thinner the gate oxide, the more oomph the

more oomph the more oomph the

more oomph the fetfetfetfet will have (we’ll see why soon) but the will have (we’ll see why soon) but the will have (we’ll see why soon) but the will have (we’ll see why soon) but the harder it is to make it defect free.

harder it is to make it defect free. harder it is to make it defect free. harder it is to make it defect free.

(32)

On top of the thin oxide a 0.7um thick layer of On top of the thin oxide a 0.7um thick layer of On top of the thin oxide a 0.7um thick layer of On top of the thin oxide a 0.7um thick layer of polycrystalline silicon, called

polycrystalline silicon, called polycrystalline silicon, called

polycrystalline silicon, called polysiliconpolysiliconpolysiliconpolysilicon or or or or polypolypolypoly for for for for short, is deposited by CVD. The poly layer is patterned short, is deposited by CVD. The poly layer is patterned short, is deposited by CVD. The poly layer is patterned short, is deposited by CVD. The poly layer is patterned and plasma etched (thin ox not covered by poly is etched and plasma etched (thin ox not covered by poly is etched and plasma etched (thin ox not covered by poly is etched and plasma etched (thin ox not covered by poly is etched away too!) exposing the surface where the source and away too!) exposing the surface where the source and away too!) exposing the surface where the source and away too!) exposing the surface where the source and drain junctions will be formed:

drain junctions will be formed: drain junctions will be formed: drain junctions will be formed:

pppp field oxide field oxide field oxide field oxide poly wires poly wires poly wires poly wires gate oxide gate oxide gate oxide gate oxide

(only under poly) (only under poly) (only under poly) (only under poly)

exposed surface for source exposed surface for source exposed surface for source exposed surface for source and drain junctions

and drain junctions and drain junctions and drain junctions

Poly has a high sheet resistance (25 ohms/square) which Poly has a high sheet resistance (25 ohms/square) which Poly has a high sheet resistance (25 ohms/square) which Poly has a high sheet resistance (25 ohms/square) which can be reduced by adding a layer of a

can be reduced by adding a layer of a can be reduced by adding a layer of a

can be reduced by adding a layer of a silicidedsilicidedsilicided refractory silicided refractory refractory refractory metal such titanium (TiSi

metal such titanium (TiSi metal such titanium (TiSi

metal such titanium (TiSi₂₂₂₂), tantalum (TaSi), tantalum (TaSi), tantalum (TaSi), tantalum (TaSi₂₂₂₂) or ) or ) or ) or molybdenum (MoSi

molybdenum (MoSi molybdenum (MoSi

molybdenum (MoSi₂₂₂₂). These have sheet resistances of 1, ). These have sheet resistances of 1, ). These have sheet resistances of 1, ). These have sheet resistances of 1, 3 or 5 ohms per square, respectively. This is great for 3 or 5 ohms per square, respectively. This is great for 3 or 5 ohms per square, respectively. This is great for 3 or 5 ohms per square, respectively. This is great for memory structures that have lots of poly wiring.

memory structures that have lots of poly wiring. memory structures that have lots of poly wiring. memory structures that have lots of poly wiring.

(33)

The entire surface is doped, either by diffusion or ion The entire surface is doped, either by diffusion or ion The entire surface is doped, either by diffusion or ion The entire surface is doped, either by diffusion or ion implantation, with phosphorus (an electron

implantation, with phosphorus (an electron implantation, with phosphorus (an electron

implantation, with phosphorus (an electron donordonordonor) which donor) which ) which ) which creates two n

creates two n creates two n

creates two n----type regions in the substrate. The type regions in the substrate. The type regions in the substrate. The type regions in the substrate. The

phosphorus also penetrates the poly reducing its resistance phosphorus also penetrates the poly reducing its resistance phosphorus also penetrates the poly reducing its resistance phosphorus also penetrates the poly reducing its resistance and affecting the

and affecting the and affecting the

and affecting the nfet’snfet’snfet’snfet’s threshold.threshold.threshold.threshold.

pppp n+ wires: 20

n+ wires: 20 n+ wires: 20

n+ wires: 20----30 ohms/sq.30 ohms/sq.30 ohms/sq.30 ohms/sq.

Finally an intermediate oxide layer is grown and then Finally an intermediate oxide layer is grown and then Finally an intermediate oxide layer is grown and then Finally an intermediate oxide layer is grown and then reflowed

reflowed reflowed

reflowed to to to to flattenflattenflattenflatten its surface. Holes are etched in the its surface. Holes are etched in the its surface. Holes are etched in the its surface. Holes are etched in the oxide (where contacts to poly/diff are wanted) and oxide (where contacts to poly/diff are wanted) and oxide (where contacts to poly/diff are wanted) and oxide (where contacts to poly/diff are wanted) and alumi

alumi alumi

aluminnnnum deposited, patterned and etched.um deposited, patterned and etched.um deposited, patterned and etched.um deposited, patterned and etched.

metal wires (0.08 ohms/square) metal wires (0.08 ohms/square) metal wires (0.08 ohms/square) metal wires (0.08 ohms/square)

diff contact (0.25 diff contact (0.25 diff contact (0.25

diff contact (0.25 ---- 10 ohms)10 ohms)10 ohms)10 ohms) nnnn---- channel MOSchannel MOSchannel MOSchannel MOS

field effect transistor! field effect transistor! field effect transistor! field effect transistor!

diffusions are “self diffusions are “self diffusions are “self

diffusions are “self----aligned”aligned”aligned”aligned” with poly with poly with poly with poly n+ n+ n+ n+ n+n+n+n+ ??? ??? ??? ???

(34)

NFET Operation

SSSS GGGG DDDD BBBB n+ n+ n+ n+ n+n+n+n+ pppp mobile electrons, mobile electrons, mobile electrons, mobile electrons, fixed positive ions fixed positive ions fixed positive ions fixed positive ions (n+ means heavily (n+ means heavily (n+ means heavily (n+ means heavily doped with donors, doped with donors, doped with donors, doped with donors, doesn’t imply doesn’t imply doesn’t imply doesn’t imply positive charge!) positive charge!) positive charge!) positive charge!) mobile holes, mobile holes, mobile holes, mobile holes, fixed negative ions fixed negative ions fixed negative ions fixed negative ions

depletion layer depletion layer depletion layer depletion layer no mobile carriers, no mobile carriers, no mobile carriers, no mobile carriers, but fixed negative ions but fixed negative ions but fixed negative ions but fixed negative ions (slight intrusion into n+, (slight intrusion into n+, (slight intrusion into n+, (slight intrusion into n+, but mostly in p area) but mostly in p area) but mostly in p area) but mostly in p area)

Picture shows configuration when Picture shows configuration when Picture shows configuration when

Picture shows configuration when VgsVgsVgsVgs < < < < VtoVtoVtoVto

BBBB

SSSS DDDD

GGGG Terminal with higher Terminal with higher Terminal with higher Terminal with higher _{voltage is labelled D,}_{voltage is labelled D,}_{voltage is labelled D,}_{voltage is labelled D,} the other is labelled S the other is labelled S the other is labelled S the other is labelled S so Ids >= 0. so Ids >= 0. so Ids >= 0. so Ids >= 0. IIII_ds_ds_ds_ds = 0= 0= 0= 0 Other symbols: Other symbols: Other symbols: Other symbols:

almost always ground almost always ground almost always ground almost always ground

(35)

FET = field effect transistor

The four terminals of a The four terminals of a The four terminals of a

The four terminals of a fetfetfetfet (gate, source, drain and bulk) (gate, source, drain and bulk) (gate, source, drain and bulk) (gate, source, drain and bulk) connect to conducting surfaces that generate a complicated connect to conducting surfaces that generate a complicated connect to conducting surfaces that generate a complicated connect to conducting surfaces that generate a complicated set of electric fields in the channel region which depend on set of electric fields in the channel region which depend on set of electric fields in the channel region which depend on set of electric fields in the channel region which depend on the relative voltages of each terminal.

the relative voltages of each terminal. the relative voltages of each terminal. the relative voltages of each terminal.

EEEE_hhhh EEEE_vvvv source

source source

source draindraindraindrain gate gate gate gate bulk bulk bulk bulk INVERSION: INVERSION: INVERSION: INVERSION: A sufficiently A sufficiently A sufficiently

A sufficiently ststststrrrrononongggg verticalon verticalverticalvertical field will attract enough field will attract enough field will attract enough field will attract enough electrons to the surface to electrons to the surface to electrons to the surface to electrons to the surface to create a conducting n create a conducting n create a conducting n

create a conducting n----type channel type channel type channel type channel between the source and drain. between the source and drain. between the source and drain. between the source and drain.

CONDUCTION: CONDUCTION: CONDUCTION: CONDUCTION: If a channel exists, a If a channel exists, a If a channel exists, a If a channel exists, a horizontal field will cause horizontal field will cause horizontal field will cause horizontal field will cause a drift current from the a drift current from the a drift current from the a drift current from the drain to the source. drain to the source. drain to the source. drain to the source. Expect Ids proportional Expect Ids proportional Expect Ids proportional Expect Ids proportional to to to to VdsVdsVds*(W/L)?Vds*(W/L)?*(W/L)?*(W/L)? inversion inversion inversion inversion happens here happens here happens here happens here Picture shows configuration

Picture shows configuration Picture shows configuration Picture shows configuration

when when when