Development and characterization of a sub-micron CMOS process as an educational tool at RIT

Rochester Institute of Technology

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11-1-2000

Development and characterization of a sub-micron

CMOS process as an educational tool at RIT

Ivan Puchades

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Recommended Citation

DEVELOPMENT AND CHARACTERIZATION OF A SUB-MICRON

CMOS PROCESS AS AN EDUCATIONAL TOOL AT RIT

by

Ivan Puchades

A thesis Submitted

in

Partial Fulfillment

of the

Requirements for the Degree of

MASTER OF SCIENCE

in

Electrical Engineering

Approved by:

PROF: --'-A..;.;,.lb;.:..e~r....:..t.;;....;H.;..."T;..;.it~u....:..s _

(Thesis Advisor)

PROF: _

PROF: _

PROF: _

(Department Head)

DEPARTMENT OF ELECTRICAL ENGINEERING

COLLEGE OF ENGINEERING

ROCHESTER INSTITUTE OF TECHNOLOGY

ROCHESTER, NEW YORK

THESIS RELEASE PERMISSION FORM

COLLEGE OF ENGINEERING

ROCHESTER INSTITUTE OF TECHNOLOGY

Title of Thesis:

DEVELOPMENT AND CHARACTERIZATION OF A SUB-MICRON CMOS

PROCESS AS AN EDUCATIONAL TOOL AT RIT

I, Ivan Puchades, hereby grant permission to the Wallace Memorial Library of the

Rochester Institute of Technology to reproduce the thesis in whole or in part. Any

reproduction will not be for commercial use or profit.

Signature

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0/

Table

Contents

LIST OFTABLES v

LIST OFFIGURES vi

1. INTRODUCTION 1

2. BACKGROUNDANDLITERATUREREVIEW 6

2.1. IC_{Manufacturing}EducationatRochester Instituteof_Technology 6

2.2. ProcessBackground 14

2.2.1. Advanced CMOS process_Technology 15

2.2.1.1. Historical TrendandPredictions 15

2.2. 1.2. ScalingRequirements 17

2.2.1.3. Ideal_Scalingvs. Actual_Scaling 18

2.2. 1.4. First _ScalingChallenges- Submicron Devices 21

2.2.1.4.1. Substrate_doping 21

2.2. 1.4.2. LightlyDoped Drains

-High energycarriers and short-channel

effects 25

2.2.1.4.3. Shallow

junctions-Xj 32

2.2.1.4.4. Gateoxideintegrity

-tox 34

2.2. 1.5. Latest Developments 37

2.2.2. RlT's CMOS P-_{wellProcess 45}

2.2.2.1. Substrate Preparation 46

2.2.2.3. Interconnects 50

2.2.2.4. Test 51

2.2.2.5. SPICE Parameters 59

2.2.3. RIT's Submicron CMOS Process 65

2.2.3.1. SubmicronCMOS Design 66

2.2.3.2. Submicron CMOS Process 69

2.2.3.2. 1. Substrate Preparation 70

2.2.3.2.2. Build Transistors 72

2.2.3.2.3. Interconnects 74

2.2.3.2.4. Test 75

2.2.3.2.5. Device Simulation 79

3. PROCESS IMPROVEMENTS 85

3.1. _Lithography- 1

urnResolution 87

3.2. Etch 88

3.2.1. Polysilicon Etch 88

3.2.2. LTO Etch- Spacers_andContactCuts 90

3.3. Diffusion 93

3.3.1. PadOxide 93

3.3.2. Well LOCOS Oxidation 94

3.3.3. Twin-Well Drive 95

3.3.4. Field Oxide Growth 96

3.3.5. Sacrificial Kooi Oxide 96

3.3.6. Gate Oxide 97

m-3.3.7. _{Poly Doping}Drive-in 98

3.3.8. Spacer Densification 98

3.3.9. D/S ActivationAnneal 99

4. PROCESS DETAILS 102

5. TESTRESULTS , 138

5.1. Process_Testing s 139

5.1.1. NMOS 139

5.1.2. PMOS 140

5.2. NMOS SPICE Parameters 146

5.3. Recommended Test Improvements 150

6. CONCLUSION AND FUTURE WORK 152

APPENDIX 154

A. PROCESS PICTURES 155

B. Silvaco's SUPREM SIMULATION INPUT FILES 173

List

Tables

Table 2.1a. PredictedprocessdevelopmentsatRTT 13

Table 2.1b. HistoricalTrend-Moore'sLaw 15

Table 2.2. 1994and 1996 _SAIRoadmap 16

Table 2.3.Ideal_ScalingRules 18

Table2.3. Comparisonof advanced processes 44

Tabel2.4.Teststructures and parameters extractedintheRITP-Well CMOS Process..52

Table2.5. _SummaryofrecentRIT P-Well CMOS Test Results _[5] 68

Table 2.6. _Summaryof simulation resultsfor 0.5umdevices 79

List

Figures

Figure 2.1. Short-channeleffects 17

Figure 2.2. Microtec Simulation- Typical

Retrogradewell_doingprofile 24

Figure 2.3. Lateralcomponentofthesurface electricfield 26

Figure2.4.IGvs. VGwithVDof_10V, 12V and 14V _[20] 28

Figure2.5.Fabricationsequence of_LightlyDopedDrains 29

Figure2.6.Verticalelectricfield for LDDvs. Non-LDDtransistors 30

Figure 2.7Surfacepotentialinthechannelfor_longand shortchanneldevices. Linear

and saturatedVtroll-off effects 31

Figure2.8. Typicalthreshold-_{voltage roll-off as afunctionof gatepoly-Silength fora}

setdrainvoltage 32

Figure 2.9. Oxide breakdown_frequency as afunctionof appliedfield 34

Figure 2.10. Inversion layer junctions _[31] 43

Figure2.11. Processcross-sectionafter substratepreparation 48

Figure 2.12.Processcross-section. Completedtransistors 50

Figure2.13. Processcross-section. Completed inverter device 51

Figure 2.14._Test-chiplayoutfortheRIT P-Well CMOS Process 53

Figure 2.15. Van Der Pauwstructureusedin Sheet Resistanceextraction 54

Figure 2.16. CrossBridge Kelvinteststructure forcontact resistance 55

Figure 2.18. NMOSFET layoutstructure 56

Figure 2.19. P-WellandN-well_dopingprofiles afterdrive-in 71

Figure 2.20. Processcross-section after substrate preparation 71

Figure 2.21. LDD's junctionprofiles 74

Figure2.22. Processcross-section. Completedtransistors 74

Figure 2.23. Processcross-section. Completedinverter device 75

Figure 2.24. The Submicron CMOS Process_Test-Chip Layout 77

Figure 2.25. Differentsize capacitorsto _studygate oxide_qualityVTshifts 78

Figure 2.26. DifferentsizeNMOS transistorsto_{study VT}roll-offand short channel

effects ₇₈

Figure3.1.Micrographsofthinnedgatelines 88

Figure3.2. _Anisotropy 89

Figure3.3.Over-etched Contact Cuts 90

Figure3.4. Fabricationsequence of_LightlyDoped Drains 91

Figure 3.5. Contact Cut Etch SEM 92

Figure 3.6. Twin-well Cross-section. SUPREM Simulation output 95

Figure 3.7. Twin-well junction depths 96

Figure 3.8.FOXandKooiOxideSUPREM Simulation 97

Figure 3.9.N+ andNLDD SUPREM Junction Depth Profile 99

Figure 3.10. P+andPLDD SUPREM Junction Depth Profile 100

Figure 4.1. 1st

Level_Lithography- N-well. SUPREM Simulation

106

Figure 4.2.After N-well Oxidation. SUPREM Simulation 109

Figure4.3.After Twin-Well Drive. SUPREMSimulation Ill

Figure 4.4. Alignmentandresolutionverniers 113

Figure 4.5. After Channel _StopImplant. SUPREM Simulation 115

Figure 4.6. AfterField Oxidegrowth. SUPREMSimulation 117

Figure 4.7._VtpAdjust Implant. SUPREMSimulation 120

Figure 4.8.After_Polyetch. _{SUPREM Simulation} 125

Figure 4.9. AfterSpaceEtch Back. SUPREMSimulation 129

Figure4.10. After D/S Anneal.SUPREM Simulation 133

Figure 5.1. Micrograph_showingthe _{l.lum poly}gate 140

Figure 5.2a,b. Thresholdvoltage extrapolation and _familyof curvesfor NMOS 140

Figure5.3. _Familyof curves of aPMOS transistor 141

Figure5.4. Low resistance pathbetweensource anddrain areasofthePMOS

transistors 142

Figure 5.5. Drain todrainresistance 143

Figure5.6. Lowresistance pathbetweenthedrainareas oftwodifferent PMOS

transistorsinsidethen-well 143

Figure 5.7. Lowresistance pathbetweenthedrainareas oftwo different PMOS

transistorsin differentn-wells 144

Figure5.8. A leakagepath existsinthep-well 145

Figure5.9. Terada-Muta Method for extracting Leff 148

Chapter 1

Introduction

1. Introduction

Rochester Institute of _Technology is recognized worldwide for its educational

programs and _laboratory facilities in the area of microelectronic _{manufacturing}

engineering. In this state-of-the-art _facility, graduate and undergraduate students design

and manufactureintegratedcircuits_usingPMOS, BJTandCMOS technologies.

In a recent article published in the December 1999 edition of Solid State

Technology magazine, author _Stanley Wolf expresses his concern about the lack of

cohesive education programs _{for IC manufacturing in} the U.S. He also concludes that

there is "a shortage of_{engineering graduates, especially} those from the _pioneering and

renowned IC manufacturing program atthe Rochester Institute of _Technology (RIT).

Numbering about 35-55/year _{(approximately} 30 BS, 10 MS, and 3 _PhDs), the RIT

graduates are _only a small fraction of the engineers _{entering IC manufacturing every}

year."[l]

Inorderto_{keepprovidinghighly}qualifiedengineersRITmust_keeppace withthe

rapid evolution ofthe IC _{manufacturing} industry, thus RIT must _continuously improve

exclusively using Submicron CMOS process technology. This implies that RIT must

improve its CMOS processto theSubmicronregionalso.

AnadvancedSubmicronCMOSprocesshasbeen developed and characterizedfor

use at RIT. The new process features _many advance device structures such as dual well,

sidewall spacers andlow-doped drains.

This project starts withthe literature review ofthemostrecent as well as the not

so-recent advances inthe front end ofIC manufacturing. The frontend is defined as the

manufacturing steps that deal with the fabrication of the transistorper _se, prior to a

secondlevel of metaldeposition. It doesnotincludeprocesses such as CMP or_anyother

planarization techniques. Although enormous improvements have been developed in the

areas, these are not included inthis work due to the vast_complexity this would entail. It

also goes beyondtheprocessdeveloped inthis thesisand reviewsthelatest developments

upto thefutureyear2010andbeyond.

It also reviews what is currently the most advanced process at the RIT _Factory

lab, the CMOS P-Well Process. It presents the sequential process steps and aid tools

which are availabletoall students.A summary ofthe most recent results anddevice data

isalso presentedinthissection.

Thebasis forthe developmentofthisprojectistheworkof graduate student_Suraj

Bashkaranin the developmentofthe RIT's Sub-Micron CMOSProcess. His work looks

at the design consideration as well as the process flow andboth process simulation and

RIT has developed a large base of _previously successful technologies. The new

process is an evolution from these _previously successful technologies. _{The majority} of

the project is developed on _{existing equipment, using} modified versions of proven

process sequences. Theseprocess improvements arepresentedin Chapter 3. Atypical IC

manufacturing process is divided in production groups. Each ofthese groups develops

theirown processes tolaterintegratethem togetherwiththeothers. Asimilarapproachis

followed in this project. Separate process steps are developed _{independently} and then

integratedtogether when needed. When avalid process _alreadyexists, this is used as is.

The separate _processing disciplines and the improvements generated in each are

described below. The integrationof alltheseimprovements ispresentedin Chapter 4.

Processing pictures, which are included in the appendix of this thesis, are also

available at _{every step} of the process as a visual aid in _determining the proper action

when problems arise. Thesetwo aids are a_keyplayerto the successful completionofthe

process.

Two 3-wafer lots where _exclusivelyprocessedat RIT usingthe _{newly developed}

Submicron CMOS Process flow, which is described in detailed in chapter 4. The

electrical test ofthese two lots show _promising results although some work must still be

done to further improve the device characteristics. The NMOS and PMOS devices are

tested for _{functionality} and SPICE parameters are extracted when possible. Some

assumptions are made when extracted SPICE parameters and these are noted. The

assumption of some _key values is _necessary in order to overcome some non-idealities

brought about _by a design error. Due to a design error the PMOS devices do not show

3-transistorcharacteristics and theNMOS deviceshave an_{extremely large leakage} current

at OV gate bias. The root cause of this error has been investigated and a solution has

alreadybeenputintoplace.

Due to the successful completion of this project, students from the

Microelectronic department of RIT will use this process flow starting in the winter

quarter of2000. _They will follow the_{newly developed}processinthefabrication oftheir

designed IC's. Theextraction ofSpiceparameters will also allow the accurate simulation

of these designs prior to their fabrication. This will place RIT at the _top of the

Universities _{offering semiconductor-manufacturing} programs and will _help further

References

1.

Chapter 2

Background

and

Literature

Review

2.1 IC_{Manufacturing} EducationatRochester Instituteof_Technology

Stanley Wolf is the well-renowned author of the three-part series Silicon

Processingforthe VLSI Era and owner ofLattice Press. In a recent articlepublished in

the December 1999 edition of Solid State _{Technology magazine,} Wolf expresses his

concern about thelack ofcohesive education programs for IC manufacturing in the U.S.

Wolf points out that despite the imminent need of IC manufacturing Engineers on the

work place, and although "engineers and scientist are well educated in specific

disciplines, such as electrical engineering, chemistry, physics, materials science,

mechanical _engineering, and _{optics, they} still enter the _industry untrained for IC

manufacturing. _{By-and-large,} even at the_{engineeringlevel, trainingin IC manufacturing}

is still_occurring onthejob" [1]. _Accordingto_{Wolf, engineering} educationhas failed to

change and supportwhatisthecornerstone_industryintoday's society,ICmanufacturing.

Wolfs perspective comes from seeing the shortage of_recent, up-to-date semiconductor

textbooks. Fourofthefive_top-sellingtextbooksonthesubjecthavecopyrightdatescirca

1990. This means that the most modern developments in _technology, which have

Finally, he concludes with a statement that has been the motivation for the

developmentof_{this thesis work;}

"There is a shortage of_{engineering graduates, especially} those from the pioneering and renowned IC _{manufacturing} program at the Rochester

Institute of _{Technology (RIT). Numbering} about 35-55/year

(approximately 30 _BS, 10 _MS, and3 _PhDs), the RIT graduates.are _only a smallfractionoftheengineers _{enteringIC manufacturing every}

year."

Other universities which have IC _{Manufacturing} facilities include, Boise State

University, University of _{Illinois, Standford, MIT,} UC _Berkely, UCLA, _University of

Michigan, University of Texas _Austin, Arizona State University, National Chiao _Tung

University and others [6]. The _laboratory courses offered _by these universities follow

along the lines ofthe more traditional hands-on courses taught at RIT. Although much

researchisconductedintheseuniversities,this _{is mainly}undertaken_by graduate students

and in only very specific subjects. The uniqueness of the Rochester Institute of

Technology laboratory is its _capability of _completing a CMOS process _by its

undergraduate students and_fabricatingcomplex circuit anddevices.

Rochester Institute of _Technology started its Microelectronic _Engineering

program in 1986. Graduates from this program are _highly sought after _{by leading}

Semiconductor companies and are often commended on their preparation and

performance as _they reach the work place. The success ofthis programis greatly due to

the excellent clean room facility, which is available to all _students, undergraduates and

graduates alike. RIT has invested heavily inthehands-onteaching methodology. The IC

laboratory at RIT is one ofthe largest at _{any university}with a cleanroomfloor space of

over 15,000 square feet [3]. The facility has a complete equipment set for the

7-manufacture of silicon integrated circuits on 4 inch and 6 inch diameter wafers. The

equipment _includes, IC Design _Tools, Electron Beam Maskmaking, 1 GCA g-line

stepper, a Canon Mine _{stepper, ASM} 248nm Excimer Laser Stepper, 193nm Excimer

laser _{Lithography System, Low Pressure Chemical Vapor Deposition system, Varian}

120-10 Ion _Implanter, Varian 400-10 Ion Implanter, Wafer Coat and _{Develop Systems,}

Reactive Ion Etch _systems, Wet Etch and RCA Clean _Benches, Surface Analysis

Systems, Spectroscopic and Ellipsometric _{Metrology Tools,} Profilometer, Chemical

Mechanical _Polishing, Electrical Test and Probe Systems and _Scanning Electron

Microscopy.

Several courses take advantage of these facilities with classic _laboratory

participation such as _{Microlithography} I and U and Thin Films. At these middle-level

courses, students are passive participants on a traditional _laboratory experience. The

instructor, with the _help of a graduate _assistant, performs well-rehearsed experiments

during which the students learn basic IC manufacturing techniques. All these courses

complementthreehour/week_lectures, whichpresentanddiscussthe topicscoveredin lab

aswellas others.

Students also become familiarized with a _variety of_{IC manufacturing} processes

such asthecompletefabricationoffourmask-levelMetalGate PMOS transistorsontheir

sophomore yearaswellas a triple-diffusedNPN BJTprocess _{[2] during}theirfourthyear.

As in atraditional _{university IC} laboratory, students take a few wafers and start at _step

These _classes, for the most _part, follow the concurrent _{(hands-on) teaching}

methodology describedbyAzavedo[4]. This_{teachingmethodology}facesthe"paradoxes"

and pitfalls presented _by the more classical method ofteaching: sequential teaching. In

sequential _teaching the curriculum is organized _{by following} the logical or historical

structure ofthesubjects tobestudied. Thecontent is divided intotopicsand eachtopicis

presented in depth. "The focus is then on programmatic content and _clarity of

exposition". Theclass presentationsexpose fixed protocols forpredetermined problems

and solutions where "The teacherpossesses all theknowledge". Azavedo recognizes the

pitfalls ofthe sequential _{teaching methodology by saying} that students are "reduced to

memorizing names and algorithms"

[4]. The above-mentioned courses address these

issues _{by creating} open-ended experiments _during laboratory. Students use _previously

learnt skills such as designofexperiments ordevicephysics tocreatetheirown courseof

action to resolve a specific problem presented _by the teacher. The teacher becomes a

mere consultanttothestudents project. Oncetheprojecthas beencompleted, the students

presentthe findings to the rest oftheclass and answer questions from the teacher. Their

gradeis basedontheexperimental designand amounteffortputinto solvingtheproblem

as well as on their _{final understanding} ofthe issue. A _faulty experimental process does

not mean a _failing grade as _long as the students can comprehend the issue under _study

andexplaintheirmisconceptionsandhow thecorrectedthem.

On the _study and evaluation of a similar course taught at San Jose State of

University [5], researchers found that students felt that _they have learned more than in

traditionalclassrooms. Inthe study,25%ofthestudents indicatedthat_theywereinactive

9-in the classroom. In _contrast, all of them thought that _they were active or moderate

participants inthelaboratory.

During theirfifth andlast_year, undergraduate students at RIT take an even more

untraditional type of _course, an IC _{Manufacturing Laboratory using} a student operated

factory[3]. Inthis course aP-Well CMOS processis used asan educational tool toteach

advanced _{manufacturing} processes. The students in the course are the operators for the

factory. The instructor is the shift manager and the different _laboratory sections are the

different shifts. _Typically inone schoolterm there are4 to 6 shifts in aweek. Eachshift

begins with a shift _meeting where the shift manager reviews the status ofthe lots in the

factory. Assignments are made for each operator based on lot selection rules and

equipment _availability and the past experience of the operator. In this _factory the

operators are encouraged to do operations that _theyhave notdone before and to average

twolot moves per shift. _Depending onthenumber ofstudents in the lab section and the

queue status operator assignments are made. At the _beginning of the school term

operators are _usually assigned in pairs to work on lots. Towards the end ofthe school

term assignments are made one lot per student. The instructor and _teaching assistant

rotate around lab from operator to operator _helping with some _{details, answering}

questions, asking questions and _solving problems. The students _keep a lab notebook to

documentwhat_theydideachweek,includingobservations,dataand other entries.

The fact that students act as operators could raise some concerns on the actual

learning accomplished. This is acommon problemwith most_laboratoryexperiences and

moving lots into their pertinent _{processing steps,} students must be able to _identify at

which_step thatparticularlot is and whether or notithas beenprocessed_correctlytothat

point. Then_theymust_correctlyperformthe _steptheyhavebeenassigned and understand

how it ties to the _200-step process and how it would affect the final product. _Finally, if

problems _{arise, the} student mustbe able to_identify a course of action _{to remedy} it. This

is all done with the aide ofthe instructor and several other resources such as in process

monitoringand_metrologytools.

This course could be classified as a extreme of concurrent _teaching [4]. _Again,

concurrent _teaching exposes student to concrete _engineering problems that require

knowledge ofthe contents of the discipline. It places them, as much as _possible, in the

shoes of the engineer in that he student describes the problem, devises a solution and

presents and/or manages it. In this _{teaching methodology knowledge is constructed,}

althoughbasic knowledge ofthe basic processes is required. The students work and the

teacher supervises _guiding them inthe right direction. Students become problem-solvers

and are comfortable_takingupnewchallenges.

Thiscourse also overcomes the twoparadoxes of_engineeringeducationfound_by

Azavado,theparadox_ofmultidisciplinaryandtheparadox_ofthespecialist.The.paradox

of multidisciplinary deals with the need of _combining multiple disciplines in solving a

problem. With theincrease interaction and integration of_{technologies, multidisciplinary}

problems ariseconstantly._According toMuscatet_al.,Microelectronic device fabrication

is _{inherently interdisciplinary} [5]. Each of the basic processes draws upon a varied

spectrum of subjects such as physics, chemistry and chemical _material, electrical

engineering. Although all these subjects have been studied _by Microelectronic

Engineering students at RIT _during the previous years, it is not until the present_course,

IC_{ManufacturingLaboratory,} that_theygettointeractalltheirknowledge. Thissimulates

what_theywillbe_doingintheworkforce.

The second is theparadox _ofthe specialist. Azavado considers it "impossible to

teach alltheknowledgethat an engineeris expectedtouse today".Teachersdo notknow

what will be required for engineers to know in the future. It is also impossible to teach

everything in the allotted amount of time. On the other _hand, this course provides

students with the skills and_{understanding necessary} to tackle _{any engineering} problems

that_mayarise attheworkplacewithconfidence.

There is nodoubt that the _Factory course has become a_very useful _learning tool

for students. Onthe other _hand, the RIT P-Well CMOS process used in this course was

developed eight years ago. _{Unfortunately,} as the _{IC manufacturing industry} has been

developing,it has fallen alongthelines described above_byWolf. It does notinclude any

ofthemost moderndevelopments in technology,whichhave happened in thelate 1990's.

The manufacturing development of a Sub-Micron CMOS process is proposed.

This would take advantage of the most advance equipment available in the RIT

Microelectronic Manufacturing facility. This equipment is capable of Sub-Micron

resolution,whichwouldbeusablefor Logic designas wellas_Analogcircuitry.

Table 2.1a summarizes the advances that are included in the RIT's Submicron

positon RIT in a level where advance research that would benefit the microelectronic

industrycanbeconducted.

The completion of this project would benefit the RTT College of _Engineering

enormously. Not only would undergraduate students be exposed to the most advanced

manufacturing processes but graduate students from the Electrical Engineering,

Computer_Engineering andMicroelectronic_Engineeringdepartmentswould alsohavethe

chanceto_{actuallyfabricating}theirownICdesigns ina_timelymanner.

Present Process Submicron RIT Process

,\,^,..>,^.,.-v,;.'..-,.,i.S,

Advanced RIT Process

P-Well

PMOS+NMOSVtadjustI

j

N+-polyGate

Analog/Digital 12V/5V Design lambda= _3-micron

"RIT's design

rules"

100mmsubstrate

Twin-Well No VTadjustI

MinimumCD: 1-micron

CanonI-line LOCOS Isolation 150A Gateoxide

Gatespacers andLDDs

N+-polyGate '-

-Analog/Digital 5V/5V Designlambda=0.5-micron

MOSIS designrules

150mmsubstrate

-Twin-Well No VT-adjust I

Minimum CD: 0.5-micron ASML Excimer Laser STI Isolation

100A Gateoxide

SpacersandLDDs TiN Contact/Metal Liner Dualdoped poly Gate Analog/Digital

Designlambda=0.25-micron

MOSIS designrules

150mmsubstrate

2000 2001

Table 2.1a. PredictedprocessdevelopmentsatRIT

2.2Process Background

The _following sections deal with the most recent as well as the not so-recent

advances in the front end of IC manufacturing. The front end is defined as the

manufacturing steps that deal with the fabrication of the transistor per _se, prior to a

secondlevel of metaldeposition. Itdoes notincludeprocesses such as CMP or_anyother

planarization techniques. Althoughenormous improvements have been developed inthe

areas, theseare notincludedinthisworkduetothevast_complexitythiswould entail.

The first section deals with the main advances developed in the 1990's and that

are not included in the current RIT CMOS P-Well Process. It also goes beyond the

process developed inthis thesisand reviews the_{latest developments up}to the future year

2010andbeyond. Thesecond section explains what_{is currently done} at the RIT _Factory

lab, the CMOS P-Well Process. It presents the sequential process steps and aid tools

which are availableto all students. A summaryofthemostrecent results anddevice data

is also presented on this section. The third section reviews thework of graduate student

Suraj Bashkaran inthedevelopmentofthe RIT'sSub-Micron CMOS Process. It looks at

the design consideration as well as the process flow and both process simulation and

2.2.1 AdvancedCMOS process

Technology

MOSFET miniaturization has been anissue of_studyever since the development

of the first integrated circuit. _According to _[7], large-scale-integrated circuits _(LSI's)

appeared in the _{early 1970's} with the introduction of a 1-kb dynamic random access

memory DRAMand a _{0.75-MHzmicroprocessor}

using 10-8um PMOS technologies [7].

Digital and _memory circuit applications benefit the most from the _{scaling down} of

MOSFET devices. Smaller dimensions mean _{higher packing density} and either more

memorystorage_capabilityorfaster switchingspeedfor logic_technology[8].

2.2.1.1 HistoricalTrendandPredictions

According to Moore's law _[9] the number oftransistors per _chip would double

every 18 months orincrease_by afactor offour everythree years. This prediction, made

in _1975, has heldtrue for over 25 year. Table 2.1b shows how this trend _{has been very}

closely followedhistorically[7].

Year 1974 1977 1980 1983 1986 1989 1992 1995 1998

Sizeum 6.0 4.0 3.0 2.0 1.2 0.8 0.5 0.35 0.25

Shrinkrate 0.67 0.75 0.67 0.6 0.67 0.63 0.70 0.71

DRAM 4K 16K 64K 256K 1M 4M 16M 64M 256M

Table 2.1b. Historical Trend- Moore's Law

The Semiconductor _Industry Association _(SIA) published in 1994 a _{roadmap for}

semiconductors topredicttheevolutionofthe_industryuntil theyear2010 [10]. Thiswas

15-later revised in 1996 and although it shows a slight slow down in the _{shrinking rate,} it

still follows Moore's law _{accurately [11]. Table} 2.2 presents these two trends predicted

bySIA.

Year 1995 1998 2001 2004 2007 2010

Sizeum 0.35 0.25 0.18 0.13 0.10 0.07

Shrinkrate _{0.71 0.72 0.72 0.77} 0.70

DRAM 64M 256M 1G 4G 16G 64G

YEAR 1997 1999 2001 2003 2006 2009 1012

Denselines:Halfpitch_(um) 0.25 0.18 0.15 0.13 0.10 0.07 0.05

Shrinkrate 0.72 0.83 0.86 0.77 0.7 0.71

Isolated Lines: gate_(um) 0.20 0.14 0.12 0.10 0.07 0.05 0.035

Shrinkrate 0.70 0.86 0.83 0.70 0.71 0.70

DRAM @ introduction 256M 1G 4G 16G 64G 256G

DRAM @ production 64M 256M 1G 4G 16G 64G

Table2.2. 1994and1996 SAI_Roadmap

This trend is _likely to be followed since there have been announcements of the

fabrication of0.15 _um, 0.1um and evensub-O.lum MOSFETdevices _by several authors

at the research level [12] [15]. These authors have reported on the good operation of

these devicesat roomtemperature andthetechniquesutilized fortheir fabrication. These

2.2.1.2_ScalingRequirements

In digital circuit _{applications,} a MOSFET functions as a switch. _Ideally, in the

"off state no current shouldflow and low resistance orhigh currentshould bepresentin

the"on" state. Smallcapacitancesare alsoimportanttoallow rapidswitching.As thegate

length_decreases, itbecomes difficultto_{simultaneously}meetthesetworequirements.

In small _devices, even in the "off state, due to the _proximity of the drain and

source ofthe _device, theleakagecurrent fromsource to drainincreases. This is the

well-known short channel effect of the MOSFET's [7]. The extension of the drain

space-charge region is suchthat it touches the sourceregion as soon as a_very small voltage is

appliedto the gate, thus_creating alower-than-designedthreshold voltage, alsoknown as

drain induced barrier _{lowering (DIBL)} effect, and lager leakage characteristics in the

"offstate (Figure 2.1). Thesuppressionof short-channel effects is oneofthe mainareas

ofinterestwhen_shrinkingthedevicedimensions.

OV

OV Vdd

Gate

Source Drain

"\, Space Charge Region

Figure 2.1. Short-channeleffects

Smallergatelengths are desirableinthe

"on"

statebecause itreduces thechannel

resistance oftheMOSFET 's. When this channel resistanceequals thatofthe source and

drain regions, the device cannot be improved. _Thus, reduction ofthe source and drain

resistances is necessary inordertomake_scalingeffective.

To summarize, the_scalingofMOSFET devices is _onlyeffective ifimprovements

oftheMOSFET performance areaccomplished. These improvementsare often related to

newfabrication and_{manufacturingtechniques.}

2.2.1.3 Ideal_Scalingvs.Actual_Scaling

In order to suppress short-channel effects and secure good _switching

characteristics, Dennard et al. _[16] proposed an _{idealized scaling} method. _Using this

method, theparameters oftheMOSFET deviceare shrunk orincreased_by afactor ofK.

Table 2.3 shows how each parameter is modified _by K. _Thus, the space charge layer

would be reduced with the reduction in channel _{length, leading} to the suppression of

short-channel effects.

Scaling rule_(Ideal) Gate lenqth(Lg) 1/K

Parameter Scale Gatewidth_(Wq) 1/K

Gate Area_(Sg) 1/K*2

CD > o w "to c (0 1 H

Gate lenqth(Lq) 1/K Gateoxide_(tox) 1/K

Gatewidth _(Wq) 1/K Supplyvoltaqe 1/K

Gateoxide_(tox) 1/K Q)

_)

Gatecapacitance_(c)~Sq/tox 1/K

Junction depth_(xj) 1/K Gatecharge_(Qg) ~Cg*V 1.KA2

Sub, imp.Cone. _(Nsub) K Propaqation_{delay (tpd)} ~Qq/ld 1/K

Drain Voltaqe_(Vd) 1/K Clockfrequency (f) ~1/tpd K

DrainCurrent(Id) 1/K NumberofTransistors_(n) K*2

Thresholdvoltaqe(Vth) 1/K Chipsize_(Sc) ~n*Sq 1

Propaqationdelay(tpd) 1/K Power(P)-0.5

* f*

n*C*

V*2 1

This method also calls for a reduction of the power _{supply by} a factor of _1/K,

which in turn would result in a current reduction _by the same factor. The increase on

number oftransistors is also _determined atK2. The powerconsumption and_chiparea are

also keptconstant. Had this _{ideal scaling} been followed since _1974, the most advanced

LSIsystems wouldbe 1-Mb DRAMand34MHzmicroprocessors [7].

Fortunately for the microelectronic _industry, the _{ideal scaling} method was not

followed. _{The supply}voltage was not changedinthe_earlystages ofMOSFET scaling[7].

This was done in orderto _keep a _{compatibility} with the _supply voltage ofconventional

systems and alsoto obtain ahigher operating speed underhighelectric _{fields. The supply}

voltage was not reduced untiltheelectric field across thegate oxide reached the electron

tunneling limit of ~4MV/cm. This occurred _during the development of the 0.5um gate

length MOSFET technology; whenthe gate oxidethickness approached 120A.

In _1980,Brewset al. _[17] derived an empirical_{relationship between}theminimum

length and other device parameters; this must be kept in order to obtain _long channel

behavior. Theproposedempirical relationforanNMOStransistoris:

L^^OAl-lxjtJw.+wj]", (2.1)

where _L^ isthe minimum channel length forwhichlong-channel behavioris observed,

A is a _{proportionality} factor, _xi is the junction depth, tBX the oxide thickness and

ws+_wdthe sum of source and drain depletion depths in a one dimensional abrupt

junctionformulation. Suchthat:

19-"< =

JzQPWk

+VBS)j'2

andtheDebye_length,

(2.2)

r -11/2

LB =

faNA

with

fi=

kT

-1-1

(2.4)

VDSis drain-to-sourcevoltage, _Vbiis thebuilt-involtageofthejunctions and _VBS=0. NA

is theimportantfactorof substrate concentration orNsub foraNMOSFETdevice.

This empirical relation provides an estimate for MOSFET size reduction without

the needfor shrinking all dimensions_bythe same scalefactor. This _flexibilityallows the

choice of otherthan_strictlyscaled_geometries,"new geometries which are easierto make or which optimize other aspects ofMOSFEToperation"

[17].

The minimum channel length necessary in order to avoid short channel effects

and its dependence to the physical dimensions ofthe drain junction depth

x-, the oxide

thickness _tox, andthedepletion layerwidth ws +wd,was also observedby Zhi-HongLiu

et al. [18]. In this work, a threshold voltage model for MOSFET 's is derived using a quasi-two-dimensional approach. This model is based on the solutions ofthe

quasi-two-dimensional Poisson's equation in the depletion region. In their case the characteristic

lengthvalue is definedas,

with_{Xj, Xdep}and inum andTox inA.

They conclude that a simple _scaling rule is that the channel lengthmust be at least five

times the characteristic length . _Thus, =_-^-, which agrees with the empirical

prediction madein _1980, andemphasizestheneedforcontrol ofthe three_keyparameters

drain junctiondepth_Xj, theoxidethickness tox,andthedepletion layerwidth Xdep.

2.2.1.4 First_ScalingChallenges- Submicron Devices

The active regiondeterminesthearea where thedevices arebuilt. This is thearea

wherethetransistorper se is built. The scalingconsiderations forthe activeregionofthe

transistors must include the three important factors mentioned above, drain junction

depth_Xj, theoxidethickness tox,andthe depletion layerwidth

Xdep

2.2.1.4.1Substrate_doping

The depletion layer width _Xdep, calculated from the one dimensional

abrupt-junctionapproximationresultsinthe expression,

\2-Si-{2-<j>F)

"*.

TF'

(2.6)

dep n _q-N

SUB

which shows the inverse proportionality of the depletion width dimension with the

substrateconcentration.Accordingtoboth,theidealand empiricaltheoriesofscaling, the

value ofthe substrate_doping concentrationmustbe increased inordertoreducethevalue

ofthedepletionregion.

Historicallythe substrate

doping

device was _closely controlled _by the formation of a n-well or a p-well in the _starting

silicon substrate. The challenge ofCMOS _technology is to fabricate side _by side on the

same _chip bothNMOS and PMOS transistors. _{Thus creating} silicon regions of opposite

polarity to provide local substrates for the _{complementary} transistors [20]. These wells,

besides _beingoftheright_{polarity, also provide electricalisolationfromeach other under}

every operating condition. _They are biased with the _{supply voltage,} which ensures a

reversebias condition[21].

The first CMOS IC's employed the single-well _technique, which was used for

several yearsdue toits _simplicity [22]. Thistechnique formsan opposite _polaritywell in

the_startingsubstrate, usuallyat the_beginning oftheCMOS process. This wellis formed

byion_{implantation,} followed_bya_longdiffusion athightemperatureand aselective field

oxidation.

P-well_technologywas developed first. Beforethe_availabilityofion_{implantation,}

surfaceinversionundertheNMOS fieldcould notbe easilyeliminatedin CMOS without

the use of _{area-consuming "guard} rings". With the _capability of_controlling the p-well

doping, the boron segregation into the field oxide and the effect of fixed oxide charge,

which would lead to charge inversion and a low NMOS field _threshold, could be

compensated. _Thus, a NMOS field transistor of higher threshold was created [21].

Another reason for the use of this _technology was the better "gain matching"

between

concentration in the _p-well, and the consequent carrier _{mobility reduction,} could

compensateforthe_{lower mobility}ofholecarriers.

Theuse of an n-well was_developed as soon asion implantationbecameavailable.

This approach took advantage of the _already dominant NMOS _technology since these

devices could still be fabricated in the silicon bulk with the _only addition of PMOS

transistors in the n-well. _{NMOS devices} are _inherently faster due to the higher electron

mobility at comparable lithographic resolutions. An added advantage is the ease of the

transition toBiCMOS _technologyduetothepresence of an n-well,which can serve as an

electrically isolatedcollector.Ann-well alsoimproved_{latch-up immunity} [22].

The advantages of single well processes start to vanish as minimum feature size

decreases [21]. It becomes moredifficultto optimizeboth NMOS andPMOS transistors.

To match the characteristics of a NMOS transistor to those of a PMOS using a p-well

process,a well surface concentrationmustbeaboutfivetimeshigherthan thatofthebulk

substrate. _Thus, this requires a low doped starting substrate, which is susceptible to

punch-throughbetween thedepletion layers ofthe scaleddownsource and drainregions.

Thesolution forthis is a _deepphosphorous punch-through prevention _implant, followed

by a shallow boron threshold adjust implant. _Also, the well lateral diffusion and the

extension ofthedepletion layer in the _lightly dopedside, the siliconbulk side,constrain

the minimum _{spacing between NMOS} and PMOS devices, not _{allowing for} an increase

ondevice density.

The alternative twin-well presents an integral solution to these problems. Each

well is formed _{separately by doping} it at a higher concentration than the substrate. The

23-wells are_{symmetrically}formedandtheNMOS andPMOS devices formedand optimized

independently. On theother_hand,twin well _technologydoes notincrease devicedensity.

Even though the well _{border is located} close to its drawn position, as opposed to the

single well process where design rules or an extra mask _step where _necessary to

compensateforlateral well_diffusion, welldiffusion is still aproblem. A_longwell

drive-in isstill_necessarytodiffusethe_doping,thuslateral diffusion is stillpresent.

Adding to this problem is the requirements for high substrate concentrations.

Accordingto [8],for 1 urndevicesa_dopingconcentration of

lE16/cm3

is sufficientbut it

results intoo low of athreshold voltage. Asurface threshold adjustimplantis enough to

achieve the required threshold. On the other _hand, as the channel _doping concentration

approaches values of lE18/cm3 to prevent drain to source _{punch-through, the} resultant

threshold voltage becomes too high _[8], close to the _supply voltage. In this _case, a

retrograde _dopingprofile is needed (see figure 2.2). The thresholdvoltage is lowered to

thedesiredvaluewhile still_maintainingpunch-throughcontrol.

0. 0.3 0.6 0.9

DistanceY(microns)

Figure 2.2. Microtec Simulation - Typical Retrograde

well_doingprofile.E=500KeV, Arsenic,

Retrogradewells areformed_by

high-energy

isolation structures are _{already in place, thus}

preventing the problem of _impurity

segregation. Afterthe retrograde_implant, thermal steps arekept to a minimumin order

toretaintheoriginalimplantprofile. Rapid ThermalAnnealreactors _(RTA)have become

veryusefulfor this. This prevents _impuritydiffusion towards the surface of_{the channel,}

which wouldinterferewiththedesignedthreshold voltage[21].

Another major benefit of retrograde wells is a significant increase in device

packing density compared to twin well technology. _{Well lateral diffusion is practically}

eliminated since nohightemperature _{step is necessary} after implantation. Thisallowsfor

more _closely packed CMOS devices. The retrograde well technique is _beingused in the

most advanceddevicesand seems tobethe trendforthe_coming years.

2.2.1.4.2_LightlyDoped Drains

-High energycarriers and short-channel effects

As channel length dimensions get smaller, there is a _{reliability issue concerning}

channel hot carriers due to the high longitudinal electric fields. _Lightly doped drain

(LDD) FET structures wereintroducedto deal withthis issue [25]. This structure creates

a series resistance withinthesource anddrainterminals which_helplowerthevalue ofthe

electric fieldinthe channel, thusreducingtheenergyofthechannel carriers._{Incidentally,}

it was later shown that the LDD structures could also reduce another kind of short

channel effects: thresholdvoltage roll-off[22].

25-At the saturation value of

VDS

the channel. Figure 2.3 shows thechannel lateral electric field values forboth _long and

short channeldevicescalculatedinsimulation[21].

-0.5 0.0 _{0.5 1.0 1.5}

POSITION IN CHANNEL_(um)

Figure2.3. Lateralcomponent ofthesurface electricfieldas afunctionof channellength.

The extremely large values ofthe electric field nearthe drain junction cause hot

carrierinduced degradation in bothp- _{and n-channelsMOSFET duetoimpact ionization}

of electron-hole pairs [19]. An _electron, with _{energy in} excess of the conduction band

minimum_by more than the semiconductor _bandgap, can transfer _{its energy}to a valence

electron, thus _creating an additional conduction electron and valence hole. A positive

feedbackcondition iscreatedin which more impact ionizationsoccur. The resultanthigh

currentis detrimental and can_{easily damage}circuit components and_{it may}even leadto

Another problem with _high-energy carries occurs as these encounter a

semiconductor-dielectric interface. Thin gate oxides separate the gate from the channel.

These gate oxides have been getting thinner as channel _{dimensions have been shrinking}

in orderto maintain adequate gate control over the channel. _Ideally there should be no

flow of channel carriers intothegate dielectric since apotential barrierof3.2eVprevents

these _{from reaching} the oxide. _But, as mentioned _{previously, the} high electric fields

encountered near the drain end of a MOSFET create a certain amount carriers with

enough _energy to surmount the silicon-silicon dioxide barrier and to_jump into the gate

[26]. The number of carriers with enough _energy to reach the gate terminal can be

measured _{by monitoring} the gate current. Figure 2.4 shows such a measurement. For

fixed drain bias, the gate current peaks at a particular gate bias. The decline in gate

current beyond the maximum is due to the _decreasing channel electric field with the

increasinggate bias.

~<0

J*'

,a-i _

10.

ia-J

in-10""

io-"

V-1AV

Ve-12V

Vo=iOV

&

is-i<s ssi

24-Vo. i'V5

Figure 2.4. IGvs.VGwithVDof10V, 12Vand 14V[26].

Carrier emission into the gate oxide will also lead to charge _trapping within the

oxide. Although typical silicon _{dioxide films only trap} about one percent of the total

number ofinjectedelectrons this results ina charge accumulation within the gate _oxide,

which will affectMOSFET behavior [27]. The thresholdvoltage change ofthesedevices

isminimalduetothe_highlylocalized_trappingnearthedrainterminal[21].

It isalsoimportanttonotethatalltheparameters thatare scaled_duringMOSFET

miniaturization, (i.e. drain junction depth_x-}, theoxidethickness tox,and substratedoping

The _lightly doped drain _(LDD) FET structure was introduced to lower the drain

electric field [25]. Figure 2.5 shows the fabrication sequence ofthese structures. A light

implant is donemasked_by thegate. The implantation doseofthis LDD implant is about

two orders of magnitude less than that of the source-drain region. A conformal

depositionof silicondioxideisdoneright afterthision implantation. A_highlyanisotropic

dryetch ofthe silicon dioxide will leave a spacer_along the sidewalls ofthegate.A final

high-energyimplant isperformed andthedrainandsourceareas areformed.

/ uate ux

Poly /

/ \ *

/

\

FOX 1

[

]

N

^

n-V

\ /

l-)

FOX

Poly

n-

n-FOX

FOX

N+ n- n- N+

, FOX

Figure 2.5.Fabricationsequenceof_LightlyDoped Drains.

The LDD region provides a transition area between the channel and the

highly-doped source and drain. _Thus, theelectric field maximum is reduced since the potential

presents a more gradual transition. Figure 2.6 shows the lateral electric field component

inthechannel with and withouttheLDD structure [36].

?

2. UJ cc

!->

a

_j

id

LUUUUU

.NoLDD

ChUMNEHLMSYH; 1jw.

pxirjr.thichmesb:W>m i

dSftOOO _{ACCEPTOR CONIC: EEi-S KACC}

;:

300JOCC

!

J|

f<?0

/

y

, _\^

-o.s O.o at i,o

POS-ITIONINC^ANNei. farn]

Figure 2.6. Verticalelectricfield for LDDvs.Non-LDDtransistors.

l.S

Added advantages of LDD structures include the _capability of _generating self

alignedlow-resistancesilicidedcontacts, which willbeexplained _later,andthe reduction

oftheVtroll-off effect.

Thereduction in threshold voltage with_decreasingchannel lengthand _increasing

drain to source voltage is used as an indication of short-channel effects [18]. As

mentioned previously, due to the proximity ofthe drain to the source _terminal, the gate

potential _necessary to turn the device "on"

cause a reduction inthepotential _{energy barrier} thatopposes the _entry of electrons from

then+ sourceintothe_channel, inthecase of anNMOS device. Thisreduction(knownas

theDrain Induced Barrier _Lowering or _DIBL) makesthe turn-on easier [24]. These two

effects are known as linearVt and saturated Vt roll-off _(DIBL) respectively. Figure 2.7

shows the two Vt roll-off mechanisms that affect a NMOS. The surface potential _along

the channel is plotted for different channel lengths. While the turn-on surface potential

has been determined to _2<pF. As the channel length decreases the minimum surface

potential _along the channel increases near the _2<pF value. Also as _VDS is increased on

same size_transistors,theminimumsurface potentialinthechannelalsoincreases.

s

Surface Potential

N+

Shortchannel.DIBLeffect(Large_VDS)

Shortchannel.Linear Vtroll-off

Longchannel(SmallVDS)

ChannelPositi

N+

)Sition

N+

Figure 2.7 Surfacepotentialinthechannelfor_longandshort channeldevices.

LinearandsaturatedVtroll-off effects.

Typical Vt roll-off measurements used to characterize short channel effects of

CMOS transistors is shown in figure 2.8, this is done by plotting the effective channel

length ofNMOS transistors and their thresholdvoltage [18]. A comparison ofLDD vs.

non-LDD devices with equal channel lengths has shown that LDD structures are

beneficialand reducetheVTroll-off effect [18].

0.4

>

g 0.2

4

"o

>

o

1)

H

-0.2

--0.4

-1 1 1 1 1

_

/^

NMOSFET

\^^

1 1 1 1 1

0.2 0.4 0.6 0.6 0.8

Gatepoly-Silength_(um)

Figure 2.8. Typicalthreshold-_{voltage roll-off as afunctionof gate poly-Silength fora setdrainvoltage.}

2.2.1.4.3 Shallow junctions

-xy

In orderto maintain _long channel characteristics while _{scaling down} the size of

MOSFET _devices, a _very shallow junction of the drain terminal is necessary. The

junction depth ofthis device depends on _manyfactors, such as _{ion implant energy} and

subsequentthermal treatments.

Arsenic is currently being used to create the _{n+/p junction} on NMOSFETs.

Arsenic doesnot favor channeling because it is a_heavyatomand as such ittends notto

>0.1u\m. In another _technique, in order to obtain abrupt ultra-shallow _junctions, a

pre-amorphization ofthe silicon surface with species of opposite _{polarity has been} used _by

some researchers [12]. Ultra-shallow junctions have been obtained with

pre-amorphization _{by indium, followed} with a _low-energy arsenic implant. 50nm junctions

were created onthefabricationofthisadvanced nFET_by [12].

The problem arises in the formation of the p+/n junctions of the PMOSFETs.

Boron has_{traditionally}beenused asthe sole _{impurity doping}toformp-typeregions. _B+,

being a small and light atom would require _very small implant energies to create the

necessary shallow_{junctions, (i.e. 5-10KeV). This} can be alleviated with the use of the

BF^ion. Higher energyimplants canbe used since theB+_{ion only} acquires 22% ofthe

BF1^ energy [28]. However, the main concern is the _channeling of

B+

ion through the

Siliconcrystal. _BF+2astheimplanted speciesis also affected_bythiseffect sinceit breaks

on impact [29]. Other techniques such as implantation through a thin _{Si02 layer,}

crystallographic miss-orientationorthesurfacedamagecause_bythe fluorine ionsare not

efficientin suppressing the B+_{channeling [30]. This has been} accomplished _onlyby the

pre-amorphization oflarge atoms such as _Si+, Ge+

[30]. Shahidi andhisteamobtained a

junction depth of 60nm _{by preamorphizing} the substrate with _{Sb+[12]. A low energy}

BF2+

wasthenperformedtoobtainanabrupt shallowjunctionat adepthof60nm [12].

Once this shallow-junction structures are created_bymeans ofion_{implantation,} it

is important not to disturb this distribution _during the activation anneal. Rapid thermal

annealing has emerges as the solution to thisconcern. _{Using high-intensity}arc lamps or

laser_{sources, this}method isableto separatethe activationanddiffusionoftheimplanted

ions [28].

2.2.1.4.4 Gateoxide_integrity -tox

Thinner gate oxides are a requirement _{in scaling CMOS devices. A} thinner gate

oxide will allows a faster and more efficient transistor action as well as reduced

short-channel effects.

However, gate oxide wear-outis one ofthemost_{menacing failure} mechanisms of

MOS devices. The silicon _{dioxide insulator may break} and create a conductive path

betweenthe gate and the substrate,_rendering theCMOS device useless. It is known that

higher electric fields acrossthe _insulating gate oxide lead to _early oxide breakdown and

device failures. Figure 2.9 shows this oxide breakdown _frequency distribution as the

electric fieldacross theoxideis increased.

U z w D

w

O

<

100

80

60

40

20

0

BMODE

CMODE

A MODE

1

0 5

BREAKDOWNFIELD(MV/cm)

The earlier and almost _{immediate failures} arise from gross defects within the

oxide_{film. These failures are}

usually easilydetected,and thedevicesthathavethem, are

eliminatedfromthe_{manufacturingproduct line. Another groupof oxide samples willfail}

at_fairlyhighelectricfields of>7MV/cm and_mayfunction_{properly for many hours. This}

high field failure mechanism is known as intrinsic failure. It is well understood and

devices are designedso as not tooperate inthis region. Thethird _groupof oxide samples

is intermediateto theimmediatefailures andintrinsicpopulations._{These devices abruptly}

break at _any fields between 2-6MV/cm after _{many hours} of operation. This presents a

problem sinceCMOS miniaturizationhas resultedin mostdevices _beingoperated in this

region. For example a typical 0.75|im process _using a _supply voltage of5V employs a

gate oxidethicknessof _15nm,i.e. 3.3MV/cm [31]. Anotherprocess utilizes a_{3.3V supply}

with 12.5nmgate _oxide,2.7MV/cm [32].

This breakdown mechanismis not _fullyunderstood although subtledefects in the

oxide_integrity are presented as responsible forthisbehavior. This ispresumed since the

intrinsicpopulation assures usthatdefect-free silicondioxide shouldbeableto withstand

theseintermediateelectricfields.

Experimentally, current flow from the gate to the substrate material is observed

prior to intrinsic breakdown. This current flow through the insulator is associated to

Fowler-Nordheimtunneling. _Bythismechanism, electronsinthesubstrate _(anode)tunnel

through the _{energy barrier into} the oxide and drift to the gate _(cathode) [21]. This

tunnelingcurrentisoftheform,

I =AE exp2 f~B^

v* j

(7)

where E is the electric field and A and B are often termed constant. _Thus, the oxide

current is _{exponentially dependent}on the electric _{field. Experiments} have shown that as

the electric field is _increased, the gate current followsthisexponential relation shown in

equation _{7 up}to thepoint ofbreakdown.

The intrinsic breakdown mechanism points to a Fowler-Nordheim electron

tunneling injection into the oxide in ahighelectric _field, which leads to hole generation

by impact ionization and net hole _trapping within the oxide. _Thus, net positive charge

accumulation dueto this high-field impact_ionization, increasesthe cathode field so that

electroninjection also increases. This positivefeedbackproduces alocal current _density

thatdestroystheoxide structure [24].

Returning to the _{intermediate group} of oxide _{breakdown, understanding} this

breakdown mechanism is of outmost importance. As described previously, CMOS

miniaturization requires IC circuits to operate at field strengths of 2-7MV/cm. Sodium

contamination _{has been easily} recognized a source of oxide breakdown. The positive

sodium ions tend to migrate towards the cathode, enhancing the local electric field and

thus _increasing electron injection. This field enhancement continues until the oxide

breaks. It is alsobelieved thatoxidedefects may effectively lowerthebarrier for

Fowler-Nordheim tunnel injection of electrons into the oxide conduction band. The breakdown

mechanism is then identical to that of the intrinsic group, only shifted to lower fields

It is also important to note that thinner oxide should lead to reduced impact

ionization due simplyto the limited spatial extent ofthe oxide conductionband in which

the electrons possess enough _energy to ionize a valance electron. This indeed favors

MOS _technologyandminiaturizationand contrasts againstthe_increasingelectricfieldsat

which gate oxides are operating.

A method to avoid oxide damage over time is tooperate at lower electric fields.

Fowler-Nordheim injection has been determined to start at values of4.5MV/cm. CMOS

devices are designedandtheirparameters adjustedto operate at electricfields below this

limit. It has also been determined that to obtain a _{better quality oxide,} slow growth and

high growth temperature are desirable [33]. Finally, "clean" processing with minimal

contamination,maximum_getteringand_{high-qualitystarting}materials areall_{necessary in}

ordertoobtain goodquality,defect-freeoxide [21].

2.2.1.5 Latest Developments

The development from sub 0.25umto0.1|im gateCMOS has beenthe interestof

researchfor manygroups overthepastfew years. Severalnew _{manufacturing}techniques

have been developed in order to overcome the _{scaling difficulties. These include} the

advances described above such as retrograde _wells, LDD _structures, shallow junctions

andthin gateoxides inadditiontodual doped polygates,salicidedcontacts,nitrided gate

oxides and several novel device isolation techniques. Most ofthepapers reviewed here

present devices fabricated in research laboratories. The mass production of _these, with

someexceptions,isstill _awaitingtheintroductionoflithographic advancementsAs such,

the method used to determine the gate _{length has been} specified whenever applicable.

Finally, this section concludes with abriefreview of sub0.1urn _devices, which predicts

the transistorsofthefuture_upto the year2010.

Shahidi et al. _[12] reports in the fabrication ofCMOS devices with a minimum

channel length below 0.1p.m to demonstrate the potential of this _technology for the

manufacture of0.1 5um CMOS transistors. _Highly nonuniform channel_doping and _very

shallow drain/sourceextensions are usedinatwinwellprocess. The wells aredopedwith

Indium and _{antimony in} order to obtain _highly un-uniform _dopingprofiles with implant

peaks are placed at about lOOnm under the channel via a_high-energy implant of about

190KeV. The polysilicon gates are dual _doped, which assures surface channel _devices,

and patterned _using e-beam _lithography to obtain channel lengths bellows 0.1um. The

thin gate oxidethickness_{is only 4.5nm [12].}

Ultrashallow source-drainjunctions are obtained_by preamorphization_byindium

and _{antimony followed by} a low energy implant of As _(NMOS) and _{BF2 (PMOS)}

respectively. _{Counter-doping} with the _{preamorphizing} species results in a more abrupt

junction and better device characteristics. The NMOS junction is approximately 50nm

fromthe surface and the PMOS is _{approximately} 60nm fromthe surface. Thick spacers

are used to place the deeper _heavily doped source-drainjunctions far from the channel

and avoid short channel effects. A titanium silicide process is used over the drain and

source contactstominimize sourceanddrainsheetresistance[12].

The electrical results show gooddevice parameters and characteristics. Electrical

Barrier_Lowering which are _usually affected _by short channel _effects, show acceptable

values. The subthreshold slope is 85mV/decade and 90mV/decade for the NMOS and

PMOS devices _respectively for threshold voltages of 0.35V and -0.35V. Threshold

voltage roll-off is not observable above _Leff of 0.07um and the drain-induced barrier

loweringis only 150mVand no punch-through isobserved [12].

Y. Mii et al. _[14] worked on a high performance sub-0.lp.rn channel

NMOSFET's. Ultrathingate oxides _(3.5nm), retrograde channel _{doping profile,} shallow

source-drain junctions and low series resistances are the tools used to fabricate these

devices. A room temperature _delay of 11.3ps/stage is reported, which is the fastest

switching speed reported to date of publication for any silicon devices at room

temperature. The cutoff_frequency ofthese devices is 94GHz at 300K and 119GHz and

85K, which is accomplished with lowered capacitance values. Good subthreshold

characteristics are also reportedwith minimal short-channel effects [14].

In _1995, Yukio Okazaki et al. _[34] reports on the fabrication of a dual poly-Si

gateCMOS process_involvingseparate depositionsofin-situ doped

n+

and

p+

poly-Si for

the NMOS and PMOS transistors respectively. These transistors have effective channel

lengthsof0.2jxmand atthingateoxidesof3.5nm.Thispaper presentsaCMOSoscillator

cut-off_frequencyof5.78GHz [34].

Dual doped poly-Si, as mentioned previously, assures surface channel behavior

and better gate controllability. The gate material must be doped as

p+

type in order to

create surface channel PMOS devices. The mainconcern isboron _diffusivitytrough the

polysilicon gate andpenetration intothe thin gate oxide. A nitrogen-dopedPoly-Si layer

is used here to prevent boron penetration. _{This layer is deposited by (low} pressure

chemical vapor _{deposition) LPCVD} prior to the _deposition, also _{by LPCVD,} of the

boron-doped poly-Si layer. This (multilayer boron