Frontier Process Workshop 2007

(1)

NEMS

NEMS--based memory devices

based memory devices

ESSDERC Workshop on Emerging Nonvolatile Memories ESSDERC Workshop on Emerging Nonvolatile Memories 14 September 2007 14 September 2007

Hiroshi Mizuta

Quantum

Quantum Nanoelectronics

Nanoelectronics Research Center,

Research Center,

Tokyo Institute of Technology

School of Electronics & Computer Science, Univ. of Southampton

&

Department of Physical Electronics, Tokyo Institute of Technology

Yoshi Tsuchiya, Shunri Oda

OUTLINE

1. Introduction

1. Introduction –

– Co

Co--integration of NEMS

integration of NEMS

with silicon devices for information

processing

2. 2. Bistable

Bistable NEMS based memory devices

NEMS based memory devices

3. Other NEMS memory

4. Summary

OUTLINE

1. Introduction

1. Introduction –

– Co

Co--integration of NEMS

integration of NEMS

with silicon devices for information

processing

1000

10000

[nm]

Resonator Length Resonator Length

NEMS

MEMS

th

(

n

m)

MEMS to NEMS : miniaturization trend ?

1995

2000

2005

2010

2015

2020

1

10

100 Year

G

ate Length

[

CMOS nanotechnology era began - 1999

Charact

e

rist

ic Leng

Year

MPU High Performance MPU High Performance CMOS Gate Length CMOS Gate Length -- PrintedPrinted MPU High Performance MPU High Performance CMOS Gate Length CMOS Gate Length -- PhysicalPhysical

CMOS

Oscillation frequency of

a doubly clamped beam

Progressing high

Progressing high--speed Si based MEMS

speed Si based MEMS

A.N.Cleland and M.L.Roukes

Appl.Phys.Lett.

69,

2653 (1996).

L

= 7.7

μ

m

t

= 0.33

μ

m

h

= 0.8

μ

m

f

R

= 70.72MHz

Si beam

1996

Over 1 GHz operation possible with size reduction

2

L

t

n

∝

ω

y

p

L

: beam length

t

: beam thickness

1996

X.M.Henry Huang

et al

.,

Nature

421 ,496 (2003).

L

=1.1

μ

m

w

=120 nm

h

= 75 nm

f

R

= 1GHz

3C-SiC beam

2003

1000

10000

[nm]

NEMS

MEMS

th

(

n

m)

Fusion of Nano CMOS / SET and NEMS may lead to extended

device performance and even novel functionalities.

NEMS Nano CMOS

& SET

Electronic

Mechanical

NEMS integrated into Si nanodevices

1995

2000

2005

2010

2015

2020

1

10

100 Year

G

ate Length

[

Charact

e

rist

ic Leng

Year

More than

Moore?

Phononic

system

Beyond

CMOS?

CMOS

Phase 2:

Beyond CMOS

Novel

Functionalities

Phase 1:

More than Moore

Extended Performance

(2)

1000

10000

[nm]

th

(

n

m)

NEMS

MEMS

NEMS Nano CMOS

& SET

Electronic

Mechanical

NEMS integrated into Si nanodevices

Fusion of Nano CMOS / SET and NEMS may lead to extended

device performance and even novel functionalities.

1995

2000

2005

2010

2015

2020

1

10

100 Year

G

ate Length

[

Charact

e

rist

ic Leng

Year

More than

Moore?

CMOS

Phase 1:

More than Moore

Extended Performance

CMOS nanotechnology era began - 1999

OUTLINE

1. Introduction

1. Introduction –

– Co

Co--integration of NEMS

integration of NEMS

with silicon devices for information

processing

2. 2. Bistable

Bistable NEMS based memory devices

NEMS based memory devices

floating-gate

nc-Si dots

G

e

-

e

-

_e

-

_e

-

compressive

_strain

stable state 1

compressive

strain

Upward

bent

Mechanical bistable states

Nonvolatile NEM memory

channel

S

D

air gap

compressive

strain

compressive

strain

Downward

bent

stable state 2

z

No charge tunneling via gate oxide

z

High

High--speed write/erase operation

speed write/erase operation

z

Compatibility with conventional Si

process

Advantages

Y. Tsuchiya et al., J. Appl. Phys. 100, 094306 (2006)

Buckled SiO

2

2 beam with embedded SiNDs

beam with embedded SiNDs

•Beam

：

200 ×

20 nm

•Diameter of dots: 10 nm

•Interdot spacing: 10 nm

Young’s modulus

Poisson’s ratio

Si 190 GPa 0.27

SiO 70 GP 0 175

Si nanodot

10nm Si (111)

SiO2 70 GPa 0.175

SiO

2

matrix

-40 -30 -20 -10 0 10 20 30 40

D

isp

la

ce

m

e

n

t (

n

m

)

-2 -1 0 1 2

Applied force (μN)

Si Wafer

SiO2(Thermal)

Resist

Anisotropic and Isotropic etching

SEM i

f

b

N t

ll

d

d b

b

t b id

Test beam structure fabrication

Release of stress at Si/SiO

22

interface after undercut

2μm

SEM image of a beam

Naturally upward

Naturally upward--bent bridge

bent bridge

structure observed

Thermal

oxidation

Isotropic

etching

Bent

upward

Y. Tsuchiya et al., J. Appl. Phys. 100, 094306 (2006)

Before loading

Load on the beam using the

Load on the beam using the nano

nano--indentor

indentor

After loading

in collaboration with Y. Higo and K. Takashima of

Tokyo Institute of Technology

Loading experiment for the beam

Bent upward

Bent downward

(3)

Electrical switching of the beam

SiO2: 100nm Cr: 15nm

Va

Va = 36V

Buckled beam

V

a

= 0V

Va = 37V

Direct observation of beam mechanical bistability

Japanese mechanical bistable device 200 years ago

‘Vidro’ ‘Poppin’

An instrument with a glass lamella

-‘ A woman playing a vidro’

Utamaro Kitagawa (1753-1806)

6 8

[MPa

]

Increase by Z

03

We calculated P

S

with changing the

length L, width W, thickness T and

initial beam displacement Z

0

.

Change initial displacement

Change Thickness

SiO

2

Thickness 150nm

Mechanical properties of buckled FG

20 40 60 80 100

2 4 6

0

Initial displacement Z0 [nm]

S

w

it

c

h

ing pow

e

r P

S

[

0 50 100

0.01 0.1 1 10 100

Initial displacement Z0 [nm]

S

w

it

c

hing p

o

w

e

r P

S

[M

P

a

]

P

S

∝

p

0

Change Length

Length 4μm Length 2μm Length 1μm

Thickness 100nm

Thickness 50nm

Z

0

3 L

-4

_T

T. Nagami et al., IEEE Trans. Electron Devices 54, 1132 (2007)

2

3

4

5 2×1×0.1

μ

m (n = 1)

1 ×

0.5 ×

0.05 μ

m (n = 0.5)

500×250×25nm (n = 0.25)

g

po

w

e

r P

S

[M

P

a

]

4

1 ,

2

1 ×

Scaling law for switching power

20

40

60

80

100

1

0 Initial displacement/scaling rate Z

0

/n [nm]

Sw

itc

h

in

g

Switching power unchanged by proportional

scaling

,

T. Nagami et al., IEEE Trans. Electron Devices 54, 1132 (2007)

Readout operation of NEMS memory

OFF

state

1018

1016

1014

ti

on (c

m

-3)

16 14 12 10 8 642 0

1.8 1.6

1.4

e

ntial (V)

16 14 12 10 8 642 0

ON

state

10

1012

1010

108

106

E

lec

tr

on c

onc

ent

ra

1.2 1.0

0.8 0.6

E

lec

tr

os

ta

ti

c

pot

e

0.4

0.2

0

-14 -12 -10 -8 -6 -4-2 0 -14 -12 -10 -8 -6 -4-2 0

Potential distribution

Electron distribution

Hybrid electromechanical

Hybrid electromechanical –

– transport simulation

transport simulation

Structural mechanics analysis

(

c

∇

u

)

=

F

⋅

∇

−

F

: force

t

l ti

t i

u

: displacement

Drift-diffusion analysis

(

)

(

p p

)

SRH

SRH n n

qR

p

qD

qp

qR

n

qD

qn

−

=

∇

+

∇

−

⋅

∇

=

∇

+

∇

−

⋅

∇

ψ

μ

ψ

μ

n, p: electron, hole density

Software: COMSOL Multiphysics Parallel (FEMLAB)

3D or 2D hybrid finite element method analysis

Electrostatic force Deformation

Drift electric field

c

:

u

-

σ

translation matrix

Electrostatics analysis

(

ε

∇

ψ

)

=

ρ

⋅

∇

−

ψ

: electrostatic potential

ρ

: charge distribution

ε

: dielectric constant

Charge redistribution n, p: electron, hole density

μ: mobility

q: elementary charge D: diffusion coefficient

RSRH: SRH recombination rate

Electro-mechanical

memory operation

(4)

For reducing switching voltage

Smaller zero bias displacement

leads to lower switching voltage

P

S

∝

L

-4

T

Z

0

3

0

10

20 a

c

e

m

ent

Z

[

n

m

]

decreasing Z0

Z

0

-20

0

20

40 -20

-10

Gate voltage V

g

[V]

Be

a

m

d

is

p

la

Simple reduction of Z

0

may result in losing bistability.

Effects of cavity structures

0

10

20

30 a

c

e

m

ent

Z

[

n

m

]

bottom, side, top fixed

Completely rigid wall

-50

0

50 -30

-20

-10

Gate voltage V

g

[V]

B

eam

di

s

p

la

bottom, side fixed

bottom fixed (original)

Careful structural design of the FG as well as the outer

cavity needed.

Readout operation of NEMS memory

-10 0 10

-20 -10 0 10 20 B e am Di s p la c e m ent Z [ n m ] ① ②

①

OFF state

Electron density

[cm-3_]

1018 p-Si

1×1016cm-3

Charge sheet 8.5×10-8_C/cm2 Gate (Cr:100nm)

-10 0 10

10-9 10-8 10-7 10-6 10-5 10-4 10-3 10-2 10-1 100 101 102 103

Gate Voltage Vg [V]

D rai n Cu rr en t I d [ A /m ] ① ②

0 0 0

Gate Voltage Vg [V]

②

ON state

10 1016 1014 1012 1010 108 106 104 102

Channel is formed

Optimized Readout characteristics

30 m ] upper cavity height 40nm lower cavity height 40nm p-Si substrate Bridge deformation Z upper cavity

height 40nm

lower cavity height 40nm

p-Si substrate Bridge deformation Z

Beam & cavity structure optimization

15 10-14 10-13 10-12 10-11 10-10 10-9 10-8 10-7 10-6 10-5 10-4 D ra in c u rr e nt Id [A / μ m] Zave0 21nm 18nm 14.5nm 12nm Z0=

-40 -20 0 20 40

-30 -20 -10 0 10 20

Gate voltage Vg [V]

B e am dis p lac e m ent Z [ n m 18nm 12nm Z0= 21nm 14.5nm Br id ge deform a ti on Z [ n m]

P

S

∝

L

-4

T

Z

03 Z0=

0 10 20

100 101 102 103 104 105 106 107 108 109 0 1 2 3 4

Zero bias displacement Z0 [nm]

O N /O FF r a ti o T h re s h o ld v o lt ag e s h if t Δ Vt [V ] perpendicular model parallel model perpendicular channel parallel channel

Zero bias deformation Z0[nm] -3 -2 -1 0 1 2 3 10-15

Gate voltage Vg [V]

current

current Channel // FG

Channel FG

Fabrication of FG with

Fabrication of FG with SiNDs

SiNDs

σ

～

2 x 10

11

_cm

-2

VHF pulsed plasma process:

VHF pulsed plasma process: nc

nc--Si dot deposition

Si dot deposition

T. Ifukuet al.,Jpn. J. Appl. Phys. 36, 4031 (1997) Pulsed-H2Supply

100

Dot diameter (nm) 10

30

20

0

25 50 75

SiH4 H2 0.5 s F requen c y ( % )

Diameter < 10 nm & dispersion ±1nm

Fabrication of FG with

Fabrication of FG with SiNDs

SiNDs

Si (111)

SiO

2

TEM image of a nc-Si dot

As deposited

5nm

10nm

Substrate

SiH4 gas

H2or

Ar gas VHF (144MHz) Plasma Cell UHV Chamber To TMP PC control Orifice

(5)

Fabrication of FG with SiNDs

SOI based thermal oxide CVD grown SiO2 SiNDs (a)

(b) (c)

10nm

Upper cavity

σ

～

2 x 10

11

_cm

-2

ECR-RIE (Gas:CF4/ anisotropic)

Plasma Etching (Gas:CF4,O2/ isotropic)

ECR-RIE Plasma Etching

(d) (e)

Upper cavity

formed

Lower cavity

formed

Fabrication of FG with SiNDs

Length:

1μm

Cr:100 nm SiO 50

Beam width:1 μm

500nm

Buckled bridge with SiNDs

1μm

SiO2:50 nm

Beam thickness: 100 nm

Upper: 150 nm

Lower: 150 nm

Micro-Raman spectroscopy (

μ

RS)

Ar

+

_laser

Beam size

1 μm×1 μm

ω

0

0 ω

Δ <

σ >

0 tensile

0 Mechanical stress analysis using

Mechanical stress analysis using

μμ

RS

(

ω0

~ 520 cm

-1

₎

4 μm

1 μ

m step,

25 points

around bridge

0 ω

Δ >

σ <

_compressive

0

-1

[MPa]

434 [cm ]

σ

= −

× Δ

ω

: Stress

σ

I. De Wolf, Semicond.Sci.Technol.11(1996) 139-154.

: Raman mode frequencies

of Si in presence of stress

ω

0

ω ω ω

Δ = −

Jobin-Yvon U-1000

• 514.5 nm Ar

+

_{laser source}

• 1

μ

m spot diameter

• Resolution ~0.15 cm-1 wave number

Jobin-Yvon U-1000

• 514.5 nm Ar

+

_{laser source}

• 1

μ

m spot diameter

• Resolution ~0.15 cm-1 wave number

σ[MPa]

Mechanical stress analysis using

μμ

RS

Buckled bridge

Pad area

[MPa]

400

200

0

-200 [MPa]

400

200

0

-200

Tensile stress of about

100MPa observed around

the beam edges

Peak determined by using

Lorenzian fitting

n

cy

(GHz)

2.0 μm 0.5 μm width =

Switching speed of a simple flat FG

For a simple flat SiO

₂

beam with L < 1

μ

m, over

1GHz frequency can be obtained, but……

[2] A.N.Cleland and M.L.Roukes, APL 69, 2653 (1996). [1] X.M.Henry Huang et al.,

Nature 421,496 (2003).

Freque

n

Beam length (

μ

m)

2

L

t

n

∝

ω

0.2 0.4 0.6 0.8 1

0 12

For

c

e

P0

40 -20 0 20 40 60

a

ti

ng

ga

te d

is

p

la

cm

ent Z [

n

m

]

40 -20 0 20 40 60

a

ti

ng

ga

te d

is

p

la

cm

ent Z [

n

m

] Initial displacement 15.1nm 26.6nm 34.7nm 41.3nm

Switching speed of a buckled bistable FG

[×10-10_] time t [s]

5×10-12

0 0.5 1 1.5 2

[×10-8 ] -60

-40

Time [s]

Fl

o

a

0 0.5 1 1.5 2

[×10-8 ] -60

-40

Time [s]

Fl

o

a

Oscillation

at Z

0

= 34.7nm

Length 1μm

Width 500nm Thickness 50nm

Instantaneous

applied force

(6)

Beam damping effects on switching speed

Beam oscillation damping

after switching

( )

t

f

ku

dt

du

dt

u

d

m

2

+

ξ

+

=

2

mass damping parameter

stiffness

k

m

dK

dM

β

α

ξ

=

+

mass damping

stiffness damping

Beam length: 1

μ

m

Cell

Device

Structure

Mechanism of

PCRAM

Phase C

Nano-Crystal

Charge in FeRAM

Polarization

MRAM

MR Change Flash

Charge in

NEMS-Memory

Mechanical

A variety of nonvolatile RAM candidates

Non-volatility

Issues

Cell Size

Voltage

P/E Cycle

Speed

Program

Read

Change

1012

3 V <20 ns 100 ns

8-15F2

Program Curt. reduction Nano-dot

108

< 12 V <20 ns 10 us

4-8F2

Program Volt. reduction

1010

5 V 100 ns <50 ns

10-20F2

H2block CVD

g

1015

3 V <50 ns <50 ns

8-15F2

Program Curt reduction Floating Gate

108

< 12 V <20 ns 10 us

4-8F2

Program Volt. reduction

bistability

> 1012?

< 10V <20 ns ? < 50 ns

6-10F2

Power reduction, Shock immunity

OUTLINE

1. Introduction

1. Introduction –

– Co

Co--integration of NEMS

integration of NEMS

with silicon devices for information

processing

2. 2. Bistable

Bistable NEMS based memory devices

NEMS based memory devices

3. Other NEMS memory

Suspended

Suspended--Gate MOSFET

Gate MOSFET

OFF

p-Sub n

+

n+

Movable gate

6um

Voltage (V

tgap

(n

m

)

t

gap Pull-in

Pull-out

Pull-in

Pull-out

o tage (

n+

ON

Movable gate

N. Abelé, A. Villaret, A.Gangadharaiah, C. Gabioud, P. Ancey and A.M. Ionescu, IEDM2006