Boundary scan system design

Rochester Institute of Technology

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6-17-1996

Boundary scan system design

Craig Loomis

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Approved By:

BOUNDARY SCAN SYSTEM DESIGN

by

Craig R. Loomis

A Thesis Submitted

In

Partial Fulfillment

of the

Requirements for the Degree of

MASTER OF SCIENCE in Computer Engineering

George A. Brown, Professor and Thesis Advisor

Dr. Pratapa V. Reddy, Associate Professor

Dr. Robert E. Pearson, Associate Professor

Dr. Roy Czemikowski, Department Head

DEPARTMENT OF COMPUTER ENGINEERING

COLLEGE OF ENGINEERING

ROCHESTER INSTITUTE OF TECHNOLOGY

ROCHESTER, NEW YORK

THESIS RELEASE PERMISSION FORM

COLLEGE OF ENGINEERING

ROCHESTER INSTITUTE OF TECHNOLOGY

Title of Thesis: Boundary Scan System Design

I, Craig

R.

Loomis, hereby grant pennission to the Wallace Memorial Library of

Rochester Institute of Technology to reproduce this thesis in whole or in part. Any

reproduction will not be for commercial use or profit.

ABSTRACT

Given the _strong competition in digital designon the national and international

levels,

boundary

scan devices are_rapidly

becoming

a _necessary as opposed to aconvenient

feature on integrated circuits. This thesis serves adualpurpose.

First,

it demonstrates

how

boundary

scan devices canbe used toincrease the _testabilityof acircuit and it

presents several factors used to_quantify the cost associated with the addition of

boundary

scan _{compatibility} todigital designs. Costtradeoffs are often the most

intimidating

hurdle forengineers to cross when

deciding

if

boundary

scan_{compatibility} is worth the

effort.

Second,

itdemonstrates theuse oftheTektronix LV500 (logic _verifier) as a

general _{testing tool, using}

boundary

scan designs as examples. These examples provide

an _{understanding}ofthe function of

boundary

scancells and theJTAG/1 149. 1 standard.

The _LV500, which is used

by

studentsin the DepartmentofComputer

Engineering

and

Microelectronic

Engineering

at

RIT,

is anindispensable tool _{for making}critical_timing

measurements. It also allows a userto evaluate and _step through simple as well as more

complicateddesigns. It is my hope that this thesis and the tutorialprovided will facilitate

the use ofthe LV500 in future _testingworkperformed in RIT'scenterfor

Microelectronic and Computer

Engineering

clean roomfacilities. Upon

following

the

example circuits

described,

one shouldbecome familiarwith

boundary

scan _terminology

TableofContents

List ofFigures vii

ListofTables ix

Glossary

x

1.0 Introduction and

History

1

1.1

Testability History

1

1.1.1 ImportantCharacteristics of

Testability

2

1.1.2 Current

Testability

Issues 4

1.2 How

Testability

HasBeenImplemented 8

1.2.1 Fault Types 9

1.2.2 TwoRequirementsofFault Detection 10

1.2.3 A ClassicalExample 1 1

1.3 LimitsofClassic Example 12

1.3.1

Increasing Density

ofICs 12

1.3.2

Increasing Density

ofPCBs 13

1.3.3 Physical Interface withBed-of-Nails 14

1.4

Boundary

Scan Alternative 15

1.4.1 The Basics 16

1.4.2

Overcoming

Density

ofICs 19

1.4.3

Overcoming Density

ofPCBs andPhysical Interface 19

1.5 ProblemStatement 20

1.6 SystemConstraints 21

1.7

Terminology

22

1.7.1 JTAG Specifications 22

1.7.2 TektronixLV500 27

2.0 Functional Specifications 28

2.1 Overview ofTutorial 28

2.2 LV500

Setup

and Configuration 29

2.2.1 Menus 29

2.2.2 Testhead Installation 33

2.3 40 pin ZIF Testhead 34

3.0 Tutorial for Test Boards 36

3.1 SingleTest

Chip

36

3.1.1 BSCANJTest

Setup

36

3.1.1.1 DUT

Wiring

39

3.1.1.2 LV500

Setup

42

3.1.1.3 Pattern Test Vectors 50

3.1.2 Single

Stepping

Test 54

3.1.3 Schmoo Specification 65

3.1.3.1 InputVoltage Limits 66

3.1.3.2 Propagation

Delay

69

3.2 Single

Chip

with Combinational Logic 73

3.2.2 Design ofState Machine 73

3.2.3 BSCANJITest

Setup

84

3.2.3.1 DUT

Wiring

85

3.2.3.2 LV500

Setup

88

3.2.3.3 Pattern Test Vectors 89

3.2.4

Running

Test 90

3.2.5 Schmoo Specification Tests 99

3.2.5.1 TCKPulse Parameters 99

3.3

Boundary

Scan Circuit Design 105

3.3.1 LogicDesign atthe IClevel 105

3.3.2

Boundary

Scan Architecture Features 106

3.3.3 The Design Overview 107

3.3.4 The DesignDetails 119

3.3.4.1 DesignoftheTAP 119

3.3.4.2 Designofthe Instruction Register 125

3.3.4.3 Design ofthe BypassRegister 129

3.3.4.4 Designofthe

Boundary

Scan Register 130

3.3.4.5 Design ofthe Custom Scan Register 133

3.3.5

Summary

of

Boundary

Scan CircuitDesign 135

4.0

Summary

And Conclusion 138

4.1 DesignDetails 138

4.2 Problems Encountered and

Remaining

Limitations 141

4.3 Suggestions forFuture Enhancements 141

5.0 References 142

APPENDIX A

Listing

of

Timing

Diagrams 145

APPENDIX B Code Generation 154

B.l Unix Applications 154

B.l.l

Peg

InputCommands 154

B.1.2

Peg

Eqn Output (Eqntott Input

File)

155

B.1.3

Peg

Summary

Output File 156

B.1.4

Peg

Truth-Table Output File 156

B.l. 5 Eqntott Output File (Espresso Input

File)

157

B.1.6 Espresso Output File 158

B.2 MentorGraphics Simulation Files 159

B.2.1 QuickSim Input Files 159

B.2.2 QuickFault Input Files 165

B.2.3 QuickFault Output File 171

B.3 LV500 Input File 174

B.3.1 BSCAN I.NEWPattern File 175

B.3.2 BSCAN II.NEW Pattern File 178

APPENDIX C Discussion of

Printing

Operation 180

APPENDIXD Contacts 181

Table ofFigures

Figure 1 Average NumberofFaults

During

Product Life Cycle 5 Figure 2 Relative Costof

Repairing

aProduct

During

Life Cycle 6 Figure 3 TotalTime Requiredto Generate Test Patterns 8

Figure 4 Circuit ExampleofLogical Faults 9

Figure 5 Recent Trends in Gate-to-Pin Ratio 13

Figure 6

Boundary

Scan Cell 17

Figure 7

Boundary

Scan Path on PCB 18

Figure 8

Boundary

Scan Architecture 24

Figure 9 TAP State Diagram 25

Figure 10 LV500 Keyboard 30

Figure 11 Power

Up

Menu 32

Figure 12 Main Selection Menu 32

Figure 13 LV500 SystemConfiguration 34

Figure 14 40pin ZIF

Wiring

Diagram 35

Figure 15 Save/Restore Menu 37

Figure 16 Testhead

Wiring

Diagram 38

Figure 17 DUT

Wiring

Menu 41

Figure 18 Channel D Menu 44

Figure 19 Channel

Q

Menu 44

Figure 20 Detail ofClock Phase Signals 45

Figure 21 Template Menu bscan_stndrd 46

Figure 22 Template Menu play_templat 47

Figure 23 Pattern Menu 50

Figure 24 POWERJJP Macro Menu 51

Figure 25 RESET Macro Menu 51

Figure 26

Config

Menu 53

Figure 27 BYPASS Scan Register 56

Figure 28 Instruction Register 57

Figure 29 Placement ofSingle

Step

Commands 60

Figure 30 SAMPLE Scan Register 62

Figure 31

Setting

Bit D8 High to

Flag

Error 64

Figure 32

Replacing

mask_TDI with mask_LATCH template 64

Figure 33 Define Schmoo Menu 65

Figure 34 Input VoltageLimits 68

Figure 35

Determining

propagation time from D to

Q

70

Figure 36 Propagation

Delay

Time 72

Figure 37 Coffee Break 75

Figure 38 Gate Level Connections 79

Figure 39 Percentage ofTotal Faults 80

Figure 40 Faults perCycle 80

Figure 41 Control andTestLatches 82

Figure 42 Detail Switch Schematic 82

[image:8.612.81.543.86.725.2]

Figure 43 Coffee

Break-Wiring

Diagram 83

Figure 44 Save/Restore Menu 84

Figure 45 Breadboard

Wiring

Diagram 87

Figure 46 Template Menu for bscan_stndrd 88

Figure 47 Pattern Menu 89

Figure 48 Pattern Menu for Manual Mode

Stepping

91

Figure 49 Location ofDevice State Bits 94

Figure 50 '8373

Latching

Output in TEST Mode 94

Figure 51 Next State Bit Stream

Shifting

intothe '8373 95

Figure 52 ConclusionofBSCANJI Pattern 98

Figure 53

Boundary

Scan Cell 99

Figure 54 Definition of

Setup

and Hold Times forthe Circuit 101

Figure 55

Sweeping

the PhaseWidth and Phase

Delay

ofOB 101

Figure 56 TCKPulseLimits 103

Figure 57 Higher Resolution TCKPulse Limits 104

Figure 58 State Machine Logic for the Second Example 107

Figure 59 Gate Level Connections 109

Figure 60 PercentageofTotalFaults Ill

Figure 61 Percentage ofTotalFaultsWith Feedback Multiplexer 1 1 1

Figure 62 Gate Level Connections for Mode Select Multiplexers 1 12

Figure 63 Fault CoverageofQ0 Observation Point 113

Figure 64 FaultCoverageofQl ObservationPoint 114

Figure 65 FaultCoverageofQ2 Observation Point 115

Figure 66 Fault Coverage ofQ0and Ql Observation Point 116

Figure 67 High Level Schematic forCircuit 118

Figure 68 TAPOutput Signals 122

Figure 69 TAP Schematic 124

Figure 70 TAP Simulation 125

Figure 71 IR Register Level Schematic 127

Figure 72 IR SelectionofSAMPLEDR 127

Figure 73 IRControl Logic ₁₂₈

Figure 74 BypassRegisterControl Logic 129

Figure 75 BSC Register Level Schematic 132

Figure 76 BSR Scan Path 132

Figure 77 Custom Register Level Schematic 134

Figure 78 Custom RegisterControl Logic 134

Figure 79 Schematic for Logic of

Boundary

_{Scan Component} 137

Figure 80

BSCANJ

e.g. 1 145

Figure 81

BSCANJ

e.g. 2

Timing

Diagram 146

Figure 82 BSCAN_I e.g. 2

Timing

Diagram

(cont.)

147

Figure 83 BSCANJI

Timing

Diagram 148

Figure 84 BSCANJI

Timing

Diagram

(cont.)

149

Table ofTables

Table 1 Logical

Mapping

ofDUT ₄₀

Table 2 Description of_{Phase Times for Figure} 21 46

Table 3 Description of_{Phase Times for Figure 22 47}

Table 4 State Assignment Table 74

Table 5 State Transition Table 76

Table 6 DUT

Wiring

Table 86

Table 7 TAP Output Signals 121

Table 8

Mapping

ofIR to its Address Instruction 126

Table 9 NumberofLogic Cells Required forImplementation 139

Table 10

BSCANJ

Timing

Table e.g. 1 151

Table 1 1

BSCANJ

Timing

Table e.g. 2 152

Table 12 BSCANJI

Timing

Table 153

Glossary

ASIC Application Specific Integrated Circuit. A type ofIC device that performs

specific pre-programmed functions suchas_controllingelectronicinstrument

panels andthe _sensing offluid levels.

BIST Build In Self Test. Logic included in a design thatperforms a self-contained

self-testofthe device.

BSR

Boundary

Scan Register. A set of storage cellsthat use multiplexerstocontrol

the flow ofdatainto and out of an I/O pin. The I/Ocan bedirected from the

normal path to a serial shift register of similarBSRs.

DFT _{Design For Testability. A design methodology} that channels_{early design} efforts

toensurethat afinal design product is testable.

DIP Dual In-line Package. A rectangular plastic

housing

for ICand othercomponents

that isused on PCBs.

DUT Device Under Test. Circuit that is

being

tested forfaults.

IC Integrated Circuit, also called a

"chip."

An _{integrated array}ofactive and passive

elements with a single semiconductor substrate.

LFSR Linear Feedback Shift Register. A shiftregister with some ofitsoutputs

exclusively ORED togethertoforma feedbackmechanismwhich creates a

Pseudo-Random PatternGenerator.

LSSD Level Sensitive Scan Design. _{A design methodology} thatensuresrace-free

operation. Itis based upon _memoryelements thatare independent of signal

MCM

Multi-Chip

Module. A circuitformed

by

_{placing ICs}on _top of each other to

increase circuit

density

and decreasesignal tracelength.

PCB PrintedCircuitBoard. The"platform"forelectronic circuit constructionthat

contains all theconnectionsbetween thecomponentsprinted on theboard.

PRPG Pseudo-Random Pattern Generator. ALFSR configured to generatedatatodrive

a logic block. It isoften used in conjunction withaPSA

during

testing.

PSA Parallel Signature Analyzer. A LFSRused to compress the outputsofa logic

blockintoa testregister such thata unique value isobtained aftera testisrun.

SLSI Super Large Scale IC. An IC with 50,000 to 100,000transistors.

SMT Surface Mount Technology. A methodof_{manufacturing}PCBs in which chips

are fixed

directly

ontothe surface oftheboard instead of

being

solderedinto pre drilled holes.

ULSI Ultra Large ScaleIC. An ICwith over 100,000 transistors.

VLSI

Very

Large Scale IC. An IC with5,000 to 50,000transistors. Itis also used with

reference to an IC design with _any large number oftransistors.

1.0

Introduction

and

History

Boundary

scandevices can be usedto

internally

test the

integrity

of an IC (Integrated Circuit)1

or MCM

(Multi-Chip

Module)2 thatisembedded in a system'sdesign.

They

can also be used to testthe externalconnections betweencomponents3

that are onthe

same PCB (Printed Circuit

Board)

even ifsome ofthe components are not

boundary

scannable themselves. The

key

behindtheir_utility is twofold.

First,

isthe novel idea of

using an IC built with _serially connectedI/O (Inputand

Output)

pins that allowtest access.

Second,

is the use of anIEEE standardto ensure_{compatibility among} different vendors. TheIEEE 1 149.1 Standard Test Access Port andBoundary-Scan Architecture

document has been underdevelopment since themid 1980'swith its formal acceptance in

1990.4 _This

thesis provides a brief

history

of_testability and recenttrends in _technology

that haveresulted in the new

boundary

scan standard. Italsodiscusses how students in

the Computer

Engineering

and Microelectronic

Engineering

Departmentsat RITcan benefit

by designing

circuits and ICs thatincorporate the

boundary

scan standard.

1.1

Testability

History

It has been said that_{testability has} been around eversince the cave man whoinvented the

club, knocked himselfoutwhile _trying toprove itworked.5 _{This first}

section gives a definition of_{testability followed}

by

recent

history

_showingwhy

boundary

scan devices

1.1.1

Important Characteristics

of

Testability

A circuit's _testability is

becoming

a criticalrather than convenient feature for non-trivial

digital systemsdesigned today. Before

discussing

currenttrends in testability, it is first important to understand what_testability is. Onedefinition _states,

"Testability

is a

characteristic ofadesign which allowsthe status (operableor

inoperable)

ofa system or

any ofits subsystemsto be confidently determinedin a_timely fashion."6 The definition is good as it contains twoofthe_primary ideasof_{testability; namely} the timeittakes to

perform a testandtheinformationthat the test provides.

Examining

these two ideas will

provide insight to the core of_{many testability} issues. Let's start with the time ittakes to

performa test. Thistime is dependentupon the size ofthe design and the tools available

at the

facility

in whichthe tests are performed. In otherwords, it dependsupon how easy

it is to exercise adesign toobtain a system of measured responses which ascertain

whetheritis

behaving

properly.7

Thus,

by increasing

the access totest

features,

testability is increased. This is dependentupon the level and_complexity ofthe system

being

tested. The systemlevel will _{vary fromtesting}ofVLSI

(Very

Large Scale

Integrated)

circuit wafers to _testing a PCB (Printed Circuit Board). Thesystem

complexity will _{vary in} numbersofcomponentsor gates andin the degreeofdata abstraction. Forexample, tests

being

performed _{may vary}from measuring a single

voltage with a _probingstation to _measuring a matrix ofdigital voltageswith a logic

verifier.

The second aspect oftestability, the information that the tests provide, is driven

by

both

the level ofthedesign and thediagnostic detail requiredfor its evaluation. Asthe design

level varies from IC design to PCB

design,

the amountofinformation available changes

information also increases withthe design level. Anotherreason is that the systems

complexity increases from monitoring voltage levelsto_monitoring digitalabstractions

representing system states and controldata. There is much_{responsibility} given to the

designerto make use ofthatinformation asbest _they seefit. Attimes, it is sufficient to

acknowledge whetheratest haspassed or_not; whilein other instances a system_may

have toprovide detailed diagnostic feedbackon its actionsin ordertoisolate possible

future faults. For_example, in order todetectand correct_{early design} errorsthe cause of

the errormust first be found through testing.

Hence,

_testing is not _only performed to

detectfaults but also to determine the cause of aknownfault or misbehaviorin the

system.

Again,

depending

upon the levelof

design,

this _may target_{anything from} the

detection of a misaligned maskthat causes a shortbetween two_polysilicon lines on a

VLSI _wafer, totheclock signal that hasan intermittent errorin a PCB. The important

thingto rememberisthat the value ofacircuit's _testabilitylies not_{only in how easy} it is

1.1.2

Current

Testability

Issues

Now that the characteristics thatmake _up

testability

havebeen

discussed,

let's focus on

businessconcerns andthepotential impact thata design's testability hason its life cycle.

Threeofthe mainissues in adesign are the_reliability, costand time to market. The

reliability ofadesign relates to howit functions both after_{manufacturing} andwhen it is

being

used

by

a customer. The design should operate as specifiedforthe longesttime

possible. For some

designs, (e.g.,

medical _{equipment) reliability, relating}tothe _safety

and well

being

ofits_users, is themost critical issue. In other

designs,

thedesire to

minimize failures and maximize product reputationdrivesthe increasesofproduct

reliability. Cost is anotherissue from acustomer's standpoint. It should _stay within initial budget constraintsforthe lifeofthe product, notjustwhile

being

manufactured.

The final issue is the time tomarket fortheproduct.

Having

a product available when a

customer needs ordesires

it,

is often referred to as themarket window. The first

company to _ship products

during

this time will maintain ahigh market share.

Again,

this

helps to determine the overall cost oftheproduct. These threeissues are_verymuch

related with each

being

intimately

linked to testability.

Reliability

may show the strongest link to_testability since it increases proportional to

increased testing.

Simply

stated, the more aspects ofa system _tested, the fewerpotential

faults reach thecustomer. Onelink between design _reliabilityandincreased _testability

relates to component

failure,

as shown in Figure 1. The average_reliability of a product is bounded

by

two stages ofincreasedcomponent _{failure. The} second _stage, shown on the

right halfofthe Figure 1, represents"old

age."

This canbe theresultof metal migration,

can occur. Forthisreasonit is especially importanttorun adesign through itstest stages

during

a "burn in"periodpriortocustomer release.

Infant_Mortality

OldAge

TypicalCurve

AgeofDesign

Figure 1 AverageNumberofFaults

During

ProductLife Cycle. For

a typical_product, the averagenumber_offaultsis bounded

by

infant

moralityand old age.

As forthe _{relationship between} overallproduct costand _testability, the cost _typically

decreases withincreasedproducttestability. Inparticular,the costof

fixing

a

faulty

product is much lowerwhen thefault iscaught _{early in} the product life cycle. Figure 2

provides a graph

describing

the"Rule of 10's"

where thecostof

detecting

and_repairing a

faultincreases tenfold at each _progressing stage oftheproduct's lifecycle. As an

example, assumethata misaligned mask has causeda trace tocreatea short circuit

between twooutput signals. In

discovering

this circuitflaw before packaging _{the wafer,}

the cost would encompass the_processing and replacement ofthe misaligned wafers. If

cost_may be 1,000 fold tocorrect it. This drastic costincreaseincludespackaging,

shipping and installation of each systemthat thefaultresided

in,

plus the cost of on-site modification and trouble _shooting

by

field engineers.

SoftwarePrototype Hardware Prototype ClinicalEvaluation Field Operation

TypicalCurve

StateofDesign

Figure 2 Relative Costof

Repairing

aProduct

During

_{Life Cycle}

Ateach progressivestage, the relative cost _ofrepairing a product

The remaining

issue,

time, also relates tocostbecause ofthe time incurred

by

engineering and _{marketing departments}

during

productdevelopment.

However,

more specific to _testability is the time spentin

developing

the test hardware and software.

Assuredly

there willbe some finite _time, but this timecan beminimized

by

_considering

and

implementing

_testability

during

the initial design stages.8 _In

recent

history,

testability hastypically been implemented asan afterthought. This is represented

by

the

solid line ofFigure

3,

which corresponds to a _stepfunction at each stage of product

development. Each stage ofthedesignrequiresthe generation of new testvectors. For

example,iffinal product _testingis notthoughtof

during

the initial design _stages, simple

macrosare written to test

during

the first software prototype . This is followed

by

the

generation of new test vectors atthe firsthardware prototype, with yet another set

generatedforfield service engineers to test thefinal product at a customer's location. In

all, four separate sets oftest vectors _{may be} generated. The desire of

designing

for

testability7

(DFT)

is to implement the generation oftestvectors and special test

structures atthe earliest stages ofthe design. The dashed line ofFigure 3 represents the

optimal time required togenerate testvectors. This is where most ofthe test vectors are

designedat the

beginning

stages and usedthroughoutthe product's life; thus

decreasing

the total time devoted to the generation oftestpatterns. In summary, increased testability

should increase the_reliability while

decreasing

productlife cycle costs

by

_catchingfaults

at earlierdesign stages. The totaltime devotedto _testing should alsodecrease

by

incorporating

testability features intothe_earlyproductdesign stagesrather than ad hoc

Software Prototype

Hardware Prototype

Clinical Evaluation

J Field Operation

Typical Time

Optimal Time

>

State ofDesign

Figure 3 Total Time Requiredto Generate TestPatterns. The

amount_oftimespent on _testingcan beappliedto laterstages, thus

optimizing the total timespent on test.

1.2

How

Testability

Has

Been

Implemented

The definition of_testability and its impactson market needs has been presented. How

then is_testability implemented? The next section examinesthe implementationof

1.2.1

Fault Types

When a testperformedon adigital design

fails,

the source is alwaysofaphysical nature.

Often thesephysical faults aremappedinto logical faults forclassification and toreduce

theircomplexity. Twotypical examples ofhowcommon physical faults map intothe

logical domain are shown in Figure 4. The structuralfaultofashort circuit between two

linesoftrace_may drive anode toa given voltage level. For

instance,

ifthe short occurs

between VCC and a _node, VCC drives the signal high andit is labeled alogical

"stuck-at-one"

(SA1) fault. If, onthe other

hand,

GND drives the_node, then it is labeleda

logical "stuck-at-zero"

(SAO) fault. Ifthefault is due to an open circuit ratherthen a

short_circuit, power voltages_may still drive theresultant _nodes,or_{they may become} a

function ofthe connected signals. In either_case, the resultof_{using logical} mappings to

classify faults greatly reducesthe _complexity ofthe _remainingfaultequations. Test

equations are difficultto determine forall buttrivial designs because IC_packaging hides

most nodes ofinterest. This leadsto the question ofhow the

faulty

internal nodesof an

IC are

indirectly

monitored throughexternal pins.

o

NODE 2 (short toVCC)

LKr-^.^^

OUT=/A+ AB

B

NODE 1 (open circuit)

Figure 4 Circuit Example ofLogical Faults. Physicalstuck-at-faults

1.2.2

Two Requirements

of

Fault

Detection

Two important conceptsof_testability are thepropertiesof_{controllability} and

observability. Inorder to isolate an internalnodein a

design,

the node must have both of

theseproperties at the same time.

Specifically,

there must exist a set oftestvectors that

when applied to the _{primary inputs}

(e.g.,

IC pins, PCB test_pins) will isolate all the

possible faults

(controllable)

forthatnode.9

Thelogic states oftheinternal node mustbe

able to propagate to a visibleoutput(observable). Ifeitherofthesepropertiesdo not

exist for agiven

fault,

then thefault is not detectable. Forexample, to testnode one

(referring

toFigure

4)

fora SAO_{fault, apply} the vector

A=l,

B=l. Iftheoutput is

0,

and

single stuck-at-faultsare _assumed,then node one is SAO.

Similarly,

totestnode one for

a SA1 faultthevector

A=0,

B=l can beapplied. Iftheoutput is

1,

then node one is SA1.

Because nodeone is controllablefrom inputs A and B and observable at the outputnode

forthe SAO and SA1

faults,

it is

fully

testable. One the other

hand,

nodetwo can notbe

tested fora SA1 fault. In orderto do so, the vector_A=0, B=0is

desired,

butthe output

for this is the same as the output for_A=0, B=l _(i.e., the stuck-at-faultcase). Although

the fault is controllable, it is not _observable, and hence nottestable. It is importantto

note thatwhile high numbersfor controllabilityand _{observability} data sets are

desirable,

it is the intersection ofthe two sets thatprovides insight asto adesign's testability.10

This intersection is dependent upon system

design,

and as the previous circuit _{(Figure 4)}

shows, it is not hard to design a circuitthatis difficult to test.

1.2.3

A

Classical Example

Aclassic example ofthe implementation of

testability

over thepastdecade uses a

bed-of-nails approach. The

"bed"

consistsof a matrix ofprobes that applies and receives

voltage signals froma DUT (Device UnderTest).

By

_abuttingthe bed-of-nails against a

PCB and _applying a set of parallel test_{vectors, the} board'sresponse isrecordedand

compared to the desiredoutput. Theprobes ofthe bedcontact eitherICcomponent pins

ortest-points embedded intothe board layers asdesigned toincrease its testability. This

approach has beenfueled

by

through hole _technologycomponents with typical pin

spacingon 100 mil centers11

andhas performed well in

detecting

faults. One significant

feature is the _ability todiagnose multiple faults withone pass ofthe overthe testhead.12

It is also able todetect shorts before

initially

_{powering up} the

board,

_preventing the

potentially catastrophic damage due to shortsbetween power and ground. Another

benefit is the _ability to test and detect analogrelated faultsofhybrid PCBs. Allofthese

benefits are _greatly enhanced through the use software tailored to _generating testvectors,

storingthe DUT's responses to test headpasses, and._analyzing theresultsforpossible

1.3

Limits

of

Classic Example

The bed-of-nails approachhas provided a great serviceto test-engineers in thepast.

With the

increasing

_complexityofICs and

increasing

PCB density, bed-of-nails _testing

on currentPCBs _{is fast approaching}obsolescence. An alternative approach _usingthe I/O

boundary

ofICsto shiftin testvectors througha standard testbus (IEEE 1149.

1)

is

suggested.

1.3.1

Increasing Density

of

ICs

Among

the

limiting

factors ofthe _{bed-of-nails methodology}is the ever

increasing density

ofintegratedcircuits.

Currently,

sub one micron technologies are _producingcircuits with

densities _soaringabove the classic VLSI definitionof5,000 to 50,000transistors and

requiring new definitionsofSuper Large ScaleIntegration

(SLSI)

50,000-100,000

transistors andUltra Large Scale Integration

(ULSI)

forgreaterthan 100,000 transistors.

Pointin fact, one recentdesign of a microprocessorcontainsover 3 million transistors!

]-The

difficulty

with thisincreased _{IC complexity}is the sheer number ofinternal nodes

thatrequire _testability access coupled with the _growing gate to pin ratio (Figure 5).

Becausethe growth in the numberof gates has notbeen paralleled with a growth in IC

pins, internal circuit nodeshave been even moredifficult to observe and control from the

outside. If theissue of

increasing

_complexity ofVLSI circuitsdoes notlimit bed-of-nails

access from external nodes,itwill _certainly make _testingmore _costly to

develop

Gate

to

Pin

Ratio

/N

Trend

Recent Past

Present

Future Trends

Time

Figure 5 Recent Trends in Gate-to-Pin Ratio. The recenttrendin

gate-to-pin-count ratio willcontinue in thefuture. This is one challenge

facedwhen _testing digital circuits.

1.3.2

Increasing Density

of

PCBs

Along

with the growth in ICcomplexity, PCBs have also been subjectto increased

complexity. Therecent surge in PCB

density

has fueled the emergence of Surface

Mount

Technology

(SMT) components, MCM and multi-layeredboards.

Unfortunately

formost bed-of-nails _testing stations, each _{technology has introduced} a new setof

challenges.

First,

most bed-of-nailstesters were built with probes suited for 100 mil DIP

(Dual In-line Package) centers, not 25 and 50 mil SMTcenters.5*1*

The use ofSMT has

decreased thedegree towhich aprobe can isolate a signal.

Adding

to this

difficulty

is

stacking twobed-of-nails testers back to back. Although this is

being

done, it is the

manifestation of anengineer's nightmare. Use ofMCMsthat limit tracelines between

components

by

"piggy-backing"

ICchips also limit the _{board's testability} ofthese

components whenperformed throughexternalnodes alone. Multi-layered boards have

added the _ability to create a network ofsignals as neverbefore possible. Thisis at the

expense of_{adding many layers} ofsignals hidden fromthe tester's probes. The

technologydriven increase in PCB densities has increasedthecost and time associated

withthe _testingofsuch devices yet even higher.

1.3.3

Physical Interface

with

Bed-of-Nails

Another

issue,

one that relatesto the smaller IC pin _spacing with SMT_components, is

the IC pin to bed-of-nails interface. Because ofthe decrease in pin _size, there is an

increased probability of misregistration ofthe bed-of-nails interface. The misregistration

would invalidate the test results, while_creating the potential of

damaging

the PCB exists

by driving

output pinsto an undesired state.5

There isalso the chance of_shorting two

pins togetherwith probesfrom the bed-of-nails thatwould again invalidate testresults. In

summary, the

increasing density

ofICs and PCBs have caused the costof_testability with

a bed-of-nails _testing approach to rise.

1.4

Boundary

Scan Alternative

While _trying to maintainthe costofassociated with increased testability, the_philosophy

of

designing

fortestbecame prominentin the late 1980's. Themain focus ofDFT has

been to incorporate_testability in theearliestofdesign _stages, thus _minimizing itsoverall

cost. In

doing

so, a balance is soughtbetween thecostof

implementing

_testability and

the cost savings thatit brings. This fosteredthe creation of several programs such as

SCOAP (Sandia

Controllability/Observability

Analysis Program)14, COMET

(Controllability

and

Observability

Measure forTest)9 _{andPREDICT (Probabilistic}

Estimation ofDigitalCircuitTestability)15

toattempt to_{quantify testability in} terms of

the _{DUT's observability} and _{controllability} characteristics. The problem_generally

associated with these programs is that it is difficultto decide whatdesign modifications

are _necessary tomaintain _testability while _minimizing itscost. Several attempts at

increasing

testability have been made. Most have been ad_hoc,

depending

upon the

designer. Some examples include selective insertionoftest _{points, partitioning larger}

circuitsinto smaller blocks and _usingredundant logic. Although the methods work to a

degree, there aretradeoffs intrinsic toeach choice and the major

difficulty

of

incompatibility

amongvendors. In _1985, the JTAG (JointTest Action

Group)

gathered

togetherto discuss the limitsofcurrent_testing strategies and

develop

a common platform

to build from. Theirwork resulted in a standard based upon the use of

boundary

scan

1.4.1

The Basics

The essential

boundary

scan cell is shownin Figure 6. Each cell contains aclocked

register controlledthrough an inputmultiplexerand observed through an output

multiplexer. Because ofthis clocking, the

boundary

scan cellis oftencalled a

boundary

scan register (BSR). Inputdataenters fromeither thenormal input signal ortheTest

Data Input _(TDI) signaland then output dataexits from eitherthe normal outputsignal or

the Test Data Out

(TDO)

signal, as controlled

by

theirrespective multiplexers. The placement of scan cells _along the"boundary" ratherthan at each _controllingor controlled

node is whatdistinguishes

boundary

scannable systems from full scan systems. Although the JTAG committee chose a novel

idea,

it was not new. What was new, was the

suggestion

by

the committeeto use

boundary

scan cells asthe cornerstone of a_testability bus standard.16'17

Tfi

(Test Data Out tonext _cell)

NDlCI> (Normal Data In)

TDlO

(Test Data In

from previouscell)

NDO

O

(Normal Data

Out)

G

0

ShiftDR ClockDR

0

ModeSelect

Figure 6

Boundary

Scan Cell. The basicI/O cell usedto_serially

shift test and normal datainto and out _ofthe register.

By

linking

the functional inputand output pins of an IC together, a serial shift registeris

formed.

Shifting

of serial data intoand out ofthe DUT occursthrough a pair ofI/O pins.

This is analogous to _applying and _monitoring voltages through probes physical

contacting the ICspins.

Extending

this principle froma single IC to several on a PCB

results in increased testability through atest bus. This busconnects

boundary

scannable

ICs in a serialdatapath as shown in Figure 7. The added _testability is not without

penalty. ExtraIC pins and PCB signals are now dedicated to_test, and additional silicon

isrequired aswell. The extra silicon area or"real

estate"

is proportional tothe total

number ofICpins plus the extradesired _testingfunctions. Thisthesis will present

severalfactors used to _quantify the cost associated with _adding

boundary

scan

compatibilityto digital designs. Alsopresented will be severalexampledesigns _using

is used in some oftheexamples as it is oneofthefirst ICs manufacturedto the IEEE

1 149.1

boundary

scan specifications.4

The specification forthe latch is in Appendix E.

Some

boundary

scannable circuits offer powerful testfeatures thatare also explored.

Moreoversince the design oftest

functionality

is on _silicon, itcan be transparentto the

normal circuit operation.

TDI -* TDO-*

\

\

Printed Circuit Board

I/O Signal

Key

>- Scan Path

Figure 7

Boundary

Scan Path on PCB. This extends the

boundary

1.4.2

Overcoming Density

of

ICs

The

boundary

scan architecture's addressto the issue of

increasing

circuit

density

occurs

on two

fronts,

silicondesign andflexibility. The use of silicon allows_testing features to

grow as the _technology grows. The JTAG/IEEE 1 149.1 specifications alsoleave room

forthat growth. For _example,the current standard specifiesthat the

boundary

mustbe

scannable, butto increase _testability severalfunctions can be added to the scan path. The

use oftest methodologies such asBIST (Built In Self

Test),

PRPG (Pseudo-Random

Pattern

Generator),

and PSA (Parallel Signature

Analyzer)

can all be used toenhance

testability. These methodologies can contribute to the _testing of an IC

by

either

generatingrandom inputvectors or_compressing output vectors intoone unique

"signature."

The design ofthese test structuresis concurrent and transparent to the

normal operation ofthe ICor PCB

being

designed. Oneexcellent example of such a test

structure is the use ofBIST19 that initiates from a theJTAG/1 149.1 testbus and takes

place within the

boundary

scan architecture. ABIST is an extension ofthe DFT

philosophy where _testing

functionality

is built into the design itself. The test_typically

consists of afeedback systemthat generates testvectors and a similar systemthat collects

the resultsfrom the vectors. Although a BISTruns

independently

of

boundary

scan tests,

the JTAG/1 149.1 specifications can provide alink into the

initializing

and_running ofit.

1.4.3

Overcoming Density

of

PCBs

and

Physical

Interface

Because

boundary

scan is developed within the

IC,

it is independent ofthe _shrinkingpin

effects that have plagued bed-of-nails approaches. The use ofSMT and MCM

components does not degrade the _{testing ability} nordoes it increase the cost of_testing

"silicon nail"12

is applied to

boundary

scan devices thatcan escape theuse ofa physical

probe.

Similarly,

_placingcomponentsoneither sideofthePCB or_using multi-layered

boards makes no negative impact on

testability

of

boundary

scan devices since the interconnectsof

boundary

scan devices are _testable, and the

boundary

scan path can link

together ICs on the PCB.20 Although powermustnow be appliedtoa

DUT,

thephysical

interface between the DUTand the testeris limited to the testpins. The limit minimizes

thephysical interface problems and _usually makes them negligible.

1.5

Problem

Statement

Thisthesis serves adual purpose. First, it facilitates theexploration of

boundary

scan devices with tools that are available atthe facilitiesin the center for Microelectronicand Computer

Engineering

atRIT.

Secondly

it allowsone to gain

familiarity

with

Tektronix's powerful _{testing tool,} the LV500,_{currently located in} the Microelectronic

Engineering

test facility.

This thesis accomplishes both ofthese goals

by incorporating

the LV500 as a general test

tool in the _study of example

boundary

scan digital designs. Three example circuits are

used to provide a better_{understanding} ofthe function of

boundary

scan cells and the

JTAG/1 149.1 standard. The firstexample _{circuit, consisting} of asingle TI '8373,

explores the BYPASS and SAMPLEoperations _using theLV500. This example also shows that

boundary

scan operations run transparentto normal circuitoperations. The

secondexample, which has a state machine designed with aTI

'8373,

shows the value of

boundary

scanin

debugging

the combinational logic. The final example steps through

the design ofa

boundary

scannable statemachine. This _example, and thediscussion that

follows

it,

provide methods of

determining

the cost ofadditional

boundary

scan

testability. The costtradeoffs areoften themost

intimidating

hurdle for engineersto

crosswhen

deciding

if

boundary

scan_{compatibility is} worth theeffort. In _choosingto

explore both

boundary

scan and the

LV500,

_{my hope is}to be straight forward with the

most current issues and methodologies.

1.6

System Constraints

The LV500 is used _primarily in

industry

forASIC (Application Specific

IC)

verification.

It hasthe _capabilityof_generatingand _analyzing testvectorsfor upto 256channels at

speeds_up to 50 MHz. It can also monitorandplottheresults of twodimensional

parametermodifications. It is importantto note that thechoice oftheLV500 was based

upon its _{availability in RIT's} test lab and its raw _capability tocomplete the _testing that

was required. The use ofthe LV500 in this thesis is limitedto the generation oftest

vectors forsimpledigital logic systems and the generation of

boundary

scan _controlling

logic for _testing that digital system. Notintended _solely as a

boundary

scan _tester, the

LV500 sends out test vectors thatare

boundary

scan compatible. As itspowergoesfar

beyond what this thesis has usedit

for,

it is an excellent tool tobecome familiar with and

a valuable assetto the repertoire of_testing tools in RIT's laboratory. Thetutorial circuits

ofthis lab provide are also a _stepping stone in the _exploring the fullpotential ofthe

LV500.

The choice of_{using TI} components wasmade because oftheir

boundary

scan _capability

and their_strong presence in this market niche. The _components, used in the tutorial

circuits provided with this thesis, are also a_stepping stone in _exploring

boundary

scannable systems. The enclosed schematics are intended forthetest-board maintenance

1.7

Terminology

There may be many new terms andideaspresented to thereaderofthis thesis. The

following

sections provide additional detail to the JTAG/IEEE 1149.1 specifications and

theTektronix's LV500 digital tester. _{A glossary} ofterms usedis found at the frontofthe

thesis text_proceeding the firstchapter.

1.7.1

JTAG Specification

In 1985 Phillips initiated the European Test Action

Group

_(ETAG) topromote a_testing

standardfor ICs. The _group expanded intothe Joint Test Action

Group

(JTAG)

when

non-European companies such as Texas Instruments and Motorolaparticipated. At the

same timetheIEEE was

forming

its own proposal fora test bus standard. The two

organizations collaborated and formed theIEEE PI 149.1 proposal thatwas

formally

accepted in

February

of 1990.

Officially

called the IEEE 1 149.1 _standard, itis often

referred to as theJTAG standard because of theJoint Test ActionGroup's involvement.

The goal ofthe specificationsis to allow

diversity

while_{maintaining compatibility} with

otherdevices. The IEEE 1 149.1 standard specifies the physical structure ofthe testbus

and how it can be interconnected to a chip. It alsodescribestheprotocol associated with

the test bus. The fourmain test signals associated with the bus are:

TDI (TestData

In)

Allowsthe inputofdata and_{testing instructions for}the

IC.

TDO (Test Data

Out)

Allows thedataand/or instructionsto be shifted outof

the IC.

TMS (TestMode

Select)

Controls thecurrent state oftheTAP (Test Access Port). The TAP is the state machine behind the operationofthe _testing

functions.

TCK (Test

Clock)

Clocks the inputto the

boundary

scan device in on the

rising edge ofTCK and resultantdata outon the

falling

edge.

These signals are used on the

boundary

scan architecture^!

ofFigure 8. The TCK and

TMS signals are used

directly

to drive the _TAP, which in turn controls the Instruction Register (IR), Data Register

(DR)

and various multiplexers forthe I/O testdata. The IR data may either be shifted outthrough TDO or used as an address fora DRcommand.

The figure shows a test input (TDI) entering either the IR orthe DR and _shifting through

the BSRand device logic (LOGIC). The datathen travels out ofthe device throughthe

normal output pins orthrough TDO. Note that all the _{testing circuitry is}in parallel with the normaldevice circuitry, which allows the two functions to perform without

NDI I >

(Normal

Data In)

TDI

D

(Test Data In

TCK TMS

TDO

feSR

_{CHIP LOGIC}

TDI

TAP

DR

*

1

IR

TDI

BSR

TDO

-CZ>NDO

(Normal Data

Out)

4f

CZ>TDO

(Test Data _Out)

Figure 8

Boundary

Scan _{Architecture. This} isa high level diagram

ofthe

boundary

scan logicusedin

designing

a

boundary

scan device.

Figure9 containsthe TAP statediagram thatcontrols themode ofthe

boundary

scan

device. Operation includesthe

loading

of aninstruction into theIR on theright hand

side ofthe state machine and the _shifting ofdata intothe DRon theleft hand side.

TMS=1

Q

Test-Logic-_Reset TMS=0

Ttms=o

cr

TMS=1 Select-DR-Scan

!TMS=0

!_

TMS=1 Select-IR-Scan TMS=1 Capture-DR TMS=1 |tms=o TMS=1 TMS=0 Shitt-DR |TMS=1

D

Exit1-DR |TMS=0 |tms=o

Capture-_{1 R}

TMS=1 Pause-DR TMS=0 |TMS=1 TMS=0

D

Exit2-DR |TMS=1 Update-_DR TMS=1

i

"Fms=o

TMS=1 TMS=0 Shift-IR |tms=i

D

ExitMR |TMS=0 Pause-IR TMS=0

i

TMS=0

D

MS=1 Exit2-IR |TMS=1

Update-_{1 R}

TMS=1

1

TMS=0

The IEEE 1149.1 specificationslistthe functions that standard

boundary

scandevices

must be capable of_performing, as well as functions defined as extended. The

boundary

scannableTI '8373 chip contains someofthese extended or

"suggested"

JTAG

specifications.

Specifically,

the _{'8373 implements} a PRPG thatprovidestest vectors for

application to the DUTand aPSA tocompress theresultant test data intoa signature.

Faulted components_{may be identified}

by

_comparing theirsignature to the expected

signature for a

functionally

correctDUT.

The '8373 is anexample that shows how scan _circuitrycan be addedto a circuitdesign to

increase its testability. The additional _circuitry is

fully

transparentand its testing

capabilityrequires _only a four bit wide bus.

Furthermore,

the

boundary

scan path need

not _stop at oneIC or one PCB; it _{may be} extended to several boards

by

_simply

continuing the scan path. _Thus, the four bit testbus facilitates selfdiagnostics as well as

1.7.2

Tektronix

LV500

The TektronixLogic Verifier

(LV)

is used to testcomplicated circuitdesigns. The

current system at RIT canhandle _upto 64 bi-directional signals, driven

by

up to four

independentclocks. The LV500 is primarily usedfor_testing digitalcircuits and hasbeen

modified at RIT

by

the addition ofa40-pin Zero InputForce (ZIF) testhead. Although

at higherfrequencies the testheadcan be adisadvantage

by

_adding capacitance and

resistance to the connection between the tester and

DUT,

the systemis adequate for the

operating speed of most normal student projects. With this _{testhead, any} IC

directly

interfaces to the

LV500,

as the

following

tutorialdemonstrates. Anotherfeature ofthe

LV500is its compatibility with the MentorGraphicsEDA (Electronic Design

Analysis)

tools used in RIT's VLSI Design Laboratory. The application programTekWAVES can

be used to translate-2 _Mentor Graphics'

test vector (event

driven)

format intothe LV500's

statedriven format*.

Thus, one _{may design} and simulate an _{IC using Mentor}

Graphics'

tools, fabricate that IC

with the aid ofRIT's Microelectronics

facilities,

and then test the circuit _using the same

test simulation vectors that were used in thedesign on theHP/Apollo workstations.

*

TekWAVESsamplesthe event state changesfrom the Mentorstatefileand creates an outputfilethai

2,0

Functional

Specifications

The LV500'smenus are discussed as_theyrelate to the exploration of

boundary

scan

devices. The firsttwoexamplesofChapter 3 utilize theconcepts presented in this

section.

2.1

Overview

of

Tutorial

The organization ofthetutorial sectionsofChapter 3 is similarto a user's manual. The

format foreach ofthe examplesincludes:

1. Overview ofTest Purpose A Textual description of what the test will show

with _{supporting logic diagrams.}

2. Test

Setup

The steps used to recall stored test parameters on theLV500.

3. DUT

Wiring

Hardware and Menu A stepwise installationguide to _wiring

the testheadcircuitry.

4. LV500

Setup

Menu _{The logical mapping} oftest vectorfile signals to DUT

pins.

5. Pattern test Vectors A

listing

ofthe test vectors to _applyto theDUT.

6.

Invoking

the test describes how to start and proceed through a test.

2.2

LV500

Setup

and

Configuration

This section describes menuinformation that is displayed onthe LV500 andis pertinent

to the _testing examples. The installation ofthe testhead is alsodiscussed.

2.2.1

Menus

The LV500 is driven

by

interactive menus.

Physically,

thesemenus are controlled

by

the

keyboard shown in Figure 10. It is divided into the

following

main groupsofkeys:

1. A QWERTY (standard style) keyboard.

2. The program-controlled function keys

(top

row: Fl

F8)

whose functions

change _accordingto thecurrent menu.

3. A dedicated function keys (alsoon the _toprow: _<Notes>, <_{>, <Print>,} and

<SelectMenu>).

4. The

display

control keys

(including

the

joystick),

which provide cursor

lis

Sjs

is

(A sE

ic2 o

~i IS 5 1

IS .. - fe-5 o og SB | 2 Q UJ -J ^w o> ccUJ H* z oz oo E=> Oil O oc a otitis _

m o <0 ffi -_C

^ . g

JC O S 3

h- _{o ^}. n co o

i8S O Q.O

nb

ii

>

li

HI

0-<

Si

4 _

IT

- ₂ o t 8 its

M

2S (A > OUJ UJ* o2 So Sz Qd u. a>

2 (2 S

3 C

5u

o

WCA~ 2 5 =

o E-8 2 c E.2 (A w O > tn

is

IPS

Ilc-i

<53 a < a > UJ * 5-S? $8 2 u

Fieure 10 LV500 Keyboard. LV500 Keyboard layoutanddescription

ofstandardfunctions.

When thedevice is

initially

turnedon, the Power Up* menu ofFigure 1 1 is

displayed,

providing information about the system configuration. Bepatient, ittakes _{approximately}

three minutes to

fully

power_up the system. Appendix Cdiscusses howto acquire screen

dumps and textfiles from theLV500. Several othermenus will beencountered

throughout this _tutorial; tosee thempress the<SelectMenu>key.

They

are categorized

(as shown in Figure

12)

underfour headings:

1. LV

Setup

Allowsthe specification of_{supply voltages,} channel _assignments,

et cetera priorto the_running of a test.

2.

Display

Allows the_editing oftest patterns, control ofthedisplay, and the

viewingoftestdata &results.

3. Utilities Allows the access of system-level tools.

4. Applications Provides access to application software packages.

Thereare three ways to move about the menus oftheLV500. Onemethod is to usethe

joystickor cursor control keys to position the highlightedcursor on_top ofthe desired

menu. Press <Return>, and the highlighted menu will open. The second methodof

transversing the menus requires the_pressing ofafunction

key

(F4 through F8). As Figure 12 shows, there are four function keys corresponding to the fourmenu categories.

This will open the menu that is highlighted fora particularcategory. The third

possibility is tohit the <Select Menu>

key

while in the main menu. This allowsforthe

name ofa specific menu to be entered. In a sub_menu, the <SelectMenu>

key

can be

used to return back tothe main menu.

LU 5S0 9'JrE,4-l TEKTROHi:-: LU 501-3

Utilities Power _Up Idle

?-,-11

slot 0 Controller PASS

slot 1 _Memory S Mbyte PASS

slot o 9LhN Network Controller PASS

slot 3

slot 4 95'164PM 64 Channels'Pattern Generation pass slot 5 9S')64E 64 Channels'_Error Storage PASS slot 6

slot 77 slot 3

Mainframe PASS _Floppy Disk Hard Disk

1.?. Mbyte 43 MByte

PhSS PhSS

System Software Release Version 1.41 Date: 7 June 1991 Previous Shutdown: Normal Time* 13:43

Press Select Menu'

or Shift Select Menu to move between menus

Press 'Notes'

twice for a description of the LU 530 NOTES system

Fl STnrT $'Jfc4-l F4 F5 TERMINhL SET SETUP TIME

Figure 11 Power

Up

Menu. LV500 menudisplayeduponinitial

system power up.

4-1 Utilities p. Idl*

Ui 5GG MENU SELECTION

Module

^i-Ut.4-1

LU _{Set.up Display} Utilities Hppl ications

F4 F5 F* F7

Sy= Conf1q Pattern Power _Up LU Toolkit CIue Setup Macro Save Festore

Sys Monitor Schmoo Disk Services

Symbol Edi tor

Conf₁₃ Commumcation

DUT Uirin:i HW SU Uersion

Channel Orientation

Template

Det Schmoo

Press F4 , F5, F6 or F7 to move to the sel ected menu.

Press Select Menu or 'Shift Select Menu'

to move between menus. Press Notes twice for a description of the LU 500 NOTES system. Fl

ESCAFE

? CAMi:EL

F4 FS _F6 F7 FS

MOUE TO MOUE TO MOUE TO MOUE TO EXIT LU SETUP DISPLAY UTILITY APPLICTN 5 SA"t Fieure 12 Main Selection Menu. LV500menu_showingthefourmain

functionalcategories.

Open the Orientation menu atthis time. It appears undertheUtilities_category and

contains usefulinformation aboutthe LV500.

Also,

the<Notes>

key

which provides on

line documentation forthecurrent cursorfield. When pressedtwice in succession, the

notes

key

describes itself. Therestofthis tutorial willprovide enough information about

the LV500 to _step through the

boundary

scan examples. Foramore in-depth look at the

LV500's

functionality

referto the appropriate Tektronix LV500manual.23'24>25

2.2.2

Testhead

Installation

Ifthe 40 pin ZIF testhead is not the _currently installed, then it will need to be doneprior

toLV500 power up. Ifyou are notfamiliarwith the installationofthe _testhead, it is wise

to ask forthe assistance of someone who is. There are gold elastomeric connectors on

the underside ofthetesthead that are_{easily damaged.} These gold

"contacts"

provide the

means to pass the signalsfrom the LV500 testhead to its controller. Avoid _touching

them because dirt and oil from yourfingers_{may degrade}the electrical _contacts, and

avoid _pokingat them since this _{may break} the contacts. Ifit becomes _necessary toclean

the contacts, do so with a cotton swab and isopropyl alcohol, wiping gently with the

"grain"

ofthe gold wires. Figure 13 displays the 40 pinZIFtesthead installed and the

LV500'scomponents _{appropriately} connected. Oncethe testheadis secured, power _up

the LV500Tterminal and then the LV500controller. This order of power_upis preferred

LV500

Tester

40pinZIF Testhead

LV500T

LV500 Conrro ler

2.3

Figure 13 LV500 SystemConfiguration. Basic hardware setup for

communicationbetweenLV500and tutorialcircuits.

40

pin

ZIF Testhead

In this tutorial the 40pin ZIFtesthead will be used asthe interface between _any DUT and

the LV500. Figure 14 shows the properpin-outforthe LV500 to testhead mapping.

Since theLV500 has 64 signals and the testhead _{has only 40 horizontalchannels,} there

are 24 channels on the LV500that are not connected to the testhead.

LV500 Port Connections

Ni

VCC

GNDL

2.7

2.5 2.3

2.1

1.f

1,d

1.b

1.9

1.7

1.5

1.3

1.1

Of

O.d

O.b

0.9

0.7

0.5

0.3

0.1

40 Pin ZIF

Wiring

21

25

30

35

40

Figure 14 40 pin ZIF

Wiring

Diagram. Pin-out_ofthe40pinZIF

3,0

Tutorial

for Test Boards

Thischaptercontains the tutorialfor_exploring

boundary

scannabledevices on the

LV500. The use ofthree examples allows a_rampingoftheconcepts and aconcrete

foundation for_exploring othercircuits on the LV500. The first example includes_only a

single '8373 connected to the LV500. Itdemonstrates theBYPASS command in test

modeofoperation, the BYPASS command in normal mode of operation and the

SAMPLEcommand. The second example includes a '8773 with additional

combinational logic. This example shows how

boundary

scannable ICsassist in

debugging

digital designs. The third andfinal example utilizes software tools available

in RIT's VLSI

Laboratory

to shows how a circuit's _{testability is}increased through

boundary

scan design methods.

3.1

Single Test

Chip

The single _chiptest example is used tointroduce the world of

boundary

scan devices. A

single '8373 is pluggedinto theDUTtesthead and exercised _using theLV500.

3.1.1

BSCANJ

Test

Setup

Now _step through theLV500's menusto _verify the proper operation of a single

SN74BCT8373 IC and provide a basis from whichto furtherexamine the '8373's

functionality. In order to run a completed test, three components are needed. The

following

test components can be developed in any_order, but _theymust all be present at

the time the device is tested:

DUTWiring

A properly wired circuiton the testhead.

LV500 setup Acomplete _mappingof signals from the testvector file to the

DUTand adescription ofthe _timingrelationships for each testcycle.

Pattern testvectors Acomplete listofinputs

driving

the DUT and the

expected outputs.

Once the _{LV500 is running} and the Power

Up

menu ofFigure 1 1 is successfully

displayed, the BSCAN_I system configuration software must be loaded. This will setthe

LV500's current_working environment. If still in the Power

Up

menu, press the <Select

Menu>

key

to enterthe main menu ofFigure 12. Now, open the Save/Restoremenu

under the Utilities category. A menu similarto the Save/Restoremenu ofFigure 15

should be displayed.

LU 500 92U64-1 Utilities a-e Pesto Idl

Opera1i on : Pestore SeKip

File! BSChN I-new

Ccwfoents! Mul_Mchip boundary ican +'j+or1 'il C'i =pl:i-j: _[ire

:t.,ry C'lil- tree =pa.:e: 3129? fbVe=

File Home Size i.cv-ed fOWien*=

743 te:-t r^ _{05 09 91 00:15}

74F547 c -.

03 13'94 01=15

bscmnj 71 03 10 91 04:4? 91fi|i1e :hifj boundar_y =: :ir. trjtor1a1.

-BSCHtl I-ne"-71

-03 07 93-09H4 Multichip boundary =ccin tutorial.

-BSCrtNJI 70 03-'

07-93 11:55 _{Multichip boundary} =<:an tutorial. BSChM II-ne c-5 OS 07 "95 0:50 MuHi-zhip boundary scan tutorial. BSCAN III 7 03 13 91 15:15 _E^ploriny the =<:an path.

HHC547 Z'c. 05 ? 94 00:46 Bill = ₅₄₇ test file

HUCPEGFILE c

-05 c'9 94 08s@l Bills reyifter test file

IN"ERTEP 51 10 15-91 03:25 INi'EPTEP SCHrlOO SETUP

INUEFTEPZ 51 11 '01 91 03:30 W'EPTEP i-CHMOO SETUP KENLED

c~

04-17-94 04:49

Us$ _{data jcrolling ^ey}= _*o select _{file we.}

Fl

START

?2>ig.4-₁

FS

EI.ECUTE OFEFMTinri

Figure 15 Save/Restore Menu. LV500 Menu displayed when_saving

Set the first field

(Operation)

ofthe Save/Restoremenu to"Restore Setup"

by

either

using the <Open/Close>

key

and thecursor_arrows, or

by

_typing the command in.

Next,

enter

"BSCANJ"

in the File field as the name ofthe file torestore. This file contains

the system set_up forthe test tobe performed. It was written

interactively

onthe

LV500T

by

myselfand saved on this same screen. Upon completing the above _steps,

press F8:EXECUTE OPERATION to execute therestore. It_only takes afew secondsto

load the

file,

after which <SelectMain> can be pressed.

40 Pin ZIF

LV500Port

/

WirinS

S : !i iurona!

VCC

GND-8pin Socket

Figure 16 Testhead

Wiring

Diagram. Pin-to-40pinZIF_wiring

diagram forfirst tutorial circuit.

3.1.1.1

DUT

Wiring

This isthe firstofthe three sections

describing

the testcomponents forthe DUT. Inthis

section the installationand _wiring ofthe '8373 ICwill beperformed. Because _only one

IC is

being

used, itwill be installed

directly

intothe 40pin ZIFtesthead. Ifthe IC

is'

not

currently in the testhead then _{plug it}

in,

_conformingto Table 1 below. The IC should be

installed such that its firstpin contacts port0.0 ofthe testhead (andthe 12th pin contacts

port 1.6). As Figure 16 shows, the IC is inserted

directly

_abutting the end ofthe 40 pin

ZIF closestto you. Because the '8373 IC has VCC andGNDpin mappingsthat differ

from the MOSIS 40pin _standard, some ofthe signals must be routedto alternative

channels.

The '8373 is an octal d-type latch when operated in normal mode of operation. The IC is

also

fully

IEEE 1 149.1 compatible when operated in its testmode. When intest mode.

the normal operation ofthe octal latch is inhibited and the test_{circuitry is} enabled to

observeand control the device's I/O boundary. Several instructionscanbe loaded and

executed

by

_using thefour standardtestlines (TDI,

TDO, TCK,

TMS). In addition to the

standard features for IEEE 1 149.1 compatibility, the octal latchcan also perform

additional tests such as PRNG and PSA. The

following

commands (Appendix E contains

detailed

description)

are executedin this tutorial:

EXTEST

Boundary

scan registeris selected in the scanpath. Data_previously

loaded into the BSR is applied to device inputs and throughdevice outputs. Device

is in test mode of operation.

BYPASS One bit bypassregisteris selected in the scan path. A logic 0 is loaded

SAMPLE

Boundary

scan registeris selected in scan path. A snapshot istaken of

thedevice inputs and outputs. The device operatesin normal mode.

Logical

Path Name

Logical

SignalName

Sector/

Channel

DUT

Pin

0 C 0.0 1

1 _1Q 0.2 ">

2 _2Q 0.4 3

3 _3Q 0.6 4

4 _4Q O.a 5

5 GND 1.2 6

6 _5Q O.c 7

7 _6Q O.c 8

8 _7Q 1.0 9

9 _8Q 2.0 10

10 TDO 1.4 11

11 TMS 1.6 12

12 TCK 1.7 13

13 TDI 2.3 14

14 8D 1.3 15

15 7D 1.1 16

16 6D O.f 17

17 VCC 1.5 18

18 5D O.d 19

19 4D 0.9 20

20 3D 0.7 21

21 2D 0.5 22

ii _{ID 0.3}

23

23 *OC 0.1 24

Table 1 Logical

Mapping

ofDUT. Table

listing

the_{mapping of}the

Logical Signalname withtheLV500 channelandDUTpins.