An Overview of the Virginia Tech Program in Software Radios Implemented with Reconfigurable Computing

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An Overview of the Virginia Tech Program in

Software Radios Implemented with

Reconfigurable Computing

Contributing Faculty

P. M. Athanas, J. H. Reed, W. L. Stutzman, W. B. Tranter, B. D. Woerner, S. F. Midkiff

Research Associates and Research Faculty

Yeongjee Chung, Francis Dominique, Ivan Howitt, Lori Hughes, Randall Nealy, Aurelia Scharnhorst

Student Researchers

Tom Biedka, Ray Bittner, Mike Buehrer, Rick Cameron, Mark Cherbaka, Neiyer Correal, Carl Dietrich, Kai Dietz, Rich Ertel, Anwarul Hannon, Scott Harper, Yanchen He,

Zhong Hu, Song Kim, Jeff Laster, Monika Maheshwari, Nitin Mangalvedhe, Raqibul Mostafa, Steve Nicoloso, Martin Pechanec, Paul Petrus, Kim Phillips, Pascal Renucci, Nattavut Smavatkul, Srikathyayani Srikanteswara, Steve Swanchara,

Mariecel Torres, Matt Valenti, Yufei Wu, Weimen You

Sponsored by

DARPA under the GloMo Program

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Objective of the Project

• Design and build a high speed radio testbed

using

configurable computing modules and

advanced receiver architectures

→_{Improved capacity}

→_{Flexibility of platform}

→_{Increases in processing power of platform}

• Demonstrate smart antennas at the handset • Create a hardware/software testbed to prove

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Overview of the Presentation

• Software Radio Using Reconfigurable Computing

→_{Introduction to Reconfigurable Computing}

→_{Example Application: Multiuser Detection}

→_{Architecture for a General Purpose Configurable}

Radio

→_{Evolution of the Configurable Computing Platform}

and Configurable Radio

• Smart Antennas at the Handset

→_{Project goals}

→_Measurements

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Introduction to

Reconfigurable Computing

Introduction to

Reconfigurable Computing

• Configurable Computing (CC) Attempts To Increase Performance And Silicon Utilization Efficiency Through Logic Recycling using FPGA and FPGA-like Devices

• Hardware Algorithms Can Be “Paged” Into/Out Of CC Modules Much As Operating Systems Perform Software Paging

• Factors Impacting the Performance

→Logic Speed

→Speed Of Reconfiguration

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FPGAs vs. DSPs

• FPGAs can support multiple memory ports • FPGAs outperform DSPs:

→Parallelism in the algorithm

→Simple operations in a fixed sequence

→FPGAs provide greater computational density using less power

→Large data sets, low resolution (8 - 12 bits)

→Simple control

• DSPs outperform FPGAs

→MAC operations

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Configuration information

→Routing information →_{Variable size}

→_{Possibly removed as stream}

routs

Application data stream

→ →_{Possibly chained} →_{Variable size} Program/Flow Header Program/Flow Header Stream Format Data

Wormhole RTR Stream Format

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Multiuser Receiver Data Flow

FROM DDC ACTUAL RECV’D SIGNAL ESTIMATED RECV’D SIGNAL BUFFER RECV’D SIGNAL & INITIALIZE STREAMS MATCHED FILTER CORRELATOR MATCHED FILTER CORRELATOR REGENERATE & COMBINE GENERATE REVISED RECV’D SIGNAL & BUFFER MATCHED FILTER CORRELATOR DEMODULATE MATCHED FILTER CORRELATOR I Q I Q REVISED RECV’D SIGNAL OUTPUT STAGE 2 STAGE 1 RECV’D DATA ACQUISTION AND TRACKING REGENERATE & COMBINE

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Multiuser Receiver Hardware

Multiuser Receiver RF Front End Transmitter Host PC Reconfigurable Computing Platform Digital Downconverter

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Reconfigurable Computing

Modules Under Development

• Turbo Coder/Decoder

• Equalizer/ Single User CDMA Receiver • Symbol/Carrier/Code Synchronizers

• Next Modules

→Generic sample rate converter

→Coder/Decoder library

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Phase 1 - Proposed Reconfigurable Receiver Architecture

Phase 1 Implementation of the

Configurable Radio

To Be Determined Filtering/ Adaptive Equalization Complex FIR Filter Despread Binary Correlator Sampling Tracking Acquisition Noncoherent Demod FSK PSK FEC Decoder Block Convolutional Turbo De-interleave Antenna Diversity Combiner Digital Down-converter Digital Down-converter RF Front End RF Front End Receiver Control Host/ Network API Sigtek ST114

Direction for replacement of DSP µP functions with reconfigurable computing

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11 Phase 3 - Proposed Reconfigurable Receiver Architecture (PCI-based)

Graychip DDC Graychip DDC ANALOG SUPPLY PCI-BASED HOST INTERFACE Q FIFO I FIFO RF Input Circuitry Channel 2 Combiner FPGA RF Input Circuitry Channel 1 A D C DSP A D C DIGITAL SUPPLY SRAM SRAM OUTPUT MODULE FPGA PROCESSING MODULE #1 INPUT MODULE FPGA SRAM SRAM PROCESSING MODULE #2 PROCESSING MODULE #4 PROCESSING MODULE #3 PROCESSING MODULE #6 PROCESSING MODULE #5 SRAM SRAM D P R A M I/Q MOD RF OUTPUT FREQ SYNTH XMIT FPGA CODEC ANALOG INPUT ANALOG SUPPLY RAM D A C D A C R A M R A M S R A M DPLL FEC

Phase 3 Final Architecture

Features

● Wider bandwidth front end

● Stallion processor

● Run-time reconfiguration ● Library of communication

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Hardware Based Simulator

• Fast simulation engine by taking advantage of reconfigurable processor

• Supports radio development effort

PC

(Preprocessor for system configuration and for setting system parameters) reset mod_sel θ Ac External input PN sequence generator (Data) Enable init_stat reg length reset σ2 seed Modulator Receiver (Demod and data decisions) Noise generator 2x1 MUX × × PC (Post-processor for data collection and analysis) I Q I Q

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Adaptive Antenna and

Direction Finding Algorithms

and Hardware

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14 Code Timing Spatial Filters Despreaders Applications Demonstrate interference rejection through spatial filtering Study algorithm performance

Perform AoA estimation for position location applications

Developing spatial channel models

Third Generation Array

Demodulator and Beamforming

Algorithm

Front End for Antenna 1

ADC / DDC (SigTek ST-114) BPF IF AMP Local Oscillator X IF LPF ~ f=1982 MHZ f=2050 MHZ

Front End for Antenna 8

ADC / DDC (SigTek ST-114) BPF IF AMP Local Oscillator X IF LPF ~ f=1982 MHZ f=2050 MHZ DSP TI C549/C541

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MPRG Vector Measurement System

● Fully functional 8 elements, 1.25 MHz

Bandwidth, 2.050 GHz center frequency

● Flexible for adapting various

antenna/polarization inputs, carrier frequencies, bandwidths, real-time algorithms, or data collection

scenarios

● Eight Harris 40214 Programmable

Direct Digital Downconverters, eight C54x DSPs, one Analog Devices 21010

● New features being added

→ CDMA capability

→ Improved system executive processing

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Research Issues

• Adaptive array algorithm performance

in real situations

• Vector channel measurements

• Practical AOA algorithm and

hardware development

• Adaptive array algorithm convergence

issues

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Measurement Result

Channel A signal strength Channel B signal strength

Signal strength using LSCMA

time

•Indoor environment •2.050 GHz carrier •stationary rx and tx •10 second collect

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Circular Model (Macrocell)*

• Models macrocell environments

• Scatterers are uniformly distributed in a

circular region about the mobile

• Approximate radius, 30 m < R < 200 m

Circular

Scatterer

Region

R

Base Station

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Joint TOA-

AOA

(Circular BS View)

Joint TOA-

AOA

(Circular BS View)

f D c D c c c D R D c D cD c c D R else b b b m b b b m τ θ τ θ τ τ τ θ π θ τ τ θ τ τ θ , ( , ) ( )( cos( )) ( cos( ) ) : cos( ) cos( ) : . = − + − − − + − ≤     2 2 2 2 2 3 2 2 3 2 2 2 2 4 2 2 0 3.4 3.5 3.6 3.7 3.8 3.9 4 -5 0 5 -1 -0.5 0 0.5 1 1.5 2

Angle of Arrival (degrees)

Time of Arrival (usec)

P ro b ab il it y D en si ty [ lo g 1 0 (f )] D = 1km R_m= 100m

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An Overview of the Virginia Tech Program in Software Radios Implemented with Reconfigurable Computing