Using SPICE for the modelization of the static behaviour of the insulated gate transistor

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Using SPICE for the modelization of the static

behaviour of the insulated gate transistor

F. Gaffiot, J.P. Chante, M. Le Helley

To cite this version:

F. Gaffiot, J.P. Chante, M. Le Helley. Using SPICE for the modelization of the static behaviour of

the insulated gate transistor. Journal de Physique Lettres, Edp sciences, 1984, 45 (18), pp.907-911.

�10.1051/jphyslet:019840045018090700�. �jpa-00232429�

Using

SPICE

for

the modelization

of the

static behaviour

of the

insulated

_gate

transistor

F.

Gaffiot,

J. P. Chante and M. Le

_Helley

Laboratoire _{d’Electronique, Automatique} et Mesures _Electriques de l’Ecole Centrale de _{Lyon (*),}

36, avenue de

_Collongue,

_{B.P. 163, 69131 Ecully Cedex,} France

(Re~u le 26 avril 1984, revise le _5juillet,

_accepte

le _{17 juillet 1984)}

Résumé. 2014 Une nouvelle

application

d’un programme de simulation de circuits (SPICE) est

_présentée

ci-dessous. Le comportement

statique

d’un composant

bipolaire

complexe (IGT) est

_analysé

à

_partir

d’un circuit

_équivalent

faisant

_apparaître

les

_{paramètres physiques}

du

_dispositif

réel. Cette

_analyse

permet de modifier les

_{paramètres technologiques}

afin d’améliorer le fonctionnement du transistor à

_grille

isolée (IGT).

Abstract. 2014 A _new

application

of a circuit simulation program _(SPICE) is

_presented.

The static

behaviour of a _complex

_bipolar

device _(COMFET or _IGT) is

_analysed

from an

_equivalent

circuit

including

the

_physical

components of the real device. It is

_possible

to infer about _{technological}

para-meters to

_improve

the

_working

of the IGT. Classification , Physics Abstracts ’ 02.70 2013 71.10 2013 72.90 1. Introduction.

The SPICE program is well known for circuit

design

but its use for the

_analysis

of

complex

devices is unusual. _{The purpose of this Letter is} to _present a new

application

of the SPICE

pro-gram :

drawing

an

_equivalent

circuit of a

_complex

_device,

it allows one to simulate its

_behaviour,

to

_point

out the influence of the electrical _parameters of the

_model,

and

_thus,

to infer the

technolo-gical

parameters of the real device.

Our work deals with the IGT

(Insulated

Gate

_Transistor)

also known as COMFET

(Conduc-tivity

Modulation

_FET),

this device has been

_{previously presented}

_[1,

2, 5,

7]

it is _very similar to

a _power

DMOS,

the

only

difference is a P+ substrate instead of a N+ one. This P+

layer

induces a

_bipolar

PNP structure and the

_resistivity

of the

_{lightly doped layer}

is so modulated

_by

the

injection

of holes

_coming

from the anode.

Due to this

_resistivity

modulation and to the current

_gain

of the PNP transistor

_experiments

show a _great

_improvement

of the ON resistance as

_compared

to a DMOS device

_having

the same features

[2-4] ;

the other

important

characteristics of the IGT or

COMFET,

as

switching

parameters,

voltage capabilities...,

allow number of new

applications

[4, 5].

(*) E.R.A. (C.N.R.S.) no 661 « Genie

_{Electronique ».}

L-908 JOURNAL DE _{PHYSIQUE -} LETTRES

2.

_Equivalent

circuit.

Figures

1 a and 1 b show

_respectively

the

_elementary

structure of the studied device and the

equi-valent circuit used for the simulation with SPICE.

It should be

_pointed

out that

_equivalent

circuits have

_already

been

_given

_[4,

_6],

but none of them included all the

_physical

_components as shown in

figure

1 b.

The

_MOSFET,

the JFET and the

_Rx

resistance simulate the internal vertical DMOS _part of the device.

_Rx

stands for the resistance of the

_{lightly doped}

N -

_layer

and it is also the access base resistance of the PNP

_bipolar

transistor. It should be

_pointed

out that the JFET

effect,

due to

the extension of the _space

_{charge layer}

at the PN-

_junction,

is _very

_important

in

_{high voltage}

structures with low

_doping

level in the N- base and in

_strongly

densified devices. If the

_spacing

between the P

_regions

increases or if the N -

_layer

is

_{sufficiently doped}

the JFET _may be

sup-pressed.

Fig.

la. -

Elementary structure used for

_{experiments (v-layer : lightly doped N-layer).}

n

Fig.

1 b. -

The

_bipolar

NPN and PNP transistors stand for the

_thyristor

structure. R’ is a little resistance which simulates the P

_layer

between the active base

region

of the NPN transistor and the channel

region

of the MOSFET and

_Ry

is the

_pinched

resistance of the P

_layer

beneath the N + source

layer.

This last resistance which is crossed

_by

a hole current has two

_important

effects.

(i)

Induction of a

positive voltage

under the MOSFET

channel,

resulting

in a

_biasing

of the MOSFET substrate and in an increase of its drain current. The _parameters

_{required by}

SPICE 2

to simulate the substrate effect are not _very well known so we

_assign

them to be zero and we take this effect into account

_by

means of the current source

_IB.

This _source,

_being

controlled

_by

the substrate

voltage,

stands for the increase of the drain current. The shift of the threshold

_voltage

due to the substrate bias is

--_..-then the shift of the drain current _may be written

where g

is the

_elementary

_{charge, Na the}

substrate

_doping,

Z the channel

width,

L the channel

length,

~ the electron

mobility, lis

the silicon

permittivity, C;

=

(2013 )

the insulator

capacitance,

d

VDS

the drain to source

_bias,

_VBS

the substrate to source bias and

_B

the

_potential

difference between the Fermi level and the intrinsic Fermi level.

In the

_program,1B

is written as a

polynom

obtained

by

a mean _{square method.}

It is clear that this effect occurs for all the _gate bias levels and the model can be used to _represent

normal and subthreshold behaviours.

(ii)

Forward

_biasing

of the emitter-base

_junction

of the NPN

_{bipolar-transistor,}

which leads

to a

_thyristor

behaviour

[2, 4]

(in

this case, the gate can no

_longer

turn off the anode

_current).

Among

the electrical _parameters

_{required by}

_{the SPICE program} some of them are obtained

by experiments (bipolar

transistor current

_gain,

threshold

_voltage

of the

_MOSFET,

carrier lifetime in the N -

_layer).

Other ones are calculated from the

_{technological}

_parameters of the

device like

_{doping profiles,}

oxide

thickness,

geometrical

dimensions

_(1B

current source, MOSFET

transconductance,

JFET

_parameters).

The last ones are used for the fit of the

_computed

and

experimental

curves

_{(resistances,}

_{junction leakage}

_current).

3. Results.

Experimental

and theoretical curves are shown in

_figures

2a and 2b

respectively.

These charac-teristics have been drawn with an

_elementary

device :

therefore,

the values of the anode current

are low.

The first

_negative

resistance

_{region (region}

_A,

_Fig.

_2a)

is due to the increase of the MOSFET conductance as a result of the internal

biasing

of the

P layer.

The second

_negative

resistance

_{region (region}

_B,

_Fig.

_2a)

_corresponds

to the transition from a

_bipolar

MOSFET

Darlington working

mode to a

_thyristor

behaviour

_(the

internal

_biasing

of the P

_layer

results also in a

biasing

of the N+ P

_junction

in the forward

_direction).

It should be noted that the first

_negative

resistance _appears

_only

at

_relatively

low _gate bias.

L-910 JOURNAL DE PHYSIQUE - LETTRES

Fig.

2a. -

Experimental

characteristics :

_VA

is the anode voltage,

V G’

the _{gate voltage,}

_IA,

the anode current.

Fig.

2b. -

Computed

curves, for two values of the _gate bias

_voltage.

4. Conclusion.

This use of SPICE program

_permits

us to

_analyse

the behaviour of a

_complex

structure like the

IGT ;

the

_equivalent

circuit -

suitable for _computer aided circuit

_design

- of this

gives

good

I(V)

characteristics

_distinguish

different

working

modes of the

device,

which we summarize below :

-

power MOSFET at low _gate bias

_voltage,

- IGT

at

_higher

_gate bias

_voltage

and at

_relatively

low anode current

level,

-

gate controlled

thyristor

at

_high

_gate

bias

_voltage

and at

_high

anode current level.

Finally,

the SPICE _program makes it

_possible

to determine the contribution of each

_physical

component involved

in

the

three

_working

modes and then to choose the _parameters which

pro-mote _any of them.

Acknowledgments.

We would like to thank P. Rossel and P.

_Leturcq

for

_helpful

discussion.

References

[1] DESCAMPS, B., « Transistor

_bipolaire

à commande _par effet de

_champ

au _{moyen d’une}

_grille

_{isolée »,}

Patent n° _{81.11835, june} 1981.

[2] BAUDELOT, E., CHANTE, J. P., URGELL, J. J., Electron. Lett. 18, n° 13 ₍₁₉₈₂₎ 546.

[3] BALIGA, B. J., MARVIN SMITH, EDN 29 ₍₁₉₈₃₎ 152.

[4] BAUDELOT, E., « Etude des

_{caractéristiques statiques}

des structures

_thyristor

commandées par

grille

isolée : le THYMOS », thèse de

Docteur-Ingénieur, juin

(1983), ECL.

[5] BALIGA, B. J., ADLER, M. S., GRAY, P. V., LOVE, R. _{P., ZOMMER, N.,«} The insulated _gate rectifier _{(IGR) :}

a new _{power switching device »,} IEDM 82, pp. 264-267.

[6] GODIN, R. J., Int. Electron. 15 ₍₁₉₈₂₎ 52.

[7] RUSSELL, J. P. et al., IEEE Electron Devices Lett. EDL-4 ₍₁₉₈₄₎ 63.