Design and implementation of I2C with Bist Technique on FPGA

Jayashri H M, IJRIT-428 International Journal of Research in Information Technology

(IJRIT)

www.ijrit.com ISSN 2001-5569

Design and implementation of I2C with Bist Technique on FPGA

Jayashri H M Department of ECE SIT Mangalore, India [email protected]

Shilpa k

Asst Professor, Department of ECE SIT Mangalore, India [email protected]

Abstract—The I2C (Inter-Integrated Circuit) protocol is used to attach two devices for communicating with each other in a fast way exclud- ing data losses. With the fast development of Integrated Circuits (ICs) technology, the complication of the circuits has also raised. Therefore, the complexity of the circuit requires self-testability in hardware to palliate the product failure. Built-in-self-test (BIST) is such a technique which can meet the necessity of self-testability with an effective solution over pricy circuit testing system. This project represents designing and implementation of Inter-Integrated Circuit (I2C) protocol with self-testing ability.

Index Terms— LFSR, BIST, FPGA, inter integrated circuit, Verilog HDL,

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The size and power requirement of IC get reduce over the year. As Moor’s law states that for every two years number of transistor inte- grated on chip doubles. The packaging of IC requires a larger area due to the interconnections in between ICs .these wire requirement can be reduced by using I2C protocol.

I2C or I square C is commonly called as inter-integrated circuit. This I2C protocol is used for communication between the faster device and slower device without ant data loss.

As the complexity of the circuit increase, it requires Self-testability. The self-testability is done using one the technique called BIST (built in self-testability). It eliminates the external test pattern generation and simulation process. Testing time and hardware requirements can be reduced and minimized respectively.

2. I²C SPECIFICATIONS

I²C bus is built around a two wire serial bus. SDA(serial data) and SCL (serial clock line). I²C is a simple, low bandwidth, short distance pro- tocol. Most available I²C devices operate at a speed of 400kbps. It defines the concept master and slave device. Master initiates a transfer of data by generating a clock signal. The device addressed by the master is called as slave device. If more than one master tries to attain the bus, there will be conflict. This conflict is solved by arbitration process.

2.1 I²C characters

The SDA and SCL lines are bidirectional half duplex in nature carry information between master and slave device. These two lines are con- nected to the positive supply through a pull up resistor. Bus is free when both the lines are high.

2.2 Data transfer

Data is transferred after start condition. The transmission is of byte oriented. The data is placed on SDA line. After sending data, SDA line is made free by master. Acknowledge is sent by pulling SDA line low. If data is not accepted by the slave device, slave will send nonacknow- ledge by leaving SDA line high. Master senses this NAK signal and it stops the data transfer or it will initiate restart.

Jayashri H M, IJRIT-429 2.3 Features

1. Multi master operation.

2. Clock stretching and wait state generation.

3. Generation of start, repeated start, stop, acknowledge.

4. Detection of start, repeated start and stop.

5. Bus state detection.

6. Supports 7 and 10 bit addressing modes.

7. Operates for various range of clock frequency.

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The proposed architecture consists of two modes. One is normal mode and other BIST mode. In normal mode device works like usual syn- chronous I²C devie.where as in BIST mode the I²C test itsef.

3.1 BIST module

One of the techniques that used to tset the circuit itself is know as Built-In-Self-Test (BIST). The embedded logic blocks, sequential logic, combinational logic, multipliers and memories can tsest to prevent ciruit failure by theis BIST technique. In SoC design most of the cores are

integrated on the single chip so accessing thse embedded cores from outsie became great difficult, so testing of these SoC became a great challenge

Fig 1: I²C strcture with BIST

The control signal block controls the BIST module. The BIST module consists of two sub blocks. They are comparator and random pattern generator.

Random pattern generator: RPG is a part of BIST module, which is used for the verification of the circuits like I²C protocol. Many me- thods are used to design the BIST module. The bytes required to test the circuit is genetrated by the random pattern generator. Random pat- tern generator consists of two LFSRs. One LFSR is used to generate the register address and other LFSR gives the data. The byts generated by these LFSRs are given directly to I²C module. From I²C these bytes are given to thecomparator to attain the better fault coverage.

Comparator: It is used to compare the transmitted bit pattern from randaom pattern generator and received bit pattern from the I²C module.

If there is any error, the error signal wil be high. And if both the pattern matches it makes not error signal to high. By this way we can clearly get to know whether data transferd is succcessfull or not successful.

3.2 I²C module

I²C module module consists of master and slave device. FPGA is used as master and EEProm as a slave device.

I²C is implementaed using FSM( finite state machine). It is a sequential circuit. As the name idicates it uses finite states to keep track of history of operations.

The EEPROM and the device which control EEPROM uses same clock. Minimum clock frequency is required for the serial chips. Serial EEPROM has the 8 pins

• VCC and VSS for power and ground

• SCL (Serial Clock) to keep track of the data.

• SDA (Serial Data) used to transfer data from or to the device.

The first three bits of the 8-bit slave address are set using select inputs S0, S1, S2. For embedded application, EEPROM uses serial inter-

Jayashri H M, IJRIT-430 face protocol like I2C for data transfer. Other protocols which are used foe serial interface are SPI, micro wire and others.

Fig 2:

s

Fig: 2 low chart of I²C with BIST technique

Step 1: The start condition is when the data line goeslow and immediately after the clock line goes low.

Step 2: Master send the adress of the slave device.

Step 3: Slave gives a acknowledgement signal to the Master the device.

Step 4: After receiving the acknowledgement signal, the master then sends the address of the register where to save the data.

Step 5: Slave again sends an acknowledgement signal to master device about the confirmation of word address reception.

Step 6: Master then sends the data to the slave using the data bus.

Step 7: After the reception of data the slave again gives an acknowledgement signal.

Step 8: Master then send the stop bit. When the clock line goes high from low and immediately after the data line goes high then this indi- cates a stop bit.

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Jayashri H M, IJRIT-431 Fig 3: Pin diagram of I2C with BIST

Fig: 3 shows the pin diagram of I2C with the BIST capability.it shows the input applied to the device and corresponding outputs got at the output side of the device.

In fig 4: the top level schematic of BIST module is shown.Its shows that two LFSRs are used in the BIST module for the pattern generation.

Fig 4 Top level schematic of BIST module 4.2 simulation results

The timing diagram achieved from the testbencher showed that the received data in the receiver.

Simulation results for BIST mode

Jayashri H M, IJRIT-432 Fig 5: BIST mode output

Fig 5 shows BIST mode simulation result, where we can see that received and transmitted are equal. Hence not error signal is high, shows that data transferred without any dat loss.

Simulation result for normal mode

In normal mode devie works like usual I2C device. Writing data from master to slave and reding data from slave to write happens in the normal mode.

Start register add ACK Fig 6: write operation

In write operation, WR bit is made high. After sending the register address from the master slave acknowledges by ACK signal. Once ACK signal is received data is written to the slave.

Jayashri H M, IJRIT-433 Fig 7: read operation

In read operation, RD is made high and data is read from the slave to master.

4.3 FPGA implementation

FPGAs can be used to implement any logical function that can be performed by an ASIC, and it should also be noted that FPGA design is more cost-effective than that of ASIC. They have lots of advantages over microcontrollers, such as greaterspeed, number of I/O ports and performance.

The proposed design is implemented on Xilinx Spartan-3

FPGA (XC2S150). So here, the master device is Xilinx Spartan-3 FPGA. The slave device used here is EEPROM in FPGA. Here, EEPROM means electrically erasable programmable read only memory. EEPROM is a non-volatile memory. It is used as a slave device to store small amounts of configuration information.

Fig. 10 shows the FPGA implementation with Clock and Data bus

I2C clock

The Device utilization summary is given in Table 1 and. From the table it is seen that only 21% if the flip flops are used. In case of input output buffers it is 28%. So that, there are many more feathers can be added with the proposed architecture. In the timing summary, it is seen that the maximum delay is 5.936ns which is much lesser than conventional UARTs.

Table 1: Device utilization summary

name Used blocks Percentages (%)

Number of slices 41 out 0f 192 21 Number of sslice flip

flops

44 out of 384 11 Number of LUTs 72 out of 384 18 Number of bonded

IOBs

26 out of 90 28 Number of GCLKS 2 out of 4 50 Xilinx Spartan3

FPGA(XC3S400)

Slave device (EEPROM)

Jayashri H M, IJRIT-434

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I2C bus is used by many integrated circuits and is simple to implement. Any microcontroller can communicate with I2C devices even if it has no special I2C interface. I2C specifications are flexlible - I2C bus can communicate with slow devices and can also use high speed modes to transfer large amounts of data. Because of many advantages, I2C bus will remain as one of the most popular serial interfaces to connect inte- grated circuits on the board.

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