Lecture 10: Sequential Circuits

Introduction to

CMOS VLSI

Design

Lecture 10:

Sequential Circuits

David Harris

CMOS VLSI Design

10: Sequential Circuits Slide 2

Outline

q  Sequencing

q  Sequencing Element Design q  Max and Min-Delay

q  Clock Skew

q  Time Borrowing

Sequencing

q  Combinational logic

–  output depends on current inputs q  Sequential logic

–  output depends on current and previous inputs –  Requires separating previous, current, future –  Called state or tokens

–  Ex: FSM, pipeline CL clk in out clk clk clk CL CL

CMOS VLSI Design

10: Sequential Circuits Slide 4

Sequencing Cont.

q  If tokens moved through pipeline at constant speed, no sequencing elements would be necessary

q  Ex: fiber-optic cable

–  Light pulses (tokens) are sent down cable

–  Next pulse sent before first reaches end of cable –  No need for hardware to separate pulses

–  But dispersion sets min time between pulses q  This is called wave pipelining in circuits

q  In most circuits, dispersion is high

Sequencing Overhead

q  Use flip-flops to delay fast tokens so they move through exactly one stage each cycle.

q  Inevitably adds some delay to the slow tokens q  Makes circuit slower than just the logic delay

–  Called sequencing overhead

q  Some people call this clocking overhead

–  But it applies to asynchronous circuits too

CMOS VLSI Design

10: Sequential Circuits Slide 6

Sequencing Elements

q  Latch: Level sensitive

–  a.k.a. transparent latch, D latch q  Flip-flop: edge triggered

–  A.k.a. master-slave flip-flop, D flip-flop, D register q  Timing Diagrams –  Transparent –  Opaque –  Edge-trigger D Flo p Lat ch _Q clk clk D Q clk D Q (latch) Q (flop)

Sequencing Elements

q  Latch: Level sensitive

–  a.k.a. transparent latch, D latch q  Flip-flop: edge triggered

–  A.k.a. master-slave flip-flop, D flip-flop, D register q  Timing Diagrams –  Transparent –  Opaque –  Edge-trigger D Flo p Lat ch _Q clk clk D Q clk D Q (latch)

CMOS VLSI Design

10: Sequential Circuits Slide 8

Latch Design

q  Pass Transistor Latch q  Pros

+ Tiny

+ Low clock load q  Cons

–  V_t drop

–  nonrestoring –  backdriving

–  output noise sensitivity –  dynamic

–  diffusion input

D Q

φ

Latch Design

q  Transmission gate

+ No V_t drop

- Requires inverted clock D Q

φ

CMOS VLSI Design

10: Sequential Circuits Slide 10

Latch Design

q  Inverting buffer + Restoring

+ No backdriving + Fixes either

•  Output noise sensitivity •  Or diffusion input –  Inverted output D φ φ X _Q D Q φ φ

Latch Design

q  Tristate feedback + Static

–  Backdriving risk

q  Static latches are now essential

φ

φ φ

φ

Q

CMOS VLSI Design

10: Sequential Circuits Slide 12

Latch Design

q  Buffered input

+ Fixes diffusion input + Noninverting φ φ Q D X φ φ

Latch Design

q  Buffered output + No backdriving

q  Widely used in standard cells + Very robust (most important) -  Rather large

-  Rather slow (1.5 – 2 FO4 delays) -  High clock loading

φ φ Q D X φ φ

CMOS VLSI Design

10: Sequential Circuits Slide 14

Latch Design

q  Datapath latch + Smaller, faster - unbuffered input φ φ φ φ Q D X

Flip-Flop Design

q  Flip-flop is built as pair of back-to-back latches

D Q φ φ φ φ X D φ φ φ φ X Q Q φ φ

CMOS VLSI Design

10: Sequential Circuits Slide 16

Enable

q  Enable: ignore clock when en = 0 –  Mux: increase latch D-Q delay

–  Clock Gating: increase en setup time, skew

D Q Lat ch D Q en en φ φ Lat ch D Q φ 0 1 en Lat ch D Q φ en D Q φ 0 1 en D Q φ en F lo p F lo p F lo p

Reset

q  Force output low when reset asserted q  Synchronous vs. asynchronous D φ φ φ φ Q Q φ φ φ φ reset D φ φ φ Q φ φ D reset Q φ D reset φ reset Sy nc hr on ou s R es et As yn ch ro no S ymb ol Flo p D Q Lat ch D Q reset reset φ φ φ Q

CMOS VLSI Design

10: Sequential Circuits Slide 18

Set / Reset

q  Set forces output high when enabled

q  Flip-flop with asynchronous set and reset

D φ φ φ φ φ φ Q φ φ reset set reset set

Sequencing Methods

q  Flip-flops q  2-Phase Latches q  Pulsed Latches Fl ip-Fl op s Fl op Lat ch Fl op clk φ1 φ2 φp clk clk Lat ch Lat ch φp φp φ1 φ2 φ1 2-P ha se Tra ns pa re nt La tc he s P uls ed L atc he Combinational Logic Combinational Logic Combinational Logic T_c T_c/2 t_nonoverlap t_nonoverlap t_pw Half-Cycle 1 Half-Cycle 1

CMOS VLSI Design

10: Sequential Circuits Slide 20

Timing Diagrams

F lo p A Y t_pd Combinational Logic A Y D Q clk clk D Q Lat ch D Q clk clk D Q t_cd t_{setup t} hold t_ccq t_pcq t_ccq t_setup t_hold t_pcq t_pdq t_cdq

t_pd Logic Prop. Delay

t_cd Logic Cont. Delay

t_pcq Latch/Flop Clk-Q Prop Delay

t_ccq Latch/Flop Clk-Q Cont. Delay

t_pdq Latch D-Q Prop Delay

t_pcq Latch D-Q Cont. Delay

t_setup Latch/Flop Setup Time

t_hold Latch/Flop Hold Time

Contamination and Propagation Delays

Max-Delay: Flip-Flops

F1 F2 clk clk clk Combinational Logic T_c Q1 D2 Q1 D2 t_pd t_setup t_pcq

(

)

sequencing overhead pd c t _≤ T _{− 1 44 2 4 43}

CMOS VLSI Design

10: Sequential Circuits Slide 22

Max-Delay: Flip-Flops

F1 F2 clk clk clk Combinational Logic T_c Q1 D2 Q1 D2 t_pd t_setup t_pcq

(

setup

)

sequencing overhead pd c pcq t _≤ T ₋ t ₊t 1 4 2 4 3

Max Delay: 2-Phase Latches

T_c Q1 L1 φ₁ φ₂ L2 L3 φ₁ φ₂ φ₁ Combinational Logic 1 Combinational Logic 2 Q2 Q3 D1 D2 D3 Q1 D2 Q2 D1 t_pd1 t_pdq1 t_pd2 t_pdq2 ( ) 1 2 sequencing overhead pd pd pd c t =t +t ≤T _{− 1 44 2 4 43}

CMOS VLSI Design

10: Sequential Circuits Slide 24

Max Delay: 2-Phase Latches

T_c Q1 L1 φ₁ φ₂ L2 L3 φ₁ φ₂ φ₁ Combinational Logic 1 Combinational Logic 2 Q2 Q3 D1 D2 D3 Q1 D2 Q2 D3 D1 t_pd1 t_pdq1 t_pd2 t_pdq2 ( ) 1 2 sequencing overhead 2 pd pd pd c pdq t =t +t ≤T − t 1 2 3

Max Delay: Pulsed Latches

T_c Q1 Q2 D1 D2 Q1 D2 D1 φ_p φ_p φ_p Combinational Logic L1 L2 t_pw (a) t_pw > t_setup Q1 D2 (b) t_pw < t_setup T_c t_pd t_pdq t_pcq t_pd t_setup

(

)

sequencing overhead max pd c t _≤ T _{− 1 4 4 44 2 4 4 4 43}

CMOS VLSI Design

10: Sequential Circuits Slide 26

Max Delay: Pulsed Latches

T_c Q1 Q2 D1 D2 Q1 D2 D1 φ_p φ_p φ_p Combinational Logic L1 L2 t_pw (a) t_pw > t_setup Q1 D2 (b) t_pw < t_setup T_c t_pd t_pdq t_pcq t_pd t_setup

(

setup

)

sequencing overhead max , pd c pdq pcq pw t _≤ T ₋ t t ₊t ₋t 1 4 4 4 4 2 4 4 4 43

Min-Delay: Flip-Flops

cd t ≥ CL clk Q1 D2 F1 clk Q1 F2 clk D2 t_cd t_hold t_ccq

CMOS VLSI Design

10: Sequential Circuits Slide 28

Min-Delay: Flip-Flops

hold cd ccq t _≥ t ₋ t CL clk Q1 D2 F1 clk Q1 F2 clk D2 t_cd t_hold t_ccq

Min-Delay: 2-Phase Latches

1, 2 cd cd t t _≥ CL Q1 D2 D2 Q1 φ1 L1 φ2 L2 φ1 φ2 tnonoverlap t_cd t_hold t_ccq

Hold time reduced by nonoverlap

Paradox: hold applies twice each cycle, vs. only once for flops. But a flop is made of two latches!

CMOS VLSI Design

10: Sequential Circuits Slide 30

Min-Delay: 2-Phase Latches

1, 2 hold nonoverlap cd cd ccq t t _≥ t ₋t ₋ t CL Q1 D2 D2 Q1 φ1 L1 φ2 L2 φ1 φ2 tnonoverlap t_cd t_hold t_ccq

Hold time reduced by nonoverlap

Min-Delay: Pulsed Latches

cd t ≥ _CL Q1 D2 Q1 D2 φp _t pw φp L1 φp L2 t_cd t_hold t_ccq

Hold time increased by pulse width

CMOS VLSI Design

10: Sequential Circuits Slide 32

Min-Delay: Pulsed Latches

hold cd ccq pw t _≥ t ₋t ₊ t _CL Q1 D2 Q1 D2 φp _t pw φp L1 φp L2 t_cd t_hold t_ccq

Hold time increased by pulse width

Time Borrowing

q  In a flop-based system:

–  Data launches on one rising edge –  Must setup before next rising edge –  If it arrives late, system fails

–  If it arrives early, time is wasted –  Flops have hard edges

q  In a latch-based system

–  Data can pass through latch while transparent –  Long cycle of logic can borrow time into next

CMOS VLSI Design

10: Sequential Circuits Slide 34

Time Borrowing Example

La tc h La tc h La tc h

Combinational Logic Combinational_Logic

Borrowing time across half-cycle boundary

Borrowing time across pipeline stage boundary

(a) (b) _Latc h La tc h

Combinational Logic Combinational_Logic

Loops may borrow time internally but must complete within the cycle

φ₁ φ₂ φ₁ φ₁ φ₁ φ₂ φ₂

How Much Borrowing?

Q1 L1 φ₁ φ₂ L2 φ₁ φ₂ Combinational Logic 1 Q2 D1 D2 D2 T_c T_c/2

Nominal Half-Cycle 1 Delay

t_borrow

t_nonoverlap

t_setup

(

)

borrow setup nonoverlap

2 c T t ≤ − t +t 2-Phase Latches borrow pw setup t _≤ t ₋t Pulsed Latches

CMOS VLSI Design

10: Sequential Circuits Slide 36

Clock Skew

q  We have assumed zero clock skew

q  Clocks really have uncertainty in arrival time –  Decreases maximum propagation delay –  Increases minimum contamination delay –  Decreases time borrowing

Skew: Flip-Flops

F1 F2 clk clk clk Combinational Logic T_c Q1 D2 Q1 D2 t_skew CL F1 clk Q1 F2 clk D2 clk t_skew t_setup t_pcq t_pdq t_hold

(

setup skew

)

sequencing overhead hold skew pd c pcq cd ccq t T t t t t t t t ≤ − + + ≥ − + 1 4 44 2 4 4 43

CMOS VLSI Design

10: Sequential Circuits Slide 38

Skew: Latches

Q1 L1 φ₁ φ2 L2 L3 φ1 φ2 φ1 Combinational

Logic 1 CombinationalLogic 2

Q2 Q3

D1 D2 D3

(

)

(

)

sequencing overhead

1 2 hold nonoverlap skew

borrow setup nonoverlap skew

2 , 2 pd c pdq cd cd ccq c t T t t t t t t t T t t t t ≤ − ≥ − − + ≤ − + + 1 2 3 2-Phase Latches

(

)

(

)

setup skew sequencing overhead hold skew

borrow setup skew

max , pd c pdq pcq pw cd pw ccq pw t T t t t t t t t t t t t t t t ≤ − + − + ≥ + − + ≤ − + 1 4 4 4 4 4 2 4 4 4 4 4 3 Pulsed Latches

Two-Phase Clocking

q  If setup times are violated, reduce clock speed q  If hold times are violated, chip fails at any speed q  In this class, working chips are most important

–  No tools to analyze clock skew

q  An easy way to guarantee hold times is to use 2-phase latches with big nonoverlap times

CMOS VLSI Design

10: Sequential Circuits Slide 40

Safe Flip-Flop

q  In class, use flip-flop with nonoverlapping clocks –  Very slow – nonoverlap adds to setup time –  But no hold times

q  In industry, use a better timing analyzer

–  Add buffers to slow signals if hold time is at risk

D φ₂ X Q Q φ₁ φ₂ φ₁ φ₁ φ₁ φ₂ φ₂

Summary

q  Flip-Flops:

–  Very easy to use, supported by all tools q  2-Phase Transparent Latches:

–  Lots of skew tolerance and time borrowing q  Pulsed Latches: