State Diagrams
2 © tj CE 1911
State Diagrams
These slides review the basics of Finite State
Machines and State Diagrams
Upon completion: You should be able to develop an
efficient state diagram for an FSM
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State Diagrams
• Finite State Machine
• State Diagram – Moore
• State • Outputs • Inputs S123 100110 In1
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State Diagrams
• Finite State Machine
• State Transition Diagram – Moore
• Transitions ONLY occur on clock edges (rising) • Transitions occur on EVERY clock edge (rising)
• Priority stop light – Inputs: Reset, Traffic N/S, Traffic E/W
• State 0 : NS light state variable (memory) holds code for green EW light state variable (memory) holds the code for red
• State 1 : NS light state variable (memory) holds code for yellow EW light state variable (memory) holds the code for red
ST0 NS: green EW: red ST1 NS: yellow EW: red
5 © tj CE 1911
State Diagrams
• Finite State Machine
• State Transition Diagram – Moore
• Transitions ONLY occur on clock edges (rising) • Transitions occur on EVERY clock edge (rising)
• Priority stop light – Inputs: Reset, Traffic N/S, Traffic E/W
ST0 NS: green EW: red ST1 NS: yellow EW: red ST3 NS: red EW: yellow ST2 NS: red EW: green
6 © tj CE 1911
State Diagrams
• Finite State Machine
• State Transition Diagram – Moore
• Transitions ONLY occur on clock edges (rising) • Transitions occur on EVERY clock edge (rising)
• Priority stop light – Inputs: Reset, Traffic N/S, Traffic E/W • Basic transitions ST0 NS: green EW: red ST1 NS: yellow EW: red ST3 NS: red EW: yellow ST2 NS: red EW: green
If we did not sense for traffic – this would be complete
7 © tj CE 1911
State Diagrams
• Finite State Machine
• State Transition Diagram – Moore
• Transitions ONLY occur on clock edges (rising) • Transitions occur on EVERY clock edge (rising)
• Priority stop light – Inputs: Reset, Traffic N/S, Traffic E/W
ST0 NS: green EW: red ST1 NS: yellow EW: red ST3 NS: red EW: yellow ST2 NS: red EW: green TNS TEW TNS TEW
8 © tj CE 1911
State Diagrams
• Finite State Machine
• State Transition Diagram – Moore
• Transitions ONLY occur on clock edges (rising) • Transitions occur on EVERY clock edge (rising)
• Priority stop light – Inputs: Reset, Traffic N/S, Traffic E/W
ST0 NS: green EW: red ST1 NS: yellow EW: red ST3 NS: red EW: yellow ST2 NS: red EW: green reset TNS TEW TNS TEW
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State Diagrams
• Timed FSMs
ST0 output 0 ST1 output 1 ST3 output 3 ST2 output 2 reset in1 t ≤ tdelay1 in1 t > tdelay1 in1 and (t ≤ tdelay2)in1 or (t > tdelay2)
conditional transition
unconditional transition
timed transition combination transition
10 © tj CE 1911
State Diagrams
• Finite State Machine
• Hardware Design Process
1) Identify the states – collectively these make a state variable 2) Identify the Inputs and Outputs
3) Assign values for each input/output (encoding) 4) Create a state transition diagram / table
5) Assign values for the state variable for each state (encoding) 6) Create truth tables for the combinational logic blocks in the
machine model: next state, output
7) Minimize the next state and output equations using K-maps or Boolean Algebra techniques
8) Draw the circuit schematic 9) Verify the solution
10) Build the physical circuit
11 © tj CE 1911
State Diagrams
• Finite State Machine
• HDL Design Process
1) Identify the states – collectively these make a state variable 2) Identify the Inputs and Outputs
3) Create a state transition diagram
4) Name each state (create an enumerated type) 5) Code the state diagram using the FSM construct
1) Next State Logic 2) Register Update 3) Output logic
6) Verify the solution
7) Build the physical circuit
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State Diagrams
• Un-used states
• Do we care about un-used states?
• YES!
• Start-up
• Bit errors
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State Diagrams
• Un-used states
• Mod 5 counter
000 010 100 011 001 101 110 111 reset14 © tj CE 1911
State Diagrams
• Un-used states
• Mod 5 counter
• What happens if an event causes the state to become
corrupted
000 010 100 011 001 101 110 111 reset15 © tj CE 1911
State Diagrams
• Un-used states
• Mod 5 counter
• Recovery solution
000 010 100 011 001 101 110 111 reset16 © tj CE 1911
State Diagrams
• Un-used states
• Mod 5 counter
• Recovery solution
000 010 100 011 001 101 110 111 reset17 © tj CE 1911
State Diagrams
• Un-used states
• Mod 5 counter
• self starting – reset not required
000 010 100 011 001 101 110 111 reset
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State Diagrams
• Redundant / Equivalent States
• Redundant states lead to more logic than necessary
• 2 States are equivalent if
• Outputs are the same
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State Diagrams
• Redundant / Equivalent States
• Informal analysis
• 3 state variables
• 3 output bits
A 100 C 110 E 101 D 101 B 010 x’y’ x+y x+y x’y’ x x’y x’y’ y y y’ y’20 © tj CE 1911
State Diagrams
• Redundant / Equivalent States
• Informal analysis
• States D and E
• have the same output (101) • both go to C when y is true • both go to D when y’ is true
21 © tj CE 1911
State Diagrams
• Redundant / Equivalent States
• Informal analysis
• Redundant states lead to more logic than necessary
• 3 state variables → 2 state variables
• 3 output bits → re-encoded to 2 bits
A 100 C 110 DE 101 B 010 x’y’ x+y x+y x’y’ x x’y x’y’ y y’ 00 01 10 11
