A Kind of High Step-Up dc/dc Converter Using a Novel Voltage Multiplier Cell
Binxin Zhu, Lulu Ren, Xi Wu
(College of Electrical Engineering and New Energy, China Three Gorges University, Yichang 443002, Hubei Province, China)
ABSTRACT—This paper proposes a kind of high step-up dc/dc converter with a novel voltage multiplier cell (VMC). The proposed VMC sharply reduces voltage stress on switches and diodes.
Therefore, the conversion efficiency can be improved significantly. The converter also provides a wide range of voltage conversion ratios including fractional as well as VMC numbers and switch duty cycle.
The topologies, operation principles, working characteristics and voltage conversion ratio are analyzed in detail. A 500W experimental prototype with two VMCs has been developed to validate the effectiveness of the theoretical analysis, and the highest efficiency is 93.8%.
Index Terms—Non-isolated, High step-up, dc/dc converter, Voltage multiplier cell
I. INTRODUCTION
Currently, dc/dc converters with high voltage gain capacity are widely used in many applications, such as photovoltaic power generation, fuel cell power generation, X-ray power supply, uninterrupted power supply(UPS) and automotive high-pressure gas discharge lamps[1-2]. Isolated dc/dc converters are able to realize a high step-up conversion gain by changing the turn ratio of the transformer windings.
However, compared to the non-isolated converters, the power conversion process is more complicated due to the existence of the transformer. So for non-isolated converters, there are more advantages in conversion efficiency, power density and cost [3-4]. In recent years, numerous non-isolated high step-up dc/dc converters have been proposed for applications where isolation is not necessary [5].
In theory, the voltage gain of the boost converter can be infinite when the duty cycle is close to 1 in ideal conditions. Actually, that is impossible due to the effects of parasitic parameters. There are also some other problems such as high voltage stress on semiconductor devices, low conversion efficiency and poor EMI performance when the boost converter is operated to achieve a larger conversion ratio [6]. High conversion ratios can be achieved easily by cascading another boost converter, but the cost is higher and conversion efficiency is lower.
Voltage gain can be increased effectively by introducing a coupled inductor, but the leakage inductance may cause high voltage spikes on the switch when it turns off. Various passive or active auxiliary circuits have been proposed to absorb the energy which is stored in the leakage inductance [7-9]. In such cases, the whole circuit may turn out to be more complex and less efficient. High voltage gain can also be realized by using a switched capacitor converter [10-12], but there are some problems as more switches are needed, the input current is pulsating, the driving circuit is complex and the voltage gain is hard to control. The problems above have been well reduced using the combination of a switched capacitor converter and the traditional switching-mode dc/dc converter in [13].
Based on an auxiliary capacitor and diode, a converter with two times voltage gain of traditional boost converter has been proposed in [14], and the voltage stress of switches have been also reduced.
However, the voltage gain is not adjustable, which limits its application rang. Inspired by the above idea of auxiliary capacitor and diode, many kinds of voltage multiplier cell have be proposed in [15-17].
High voltage gain can be realized by using these voltage multiplier cells with a traditional boost
converter. Some other advantages can also be obtained such as voltage gain is adjustable by the number of voltage multiplier cells and the voltage stress across switches and diodes is lower. Obviously, each voltage multiplier cell has its own characteristics. The voltage stress of diodes and capacitors in [15] is lower than others, but the cell needs more diodes and capacitors. However, the current RMS value of the capacitors is different from all existing voltage multiplier cells [16-17]. That is not conducive to the design of capacitors or heat sink.
This paper proposes a kind of high step-up dc/dc converter with a novel VMC, which has the advantages such as high voltage gain, low switch and diode voltage stresses, easier control and drive.
Furthermore, all capacitors share the same current stress except the two which are connected with the load. The operating principle and steady state analysis of the proposed converter with two VMCs have been discussed in section II and III. Experimental results of this converter have also been given to validate the analysis in section IV.
II. PROPOSED CONVERTERS AND OPERATION PRINCIPLE
The proposed converter contains two inductors, two switches and n VMCs as shown in Fig. 1(a).
The unit of VMC is shown in Fig. 1 (b), consisting of 2 diodes and 2 capacitors. The voltage conversion gain is 2n times of the traditional boost converter, when the duty cycle of switch S1 and S2
are both larger than 0.5.
S2 S1 uin
L1
L2
Dnb Dna D2a
D2b D1a
D1b D(n-1)a
D(n-1)b C1a
C1b C2a
C2b C(n-1)a
C(n-1)b Cna
Cnb +
uo
-
VMC1VMC2 VMC(n-1) VMCn RL
C1a
C1b D1a
D1b
（a） （b）
Fig.1 (a) Proposed converter with n VMCs when n is even; (b) Proposed VMC.
In order to simplify, the operation principle and performance analysis of the converter with 2 VMCs have been analyzed here, as shown in Fig.2.
S2 S1 uin
L1
L2
D2a
D2b D1a
D1b C1a
C1b C2a
C2b +
uo
- RL
Fig.2 Proposed converter with 2 VMCs.
S2
S1
t
t0 t1 t2 t3 t4 t5 t
State1 State2 State1 State3 State1
Fig.3 Driver signals of S1 and S2.
The driving signals of switches S1 and S2 are interleaved and both duty cycles are larger than 0.5, as shown in Fig.3. Each switch period can be divided into three modes, and the equivalent circuits of each state are shown in Fig.4. The operating stages are explained as follows.
1) State 1[t0-t1，t2-t3][Fig.4(a)]: In this mode, Switches S1 and S2 are working on ON-state, diodes D1a, D1b, D2a and D2b are OFF. During these two interval, current iL1 and iL2 increase linearly. Currents flowing through capacitor C1a and C1b are zero and uc1a, uc1b are kept constant. The load is charged by capacitor C2a and C2b, and the output voltage drops. This stage ends when S2 is turned OFF at t1 or t3. 2) State 2[t1-t2][Fig.4(b)]: In this mode, S1 remain working in the ON-state, while S2 is working in
the OFF-state. Diode D2a and D1b are ON and diode D1a and D2b are OFF. Current iL1 increases linearly, while current iL2 decreases linearly during this period. Part of iL2 flows through diode D1b and then charges capacitor C1b; the other part of iL2 flows through capacitor C1a, diode D2a and switch S1; C2a is charged while C1a is discharged during this mode. Voltages uc1b and uc2a are increasing while uc1a and uc2b are decreasing. Output voltage uo increases during this period. This stage ends at t2.
3) State 3[t3-t4][Fig.4(c)]: In this stage, S2 is working in the ON-state, while S1 is working in the OFF-state. Diodes D1a and D2b are ON and diodes D2a and D1b are OFF. Current iL2 increases linearly while current iL1 decreases linearly. Part of iL1 flows through diode D1a, switch S1 and then charges capacitor C1a; the other part of iL1 flows through capacitor C1b, diode D2b and switch S1, and then charges capacitor C2b,so the voltage of uc1a and uc2b are increasing while uc1b and uc2a are decreasing.
This state is over whenS1 is turned ON at t4.
S2 S1
uin
L1
L2
C1
C2
C3
C4
+
uo
- R D1
D3
D4
D2
+ uL1 -
+ uL2 - iL1
- uS1 + - uS2 +
iS1
iS2 iL2
- uD1 + - uD2 +
- uD4 + - uD3 + - uC2 +- uC1 + - uC4 +- uC3 +
iD1 iD2
iD4 iD3
io
iC1
iC2 iC4
iC3
(a) State 1
S2 S1
uin
L1
L2
C1
C2
C3
C4
+
uo
- R D1
D3
D4
D2
+ uL1 -
+ uL2 - iL1
- uS1 + - uS2 +
iS1
iS2
iL2
- uD1 + - uD2 +
- uD4 + - uD3 + - uC2 +- uC1 + - uC4 +- uC3 +
iD1 iD2
iD4 iD3
io
iC1
iC2 iC4
iC3
(b) State 2
S2 S1
uin
L1
L2
C1
C2
C3
C4
+
uo
- R D1
D3
D4
D2
+ uL1 -
+ uL2 - iL1
- uS1 + - uS2 +
iS1
iS2 iL2
- uD1 + - uD2 +
- uD4 + - uD3 + - uC2 +- uC1 + - uC4 +- uC3 +
iD1 iD2
iD4 iD3
io
iC1
iC2 iC4
iC3
(c) State 3
Fig. 4 The equivalent circuit of the three switching states.
Output voltage could be controlled by changing the duty cycle of switches S1 and S2. The converter with two VMCs is analyzed as an example in the following paragraph.
III. STEADY PERFORMANCE ANALYSIS A. Conversion ratio (M)
By volt-second balance of the inductor L1 and L2, the following formula can be obtained:
in ( C1a in) (1 )
u ⋅D= u −u ⋅ −D (1)
in ( C2b C1b in) (1 )
u ⋅D= u −u −u ⋅ −D (2)
in ( C1b in) (1 )
u ⋅D= u −u ⋅ −D (3)
in ( C2a C1a in) (1 )
u ⋅D= u −u −u ⋅ −D (4) Depending on (1)-(4), the voltages across the capacitors are
in
C1a C1b
1 u u u
= = D
−
(5)
in
C2a C2b
1 u u u
= = D
−
(6)
in
o
4 1 u u
= D
−
(7)
Based on (7), the conversion ratio is
o in
4 1 M u
u D
= =
−
(8)
Similarly, the conversion ratio of the proposed converter with n VMCs is
o in
2 1
u n
M=u = D
−
(9)
B. Voltage stress on semiconductor devices
To simplify the analysis process, the voltage ripple on the capacitors is ignored. According to Fig 2, the voltage across switches S1 and S2, diodes D1a, D1b, D2a and D2b can be represented as uS1, uS2, uD1a, uD1b, uD2a and uD2b respectively. Based on (5) and (6), they can be derived as follows:
o
S1 S2
4
u =u =u (10)
o
D1a D2a D2b
2
u =u =u =u (11)
o
D1b 4
u =u (12)
Extension to the converter with n VMCs, the voltage stress of all switches and diodes are
o
S1 S2
2 u u u
= = n (13)
o
D1a D2a ... Dnb u
u u u
= = = = n (14) o
D1b 2
u u
= n (15) Apparently, voltage stress on all switches and diodes has been decreased effectively according to (13), (14) and (15). This not only means that the proposed converter can use the components with lower voltage stress, but also higher efficiency can be obtained.
C. Current stress analysis
The current ripple of inductor current iL1, iL2, input current iin and output current io can be ignored to simplify the current stress analysis, and their DC values are marked as IL1, IL2, Iin and Io. According to capacitor charge balance requirement of C1a, C1b, C2a and C2b, the average current of diode D1a, D1b, D2a, D2b are equal to the output current Io, which is given by:
D1a D1b D2a D2b o
I =I =I =I =I (16) And the peak current of the diodes D1a, D1b, D2a, D2b are also obtained as:
o
D1ap D1bp D2ap D2bp
1
I I I I I
= = = = D
−
(17)
To simplify the analysis, it is feasible to take the converter efficiency as unity. Thus, the input average current is
o in
4 1 I I
= D
−
(18) According to the capacitor charge balance requirement on C1a and C1b, the inductors average current
is
o
L1 L2
2 1 I I I
= = D
−
(19)
The average currents of S1 and S2 can be acquired as:
o S1
(1 ) 1 I D I
D
= +
−
(20)
o S2
2 1 I I
= D
−
(21) When the proposed converter is used with n VMCs, the average current through switches and diodes can be deduced as:
D1a D1b ... Dna Dnb o
I =I = =I =I =I (22)
o S1
( 1)
1
n D I
I D
+ −
= −
(23)
o
S2 1
I nI
= D
−
(24) It is difficult to analyze the conduction loss of a capacitor using its average current value due to the fact that average current of the capacitor is zero when the converter is working on steady state.
Therefore, the RMS (Root-Mean-Square) value will be a more reasonable choice. The current RMS value of the capacitors are:
C1a C1b C(n-1)a C(n-1)b o
... 2
I I I I 1 I
= = = = = D⋅
−
(25)
Cna Cnb o
2
I I 1 DI
= = D⋅
−
(26) All capacitors have the same current stresses except Cna and Cnb. All diodes have the same current stresses, too. That is conducive to the thermal design.
D. Performance Comparison
A performance comparison of the proposed converter with some existing converters [3, 15-17] is given in Table I, including voltage conversion gain, switch voltage stresses and component count. In order to simplify the comparison results, the voltage stress is normalized by the output voltage uo. All switch voltage stress of these converters has been reduced and the voltage conversion gain has also been improved significantly compared to a traditional boost converter. Compared with [3], the proposed converter can not only achieve a high step-up voltage gain, but also adjust its conversion gain by the number of VMCs. To simplify the comparison of component count between different VMCs in [15-17], it is assumed that all converters can achieve 4 times the conversion ratio of a conventional boost converter. That means converter in [15] needs 2 switches, 8 diodes and 7 capacitors. Converter in [16] needs 4 switches, 4 diodes and 5 capacitors. The proposed converter and the converter presented in [17] uses 2 switches, 4 diodes and 4 capacitors. Moreover, the capacitor current stress in all voltage multiplier cells is different. The uniform VMC capacitor current stress can be achieved in this paper except Cna and Cnb according to equation (25) and (26).
TABLE I PERFORMANCE COMPARISON
Non-isolated topologies
Proposed converter
Converter in [3]
Converter in [15]
Converter in [16]
Converter in [17]
Voltage gain 2 1
n
−D
4 1 D−
1 1
n D +
−
1 1
n D +
−
1 1
n D +
− Maximum
Switch voltage stress
1 2n
1 4
1 n +1
1 n +1
1 n +1 Numbers of
Switches 2 2 2 4 2
Numbers of
diodes 2n 4 2n+2 n+1 n+1
Numbers of
capacitors 2n 4 2n+1 n+2 n+1
Adjustable gain Yes No Yes Yes Yes
Uniform VMC capacitor current stress
Yes - No No No
Where n means the number of voltage multiplier cells, D means the duty cycle.
IV. EXPERIMENTAL VERIFICATION
To verify the validity of the analysis above, a laboratory prototype with 2 VMCs has been built. The components are listed in TABLE II.
TABLE II
COMPONENT LIST FOR THE EXPERIMENTAL PROTOTYPE
Component Model Parameter
MOSFETS IPP110N20N3 Ron=10.7mΩ
Diodes STTH15L06D VD=0.95V
rD≈10mΩ
Capacitors C1a、C1b 5µF
C2a、C2b 10µF
Inductors L1、L2 300µH
Switching Frequency fs 50kHz
Input Voltage(V) uin 30
Output Voltage(V) uo 400
Output Power(W) Po 500
Fig.5 500W prototype converter.
Fig.5 shows the 500W hardware implementation of the proposed converter. The experimental waveforms are given in Fig. 6. The input voltage, output voltage and the driver signals of switches S1
and S2 which are denoted as D1 and D2, are shown in Fig. 6(a). The conversion gain is approximately 13.3 when the duty cycles are near 0.7. This is consistent with the theoretical analysis in section III. Fig.
6(b) shows the current of iL1 which is similar to iL2. Both of them are half of the input current iin. Because the input current ripple frequency is two times the switching frequency, the size of the input filter can be decreased. The voltage and current across S1 and S2 are shown in Fig. 6(c) as us1, us2, iS1
and iS2. Voltage stresses of S1 and S2 are about 100V, nearly a quarter of output voltage. Voltage
waveforms across D1a, D1b, D2a and D2b are shown in Fig. 6(d); voltage stresses of D1a, D2a, and D2b are nearly half of output voltage, approximately 200V; the voltage across D1b is a quarter of output voltage which is about 100V. The waveforms of uc1a, uc1b, uc2a and uc2b are shown in Fig. 6(e). The DC values of uc1a and uc1b are both nearly a quarter of output voltage uo, and the DC values of uc2a and uc2b are both nearly half of output voltage. The measured waveforms shown in Fig5 validate the analysis of the converter.
D1
D2
uin
uo
(a) Waveforms of input voltage uin, output voltage uo and driver signals.
il1
iin
il2
(b) Inductor and input current waveforms.
us1
us2
is1
is2
(c) Voltage and current waveforms across S1 and S2.
uD1a
uD2a
uD2b
uD1b
(d) Voltage waveforms across D1a, D1b, D2a and D2b.
uc1a
uc1b
uc2a
uc2b
(e) Voltage waveforms acrossC1a, C1b, C2a and C2b. Fig.6 The experimental waveforms.
The efficiency of the proposed converter with different loads is shown in Fig.7. The maximum efficiency of 93.8% is achieved at the output power of 250W.
50 100 150 200 250 300 Output Power (W)
Efficiency (%)
96
94 92
90 88
860 350 400 500
Fig.7 Efficiency of the proposed converter.
V. CONCLUSION
The paper proposes a kind of high step-up dc/dc converter with a novel VMC. Theoretical analysis and experimental results show that: ① it consists of two switches, two inductors and one VMC network; ② the conversion gain has been improved greatly and also could be easily adjusted by the number of VMC; ③ Voltage stress of all semiconductor devices are reduced significantly compared to conventional boost converter, and the two inductor currents can be automatically self-balancing which provides easy control capability; ④ all capacitors have the same current stress except the two which are connected with the load, that is conducive to the thermal design.
REFERENCES
[1] W. H. Li, Fan L L, Zhao Y, et al.:‘High-step-up and high-efficiency fuel-cell power generation system with active-clamp flyback forward converter’, IEEE Transactions on Industry Electronics,
2012, 59, (1), pp. 599-610.
[2] Zhou L.-W., Zhu B.-X. Luo Q.-M.:‘High step-up converter with capacity of multiple input’, IET Power Electronics, 2012, 5, (5), pp. 524-531.
[3] C. T. Pan, C. F. Chuang, C. C. Chu.:‘A novel transformer-less adaptable voltage quadrupler DC converter with low switch voltage stress’, IEEE Transactions on Power Electronics,2014, 29, (9),
pp. 4787–4796.
[4] L. S. Yang, T. J. Liang, J. F. Chen.:‘Transformerless DC–DC converters with high step-up voltage gain’, IEEE Transactions on Industry Electronics, 2009, 56, (8), pp. 3144–3152.
[5] David Meneses, Frede Blaabjerg, Oscar Garcia, Jose A Cobos.:‘Review and Comparison of Step-Up Transformerless Topologies for Photovoltaic AC-Module Application’, IEEE Transactions on power electronics, 2013, 28, (6), pp. 2649-2663.
[6] W. H. Li, X. N. He.:‘Review of nonisolated high-step-up DC/DC converters in photovoltaic grid-connected applications’, IEEE Transactions on Power Electronics, 2011, 58, (4), pp.
1239–1250.
[7] S Y Tseng, C L Ou.:‘Interleaved coupled-inductor boost converter with boost type snubber for PV system’. Energy Conversion Congress and Exposition, Sept. 2009, pp. 1860-1867.
[8] W Rong Jong, D Rou Yong.:‘High-efficiency power conversion for low power fuel cell generation system’, IEEE Transactions on power electronics, 2005, 20, (4), pp. 847-856.
[9] W Li, X He.:‘An interleaved winding-coupled boost converter with passive lossless clamp circuits’, IEEE Transactions on power electronics, 2007, 22, (4), pp. 1499-1507.
[10] Gitau MN N, Kala-Konga C L.:‘Multilevel switched capacitor DC-DC converter with reduced capacitor bank’. IEEE 36th Annual Conference on Industrial Electronics Society, Nov. 2010, pp.
576-581.
[11] Seeman Michael D, Sanders Seth R.:‘Analysis and Optimization of Switched-Capacitor DC–DC Converters’, IEEE Transactions on power electronics, 2008, 23, (2), pp. 841-851.
[12]A. A. Fardoun, E. H. Ismail.:‘Ultra Step-up DC–DC converters with reduced switch stress’, IEEE Transactions on Industry Applications, 2010, 46, (5), pp. 2025–2034.
[13] Gang Wu, Xinbo Ruan, Zhihong Ye.:‘Nonisolated High Step-Up DC–DC Converters Adopting Switched-Capacitor Cell’, IEEE Transactions Industrial Electronics, 2015, 62, (1), pp. 383-393.
[14] Jang Yungtaek, Jovanović Milanm M.:‘Interleaved Boost Converter With Intrinsic Voltage-Doubler Characteristic for Universal-Line PFC Front End’, IEEE Transactions on power electronics, 2007, 22, (4), pp. 1394-1401.
[15] Prudente Marcos, Pfitscher Luciano Lopes, Emmendoerfer Gustavo, Romaneli Eduardo Félix Ribeiro, Gules Roger.:‘Voltage Multiplier Cells Applied to Non-Isolated DC–DC Converters’, IEEE Transactions on power electronics, 2008, 23, (2), pp. 871-887.
[16] Sanghyuk Lee, Pyosoo Kim, Sewan Choi.:‘High Step-Up Soft-Switched Converters Using Voltage Multiplier Cells’, IEEE Transactions on power electronics, 2013, 28(7), pp. 3379-3387.
[17] Zhou L.-W., Zhu B.-X., Luo Q.-M., Si Chen.:‘Interleaved non-isolated high step-up DC/DC converter based on the diode–capacitor multiplier’, IET Power Electronics, 2014, 7, (2), pp.
390-397.
