3-bit comparator2.pdf

3-BIT COMPARATOR DESIGN

Ding Chengwei 820116-A190 [email protected]

Niu Yuechao

[email protected]

Abstract-The objective of this project is to build a 3-bit comparator, which compares two numbers each

represented in 3 bits. The circuit produces 2 bits out: Q1 is active when A>B, Q1 is not active when A<B or A=B. Q2 is active when A=B, otherwise not active. Our approach is first to build up 1-bit comparator as one component and then connect three such kind of 1-bit comparator together. By applying the knowledge of CMOS and analyzing the logic behavior of the function, we can get the design with CMOS technology and run the simulation to check if it is correct.

I. INTRODUCTION

omparing two binary words for equality is a commonly used operation in computer systems and device interfaces. A circuit that compares two binary words and indicates whether they are equal is called a comparator. Here we need to design such kind of a comparator which compares the value of two 3-bit numbers and gives the output Q1 to 1 when the first number A is larger than the second number B, output Q2 to 1 when the two numbers are equal. Our method is to extend the 1-bit comparator to a 3-bit comparator by combine the logic relation between the 1-bit comparator outputs. Here we use Microwind to draw the layout of the CMOS circuit. Then we extract the spice file in Microwind and run under PSPICE to get the simulation result to verify if it works. This paper describe how to and the process of doing basic CMOS circuit design by applying the knowledge of K-Map optimization, CMOS circuit structure.

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II. 1-BIT COMPARATOR

Irst of all we need to design an 1 bit comparator. We can easily make such a component, 2 bits for input A and B, and 2 bits for output Q1 and Q2. Q1 is one when A is larger than B which means only when A is one and B is zero will set Q1 to one. And for the Q2, only when A and B both become one and zero will it be set. Here we can define

Q

as

F

′

1

Q

₁

= ⋅

A

B

Q

₂

B

A

B

A

Q

₂

=

⋅

+

⋅′

′

, as

Econd we draw the Karnaugh-map of 1-bit comparator and find the relationship between the input and the output.

S

B

A

Q

1

=

⋅

′

(when A>B)

Q

2

=

A

⋅

B

+

A

⋅′

B

′

(when A=B)

hen we can get the circuit structure and here is the logic diagram for the one bit comparator which is composed of two inverters, three two-input AND gates and one two-input or gate.

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This is the one bit comparator’s layout in Microwind.

III. 3-BIT COMPARATOR

three bit comparator is e o b ine three one-bit comparator

He asy t e implemented by comb

tog compon

ether. Here is the structure of the circuit in our design. We use three one-bit comparator ents, one two-input AND gate, two three-input AND gate and one three-input OR gate.

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Hat we have done is to use one AND gate to combine all the 1-bit comparator’s Q2 together.

Second,

s

sat ill 1 t e.

It could be easily understood only when all the bits of the three bit numbers are equal means that this two numbers have the same value. For the Q1 output, let’s consider there are two three-bit numbers,

A

₃

A

₂

A

₁ and

B

₃

B

₂

B

₁. There are three cases represent A is larger than B. First,

A

₃is

larger tha equals

B

₃ , but

A

₂ is larger than

B

₂ . The last one is w n

3

A

equals

B

₃

A

2equals , but

A

larger n

B

1. Anyone o ese three relations has been

isfied w set Q o one, so we use an OR gate her The layout of this circuit in Microwind is given like this.

n

B

₃ .

A

₃ he

and

B

₂ 1i tha f th

The simulation result in PSPICE verified this design and we put in here.

ropagation delay for Q2 (A=B) from Microwind (step=1ps) A3 256ps 176ps 225ps P A2 225ps 167ps 200ps A1 205ps 164ps 1201ps B3 1176ps 225ps 177ps B2 260ps 480ps 100ps B1 500ps 360ps 180ps Average 216.67ps

ropagation delay for Q1 (A>B) from Microwind (step=1ps) A3 116ps 150ps 154ps P A2 154ps 170ps 1106ps A1 162ps 159ps 1076ps B3 150ps 154ps 150ps B2 170ps 157ps 149ps B1 290ps 1160ps 250ps Average 169.0ps

he propagation delay of this circuit is about 216.67ps for Q2 (A=B) and 169.0ps for Q1 (A>B). T

IV. Conclusion

His paper has described how the S e used to construct the comparator by

Reference

[1] P. E. Allen , D.R. Holberg , CMOS ANALOG Circui nd Edition), chapter6,8 , Oxford Univ Pr,2002 ] William J. Dally and John W. Poulton: Digital Systems Engineering, Cambridge University Press 1998, pp519-521, 1998.

COM circuit can b

using the logic relation between different input and output nodes. We can use Karnaugh maps to minimize the representation of the functions. After that, we can use the logic units which composed with CMOS transistors to help us constructing the circuit. The PSPICE simulation results show our design has satisfied all the requirements. And also the propagation delay of this design is also within the consideration. By adding more 1-bit components into the circuit, we can easily make a larger size comparator. Of course, comparing with parallel inputs in our design, one way to save input pins is to do it in serious input with only two inputs which is beyond the scope of this paper.

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t Design (Seco [2