UNIT-1.pdf

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Class Work: 50

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Examination: 100

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Syllabus

Unit–1: architecture and machines: some definition and terms, interpretation and microprogramming. The instruction set, basic data types, instructions, addressing and memory. Virtual to real mapping. Basic instruction timing.

Unit–2: time, area and instruction sets: time, cost-area, technology state of the art, the economics of a processor project: A study, instruction sets, professor evaluation matrix

Unit-3: cache memory notion: basic notion, cache organization, cache data, adjusting the data for cache organization, write policies, strategies for line replacement at miss time, cache environment, other types of cache. Split I and d-caches, on chip caches, two level caches, write assembly cache, cache references per instruction, technology dependent cache considerations, virtual to real translation, overlapping the Tcycle in V-R translation, studies. Design summary.

Unit–4: memory system design: the physical memory, models of simple processor memory interaction, processor memory modeling using queuing theory, open, closed and mixed-queue models, waiting time, performance, and buffer size, review and selection of queueing models, processors with cache.

Unit–5: concurrent processors: vector processors, vector memory, multiple issue machines, comparing vector and multiple issue processors.

Shared memory multiprocessors: basic issues, partitioning, synchronization and coherency, type of shared memory multiprocessors, memory coherence in shared memory multiprocessors.

Text book:

Advance computer architecture by Hwang & Briggs, 1993, TMH

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Computer Architecture & Organization

Computer Architecture:

Those attributes of a system which are visible to a machine language programmer having direct impact on logical execution of a program.These attributes include Instruction set, word size, no of bits used to represent various data types, techniques of addressing memory etc.

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Computer Architecture & Organization (Contd..)

•Major Computer manufacturers offer a family of computer models based on same architecture but with different organization

•Various Intel CPU’s are based on same architecture but have different organization offering different levels of performance and price.

•IBM System 370 architecture introduced in 1970 has survived to this day as the architecture of IBM mainframe product line.

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Why Study Computer Organization & Arch.

•As a professional in field of computing one should not regard the computer as a black box that executes programs by magic

•As a professional in field of computing one should acquire some

understanding and appreciation of computer system’s functional components, their characteristics, their performance and their interactions.

•As a professional in field of computing one needs to understand computer architecture in order to structure a program so that it runs more efficiently on a real m/c.

•As a professional in field of computing one should understand how to select a computer system for your personal use or for your organizational use by

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Course Objective

The objective of this course is to provide a through discussion of fundamentals of computer organization and architecture. After doing this course you will be able to appreciate the following :-

•The Nature and characteristics of modern day computer systems. •Tremendous variety exists from single chip microprocessors to super computers. The various systems differ not only in costs but also in size, performance and applications.

•Impact of rapid pace of change covering all aspects of computer technology from underlying integrated ckt. Technology to increasing use of parallel

organization concepts in combining those components.

•Certain fundamental concepts that apply to all types of computers.

•All the basic performance characteristics of computer systems like processor speed, Memory speed, Memory capacity, and interconnection data rate are increasing rapidly but they are increasing at different rates. So designing a

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Computer Organization & Architecture

A computer is a complex system; Modern day computers contain millions of

elementary electronic components. The problem is how to clearly describe them all.

Recognizing the hierarchical nature of most complex systems , including computers we employ the top down approach and break a typical computer system into

interrelated subsystems, each of the latter , in turn hierarchical in structure until we reach some lowest level of elementary subsystem.

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Basic Functions of a Computer

The basic functions that a computer can perform are •Data Processing

•Data Movement •Data Storage •Control

Data Movement

Control

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Basic Components of a Computer

The basic components of a computer are

•CPU – Controls the operation of computers and performs its data processing functions.

•Main Memory – Storage of Data

•I/O Subsystem – Data Movement betn. Computer and its external environment.

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Basic Components of a Computer

Computer

CPU

System Interconnect

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Basic Components of a Computer

CPU

Control Unit Internal

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Basic Components of a Computer

Control Unit

Control Memory Control Unit

Registers & Decoders Sequencing

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Basic Components of a Computer

The basic functional units of a Computer consists of:

Control Unit:

It contains registers and decoding hardware required to interpret the current instruction ( In the Instruction Register). It controls the sequence of actions in the data paths to provide correct instruction execution.

Data Paths :

It consists of ALU ( Arithmetic Logical Unit), any other specialized execution unit (Floating Point Etc.), Address Generation

Hardware, data and address registers, and the inter connect between all these units.

Both these units are generally combined in one unit called CPU and in case of microprocessors its fabricated on single chip.

Memory :

The memory unit is another crucial piece of hardware. It

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Some Definitions and Terms

State:

It is a particular configuration of storage units like Registers or Memory, and a state transition is a change in that configuration.

Cycle:

It is the Time between state transitions. If storage registers are being reconfigured , its called Machine Cycle. If Memory is being reconfigured it is called Memory Cycle.

Command:

A term used to describe various Instructions, is responsible for affecting state changes.

Process:

It is a sequence of commands and an initial state. These sequence of commands apply to the initial state and generate a final state.

Machine:

The Implementation that interprets the commands and make the state transitions happen.

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Some Definitions and Terms (Contd.)

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The Machine: Interpretation &

Microprogramming

The Interpretation Process begins with the Instruction (Stored in the memory being Fetched or transferred to Instruction Register ) OP Code field being decoded by the Decoder.

OP CODE A B C

The Instruction

Decoder (A part of the implementation mechanism) controls the Data Paths

(which connects output of one register to input of other registers and vice versa ) consisting of combinational logic. Each OP Code defines which of the various data paths will be used in its Execution.

The Collection of all OP codes ( Instruction Set ) define all the Data Paths required by a specific Architecture.

The activation of a particular Data Path is done through a Control Point

activated and defined for each particular cycle of operation by the

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The Machine: Interpretation &

Microprogramming ( Contd…)

The Decoder activates Storage and Registers for a series of state transitions that correspond to the action of OP Code.

The Storage and Registers used in Instructions can be both Explicit and Implicit.

Explicit Registers Include:

• General Purpose Registers ( GPR ) •Accumulators (ACC)

•Address Registers ( Index or Base Registers ). Implicit Registers Include:

• PC (Program or Instruction Counter) – Contains address of next instruction in sequence. Most Instruction Formats Imply this to be current location plus the

length of current instruction.

•Instruction Register – This register holds the Instruction being interpreted or executed.

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The Machine: Interpretation &

•Storage Register-Also referred as memory buffer register is used to Read or

Write data to Memory.

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The Machine: Interpretation &

Microprogramming

Instruction Decoder

which has the responsibility of activation and defining of every control point in the processor for every cycle of operation can be

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The Machine: Interpretation &

Data Register

Destination Register A

Destination Register B

X X

Control Points

Decoder OP

Sequence Counter

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The Machine: Interpretation &

Microprogramming

Micro programmed Decoder

are designed using ROM. The OP Code provides an initial address to an entry which specifies the control point values as well as the address of the next micro instruction.

In Micro programmed machines the micro instruction defines the control

point values required throughout the system as well as controls the sequencing of the interpretation of a operation.

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The Machine: Interpretation &

Micro program Storage

OP

Additional Decode

C.P .S.

Micro MAR

Micro Instruction Register Next Micro

Instruction Address

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The Instruction Set

Instruction Sets define the many different kinds of data and their manipulations by different processors.

Since Instruction set details vary widely from processor to processor , three generic approaches are used to describe the different architecture types.

Consistent with most modern machines, each of these generic approaches are based on a register set to hold operands and addresses. These register sets vary from 8 to 32 words with each word consisting of 32 bits.

Additional sets of floating point registers and associated floating point execution hardware is assumed to be available whenever floating point arithmetic operations are available in the architecture. ( These can be

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The Instruction Set ( Contd..)

The major three Instruction Set Types are:

The L/S Architecture:

The L/S or Load Store architecture specifies that all operand values must be loaded from Memory into Registers before an

execution can take place.

OP

Reg Reg

Reg

An ALU ADD instruction

must have both Operands and

Result specified as Registers ( Three Address Format).

Operand in Memory is not allowed

Mostly used in RISC machines. RISC architecture tries to reduce the amount of complexity in the Instruction Set itself and regularize the instruction

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The Instruction Set ( Contd..)

The R/M Architecture:

The R/M or Register Memory architecture includes instructions that can operate both on registers and one operand in Memory.

OP

Reg Reg/Mem

Reg

An ALU ADD instruction one source operand lies in

Memory and the other source operand lies in Register

which also serves as Destination

Two address Format

Most general purpose modern mainframe computers like IBM, Hitachi,

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The Instruction Set ( Contd..)

The R+M Architecture:

The R+M or Register Plus Memory architecture includes instructions that can operate on operands both in registers and

Memory.

OP

Reg/Mem Reg/Mem

Reg/Mem

In an ALU ADD instruction all operand lie in Memory or in Registers or any combination there off.

Two address Format

(One source operand in Register or Memory is also the Destination)

Three address Format (Three operands

independently specified and each may be a register or Memory

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Basic Data Types

The most important aspect of an architecture is the format of

data values that are operated on by the Instruction Set.

The

Data Types

defines the format and use of data objects and

implies the operations that are valid for each type.

The different data types available on most machines can be

broken into following classes.

1. Integers

2. Floating Point ( Real ) Numbers

3. Decimal Digits

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Integers

are the fundamental data types used in computers.

Different formats may be used to represent signed numbers all of

which involve treating the most significant (left most) bit as sign

bit. The number is treated as negative if this bit is ‘1’.

•Sign – Magnitude Representation:

This is the simplest form of

representation where rightmost n-1 bits in an n bit number

represent the magnitude in binary format and left most bit

decides if the number is positive or negative.

S

16 b

32b

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Integers

(Contd..)

The most popular method of Integer Representation is called

Two’s Compliment representation:

Like Sign – Magnitude

representation, It also uses the most significant bit as sign bit

making it easier to see if a number is positive or negative. But

rest of the bits in a negative number are used as Two’s

compliment of the number’s magnitude.

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Integers

(Contd..)

Advantage of Two’s Compliment Representation is that

arithmetic can be handled in straight forward manner.

To subtract integer B from A we simply require to take the twos

compliment ( which can be easily done by inverting all the bits of

Integer B and adding 1 to it) of B and ADD it to A.

Additions of any two numbers ( Whether positive or negative ) is

also straight forward.

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Reals -Fixed Point Representation

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Reals –Floating Point Representation

Fixed Point Representation

has limitations and it can not be used

to represent

very large

numbers or

very small

fractions.

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Decimals

Decimal numbers are stored in two formats.

1. Packed Format: Two Digits per byte Binary Coded Decimals.

MSD ……. LSD SIGN

Length in Bytes Starting Address

Binary Coded Decimal Representation

0 0000 1 0001 2 0010 .

9 1001 + 1010 - 1011

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Decimals ( Contd ..)

2.Un Packed Format: One digit per byte in ASCII format.

0 0011 0000 1 0011 0001 .

+ 0010 1011 - 0010 1101 . 0010 1110

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Decimals ( Contd ..)

Advantages:

• Used in calculations performed by business applications

•No loss of Precision by data conversion.

Disadvantages:

•Not Natural for most machines to perform calculations

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Characters

The character strings may be used to represent decimal or text

information.

Character strings are simply a sequence of a variable number of

bytes.

The 256 representations available in a byte are defined by ASCII

standard format to represent various upper and lower case

letters, numerals and symbols.

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Bits

String of Bits ( Generally limited to word size) are used to

represent vectors of single bit elements, which may be tested and

changed mostly using logical instructions.

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Instructions

The Instruction set that defines all actions for all data types is

said to have the

Orthogonal Property

.

Most machines have

Instruction sets

to perform following

common core of operations.

•Integer Arithmetic

: add, subtract, multiply, divide

•Floating Point arithmetic

: add, subtract, multiply, divide,

square root

•Logical

: and, or, nor, xor, shift, rotate

•Bit manipulations

: extract, insert, test, set, clear

•Control Transfer

: jump, branch, trap

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Instructions (Contd..)

As per General Machine Conventions, Instruction mnemonics

consists of an operation and data type specification concatenated

with a “.”( If there is no explicit data type specification it is

assumed that data type is standard machine world.)

A similar format is used for branch conditions. In place of the

data type specification condition code is specified.

Data Type Specifications (OP.Modifiers)

B Byte

UB Unsigned Byte W word

F floating point

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Instructions (Contd..)

Branch Conditions

T True LE Less than or Equal F False LT Less Than

V Overflow EQ Equal C Carry or Borrow NE Not equal

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Instructions (Contd..)

Some Common Instructions:

ST

A, R1

Store the contents of Register R1 in Memory location A

ST.F A, R1

Store the contents of floating register R1 in Location A

MOVE A, B

Replace the Contents at location A with contents at Location B

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Instructions (Contd..)

Branch or Jump Instructions: These instructions determine program

control flow. Mainly two types

BR ( Unconditional Branch)

&

BC (Conditional Branch)

The BC tests the state of the condition code or CC ( Four Bits That reside in PSW and set by ALU Instructions)

Branch Conventions

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Register sets and Addressing Modes

•The simplest form of data addressing is accessing Registers.

•Some Processors use Numbered Registers while others use Named Registers •Some instructions use Implied Registers

•Some Processors define Register 0 ( R0) to have value ‘0’ stored in it.

Addressing Mode Summary

Mode Specification Explanation

Register RX Register X

Memory ADDR Address specified by ADDR

Indirect [RX] Address specified by contents of RX

Indexed OFFSET[RX] Address specified by OFFSET plus

contents of RX.

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Instruction Code Example:

The following code example implements a vector summation ( For an R/M Architecture).

Entry: LD.W R1, xCounter :Get x size from memory and load in R1 LD.W R2, xBaseAddress :Get the base value and load in R2

LD.W R3, #0 : Initialize Sum Register to zero Loop: ADD.W R3, [R2] : Add the next element

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Instructions (Contd..)

System States and Sequencing: Modern Instruction sets tend to

collect various pieces of control information into a single word called

Program Status Word

(PSW)

The

PSW

usually includes both user defined control information and

system information pertaining to a particular user.

User Defined Control Information

Include:

•Condition Code: defining whether the result of preceding

instruction was =0, >0, <0, or Overflow.

•Current Instruction address

•Current instruction Length

•Mask Bits to enable or disable floating point / fixed point /decimal

overflow

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Sequencing: Task to Task and Task to Supervisor

Three types of events may force program control to move from one

module to another.

•An Instruction that explicitly calls another module

•A-trap – unusual data condition that implicitly calls for operating system or service module

•An Interrupt – a concurrently executing process module or an external event that notifies the executing module of an event of mutual interest.

Control must pass from one module to another in an orderly

fashion and must return to original module when execution of

called module is complete. The Instruction sets provide for

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Addressing & Memory

Three levels of addressing:

1. The Process or User Program Level:

At this level the main concern is with efficient representation of user program statements.

2. The Operating System Level:

Multiple processes sharing a fixed address space. Issues include relocation and protection

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Addressing & Memory Contd..)

Operating System Level Addressing

• Modern computer systems require number of concurrently running programs ( User Process or System Process).

• Each process must be relocated and protected with respect to other processes .

• This is achieved by segmenting the overall address space into number of units (Segments) each having its own Base and Bound registers.

• Operating system process (Running into a segment) manages the collection of these registers called control registers.

• Upper bits of user process address are used to address a segment table ( In Memory or Registers) which has entries for base and bound.

• Base value added to lower bits of user process address gives the relocated address.

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Addressing & Memory Contd..)

Segment Bytes in Segment

Segment table

Base Bound #ID

+

CMP System Address User Process Address

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Addressing & Memory Contd..)

Virtual to Real Mapping

• A user programmer uses 32 bit virtual addresses.

• Depending on physical memory size available, these virtual addresses need to be mapped to real memory addresses.

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Addressing & Memory Contd..)

Segment number (12 bits) Page Number (8 Bits) Byte off set in Page ( 12 Bits)

32 bit

32 Bit User Virtual address

•Real memory is divided into page frames which are the same size as the virtual pages ( 4096 Bytes)

•When a page is needed during the running of a program, it is copied into a page frame in real memory.

•The process of moving program pages to and from real memory is called

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Addressing & Memory Contd..)

Virtual to Real Mapping

• Any page can go into any page frame.

• The memory management process translates a 32-bit virtual address into a 24-bit physical address. (16 MB Real Memory)

• This is done with the aid of a page table.

• The segment table base plus the 8 bit page offset of a page with in a segment defines an entry into page table associated with that particular segment.

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Addressing & Memory Contd..)

User ID Segment No. Page No. Offset in Page

ADDER

Segment table

ADDER

Page Table

Frame Number Offset in Frame

TLB

Virtual Address

Physical Address

12 Bit

8 Bit

12 Bit 12 Bit

32 Bit

Segment Table Entry

Segment Table Base

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Addressing & Memory Contd..)

0 1 0 2 3 4 4 4 Frame Number Page No.

0001 0101 0000 0001 0000 1010 1010 1011

16 1011 1011 1011

Valid Bit

1011 1011 1011 1010 1010 1011 Virtual Address #15010AAB

Physical; Address #BBB AAB

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Basic Instruction Timing

A simple machine normally consists of following functional units. • Cache

• Memory • ALU

• Address Generation Unit • TLB

• Instruction decoder

These units are accessed or employed for execution of an instruction . Access to different units occupies one or more cycles. The sequence of events

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Basic Instruction Timing

The Process of instruction execution for simple machines that executes instructions serially ( called well mapped machines), consists of following events and sub events.

•Instruction Fetch

•Generate real address from value stored in PC to access the instruction. •Access the cache

•Access Memory if cache miss occurs

•Move the word (instruction) fetched from cache / memory ( Available in SR Register) to the IR (Instruction Register).

•Instruction Decode

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Basic Instruction Timing

•Data Fetch

•Generate real address for data ( Offset +Base / Index ) •Access the cache

•Access Memory if cache miss occurs. •Execute

•Use ALU to perform required operation on data. ( Available in SR and other Registers)

•Update Registers

•Adjust PC to point to next instruction

•Store results of ALU operation in registers.

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