Abstract— Genetic algorithm (GA) is a design technique that
synthesizes an application specific Network-on-chip (NoC) topology and routes the communication traces on the interconnection network. Network-on-chip (NoC) is a new paradigm for designing scalable communication architecture for SoC (system on chip). In this paper Genetic algorithm (GA) is proposed as a reliable and efficient technique for large NoC. It is based on automated design technique that synthesizes an application specific NoC topology and routes the communication traces on the interconnection network. Initially NoC routers are implemented based on GA (genetic algorithm) optimization algorithm. Critical path analysis is performed initially in router architecture inorder to determine shortest path. As a result effective shortest path with less number of nodes is identified. Then fault analysis process is carried out in the obtained shortest path. As a result, a net fault free routing path is obtained. Genetic algorithm provides optimum mapping in NoC architecture and measures faulty blocks during run time more effectively. Experimental results show that test sets generated using the evolutionary approach are more compact and very effective than those generated by earlier approaches for many circuits. The design technique solves a multi-objective problem of reduction in power, area, latency and delay
.
Index Terms— Genetic Algorithm, Network-On-Chip,
critical and fault analysis.
I. INTRODUCTION
SoC (system-on-chip) is design architecture which consists of hundreds of processing and memory elements and is implemented in nano scale technologies. Communication architecture will be a key determinant of the overall performance of these architectures. Thus Network-on-chip (NoC) has emerged as the dominant solution for the interconnection architecture design problems of SoC design. This paper addresses the design of a NoC in SoC architecture. In starting stage communication between processor elements is done using dedicated wires or shared busses. As SoC grows in size, communication medium becomes a major issue.
Manuscript received June 15, 201`4.
N.Ramalakshmi, PG scholar, Department of Electronics and Communication Engineering, Ultra College of Engineering and Technology, Madurai., ([email protected])
N.Hemalatha, Assistant Professor, Department of Electronics and Communication Engineering, Ultra College of Engineering and Technology, Madurai., ([email protected])
Thus NoC, a new design methodology results in increase in performance over conventional bus system. Conventional NoC architecture is limited by long latency and high power consumption, which can be solved by GA optimization algorithm. The path for a data packet between a source and a destination through the routers is defined by the routing algorithm. Thus genetic algorithm (GA) an optimization algorithm is applied locally in each router being crossed and to each data packet. Dynamic based NoC router architecture is used where localization of error sources is obtained without affecting NoC’s throughput and network load. Critical path analysis is performed initially in router architecture inorder to determine shortest path. As a result effective shortest path with less number of nodes is identified. Then fault analysis process is carried out in the obtained shortest path. As a result, a net fault free routing path is obtained. Genetic algorithm provides optimum mapping in NoC architecture and measures faulty blocks during run time more effectively. This shows that GA (genetic algorithm) has been very effective for benchmark circuit test generation.
A. Overview of the project
This new method of GA-based optimization technique solves a multi-objective problem that addresses NoC power consumption and interconnection resources. The GA-based technique has the ability to escape local minima and generate excellent quality solutions in reasonable time. Further, the GA-based technique can generate a set of Pareto points where each point represents a solution with a certain power and router resource consumption. The node points provide the designer with an option to choose a solution corresponding to the desired trade-off between power and router resource consumption.
Two simulation processes is carried out in this paper: critical path analysis and fault analysis process. In critical path analysis two processing stage is present: creating a router architecture and implementation of GA optimization algorithm. This results in identification of routing path from source to destination and creating a node with limited number of routers for further transmission. In fault analysis process, obtained routing path is verified for fault. Thus resultant fault free routing path is obtained and is used for further transmission.
B. Network-on-chip (NoC) topology design
Network on chip (NoC ) is a communication subsystem on an integrated circuit (commonly called a "chip"), typically between IP cores in a system on a chip (SoC). Network on
A Study on Network-On-Chip architecture using
Genetic Algorithm
chip is a new paradigm for communications within large VLSI systems implemented on a single silicon chip. Figure1 shows a simple NoC system, designed by processing elements and routers. Depending on type of conventional algorithm used, router works through it. This NoC architecture is the basic building block in VLSI design methodology. Network on chip (NoC) has emerged as the design paradigm for design of scalable on-chip communication architectures, providing better structure and modularity. SoC architecture with NoC is viewed as a collection of computational resources connected through a network where they communicate using data’s.
Figure1: Simple NoC architecture
C. Overview of genetic algorithm (GA)
Genetic algorithm (GA) is a search heuristic that mimics the process of natural selection. This heuristic (also sometimes called a metaheuristic) is routinely used to
generate useful solutions to
optimization and search problems. Genetic algorithms belong to the larger class of evolutionary algorithms (EA), which generate solutions to optimization problems using techniques inspired by natural evolution, such as selection, crossover, mutation and fitness.
Figure2 shows the working process in GA in order to obtain random generation of new effective population, so that it can be used for further process:
1. Start with a randomly generated population of n l-bit strings (candidate solutions to a problem)
2. Calculate the fitness f(x) of each string in the population.
3. Repeat the following steps until n new strings have been created:
Select a pair of parent strings from the current population. Selection is done "with replacement" meaning that the same string can be selected more than once to become a parent.
With the crossover probability, cross over the pair at a randomly chosen point to form two new strings. If no crossover takes place, form two new strings that are exact copies of their respective parents.
Mutate the two new strings at each locus with the mutation probability, and place the resulting strings in the new population.
4. Replace the current population with the new population.
5. Go to step 2.
Figure2: Flow diagram of GA
D. Function of Router
Figure3: Single router function and its model diagram
In GA based NoC, router plays a vital role where overall system process takes place. In this paper, by designing a single router and defining its function, multiple routers (16 routers) is designed and processed. Mesh and star based router topology architecture is used in this process. Mesh router is used for critical path analysis and star router topology is used for fault analysis process. Figure4 shows some example diagram of how routers are implemented in mesh and star topology. Mesh topology router provides easy identification of shortest path along the NoC router and star topology router results in identification o faulty and fault free router along the identified path.
Figure4: Example diagram of (a) mesh based router (b) star based router
II. EXISTINGSYSTEMANALYSIS
A. Introduction
` As modern computing systems become increasingly complex, communication efficiency among and inside chips has become as important as the computation speeds of individual processing cores. Traditionally, to maximize design flexibility, interchip and intrachip communication architectures are separately designed under different constraints. Jointly designing communication architectures for both interchip and intrachip communication could,
however, potentially yield better solutions. In this paper, we present a unified inter/intrachip optical network, called chip multiprocessors (CMPs). CMPs are based on recent progresses in nanophotonic technologies. It connects notonly cores on a single CMP, but also multiple CMPs in a system.It employs a hierarchical optical network to separate interchip communication traffic from intrachip communicationtraffic. It fully utilizes a single optical network to transmit both payload and control packets. The network controller on each CMP not only manages intrachip communications, but also collaborates with each other to facilitate interchip communications.
B. Overview of adaptive algorithm in NoC
We propose a new reliable NoC-based communication approach based on adaptive algorithm. It is a packet switched network based on intelligent independent reliable routers. The PEs and IPs can be connected directly to any side of a router. Therefore, there is no specific connection port for a PE or IP. The proposed detection mechanisms can also be applied to NoCs using five port routers with a local port dedicated to an IP. However, the major drawback of these architectures is when the local port has a permanent error and the IP connected to it is lost or needs to be dynamically moved in the chip because of the dynamic partial reconfiguration. Moreover, dynamic partial reconfiguration of IPs is strongly connected in the NoC. Indeed, an IP may have access to the network by being connected to several routers, or can be dynamically moved on the chip if this only access point becomes faulty. Each port direction is composed of two unidirectional data buses (input and output ports). Each input port is associated to a first-input, first-output (FIFO) (buffers) and a routing logic block. The adaptive algorithm operation is based on the store-and-forward switching technique.
C. Process involved in Adaptive algorithm
An adaptive algorithm is an algorithm that changes its behavior based on information available at the time it is run. This might be information about computational resources available, or the history of data recently received. This adaptive algorithm is based on XY-routing algorithm whose function is to identify routing path from source to destination in rapid manner. Main difference between adaptive and XY-routing algorithm is, adaptive algorithm changes or adjusts its behavior based on the information available during run time and in XY-routing algorithm, after transmission of data/packet, it compares its own address to source and destination.
Figure5: (a) Normal router implementation (b) possible routing path. (c) Online detection of a faulty router node.
Figure5shows the communications between several IPs and (b) and (c) depicts the dynamic placement of an IP and the occurrence of a faulty node, respectively, both cases where bypasses determined by the dynamic routing algorithm are required. Furthermore, faulty nodes or even faulty regions make communications within the networks harder and even impossible with some routing algorithms, as shown in (c). Therefore, dynamic component placement and faulty nodes or regions are the main reasons why fault-tolerant or adaptive algorithms have been introduced and used in runtime dynamic NoCs. The above diagram shows example of implementation of router architecture based on adaptive algorithm. Even though this process seems to be effective, its main drawback is it consumes more time for processing the whole network. This adaptive algorithm is based on XY-routing algorithm where process takes place only in two directions. To overcome this adaptive algorithm is implemented.
Table I: Tool consumption of processing adaptive algorithm
Table I shows the amount of devices used for processing. Simulation refers to the verification of a design, its function and performance. It is the process of applying stimuli to a model over time and producing corresponding responses from a model. The simulation is performed in XILINX ISE 10.1 software. A test bench is also written to test the routing pattern from various data packets. Table II presents a comparison among state-of-the-art solutions and our approach, which shows clear benefits regarding area overhead reduction, timing performance improvements and enhancements of reconfiguration features.
Table II: Area overhead, timing performance and features comparison among state of the art solutions and the proposed
approach
D. Drawbacks
This conventional architecture overcomes many disadvantage of existing approach of XY-routing algorithm such as determining errorless data and data path identification. It also includes the process of data packet error detection and correction. The originality of the existing architecture is its ability to localize accurately error sources, allowing the throughput and network load of the NOC to be maintained. This algorithm is live lock and deadlock-free and allows data packets to pass around faulty regions. Performance of fault analysis operation (i.e. reason of analysing of fault occurrence and identification o fault module) is much low for NoC router operation.
Main drawback in adaptive algorithm is it generates permanent and transient faults (i.e. fault is no longer present if power is disconnected for a short time and then restored). This fault generates data packet error and even affects router behaviour. The main drawback of the solution is the necessity to invoke the algorithm at a non-specified time in order to apprise the routing tables of the NoC routers.
III. PROPOSEDSYSTEMANALYSIS
A. Introduction
The application specific network topology generation problem is a variation of the generalized Steiner forest problem, which is known to be NP hard. A survey of existing approaches that address application specific NoC design. Existing techniques for NoC design with irregular topologies have largely ignored the length constraints posed by physical links and also their contribution to the overall power consumption of the interconnection architecture.
B. Overview of GA in NoC
option to choose a solution corresponding to the desired trade-off between power and router resource consumption. We demonstrate the quality of results produced by our technique by experimenting with several benchmark designs and comparisons with existing approaches.
As a first step, GA technique allocates routers at physical locations in the NoC. The selection of the router locations should reduce the design space of the GA, and thus its runtime. The possible router locations are assumed to be at the corners of the computation cores. As the possible physical locations of the routers are known, we can determine the shortest distance from any node to the routers. By the same argument, we can also determine all inter-router distances. Therefore, we can estimate the link lengths (and resulting link power consumption) in the NoC with a high degree of confidence.
Next step in GA-based automated design technique selects the routers to be utilized in the NoC, maps the nodes to router ports, constructs the topology of the network, and routes the traffic traces on the interconnection architecture. During topology generation, the physical dimensions of the routers were neglected. We address deadlock avoidance during NoC generation phase, as well as a post processing step. Our static routing algorithm utilizes the knowledge of the underlying router architecture to generate deadlock avoiding routes.
GA maintains a set of solutions known as the population or a generation. GA operates in an iterative manner and evolves a new generation from the current generation by application of genetic operators. A new generation is created by first increasing the population by generating new individual solutions, and then selecting a constant number of solutions based on their fitness criteria. The fitness criterion is a cost function that captures the optimization goal.
Figure 6: (a) router allocation (b) GA based topology generation (c) router generation
C. System Architecture
In system architecture overall implementation of NoC architecture using GA is implemented. Process starts with initializing data to routing process. Based on single router function defined multiple router architecture is designed. Main advantage of this router architecture is its arrangement based on mesh structure. Once router structure is implemented, next comes implementation of genetic algorithm. This process results in effective output of obtaining destination path and processing fault analysis.
Figure7: Class diagram
Figure8: Sequence diagram
D. Module description Router
Genetic algorithm Critical path analysis Fault analysis
Router
important section in NOC chip architecture and the routers are connected to the mesh topology connection.
Figure9: NoC Router architecture
Above architecture includes five input/output ports, four of them connect the switch to its neighbouring router node in the mesh and one connects the switch to its corresponding processor. In above figure I/O ports are specified by first letter of their direction. It is simple router architecture; in which corresponding routing algorithm can be applied for further processing to produce efficient output.
Genetic algorithm description
In a genetic algorithm, a population of candidate solutions (called individuals, creatures, or phenotypes) to an optimization problem is evolved toward better solutions. Each candidate solution has a set of properties (its chromosomes or genotype) which can be mutated and altered; traditionally, solutions are represented in binary as strings of 0s and 1s, but other encodings are also possible.
The evolution usually starts from a population of randomly generated individuals, followed with iterative process, resulting in population, called a generation. In each generation, the fitness of every individual in the population is evaluated; the fitness is usually the value of the objective function in the optimization problem being solved. The more fit individuals are stochastically selected from the current population, and each individual's genome is modified (recombined and possibly randomly mutated) to form a new generation. The new generation of candidate solutions is then used in the next iteration of the algorithm. Commonly, the algorithm terminates when either a maximum number of generations has been produced, or a satisfactory fitness level has been reached for the population.
A typical genetic algorithm requires:
1. A genetic representation of the solution domain,
2. A fitness function to evaluate the solution domain.
A standard representation of each candidate solution is as an array of bits. Arrays of other types and structures can be used in essentially the same way. The main property that makes these genetic representations convenient is that their parts are easily aligned due to their fixed size, which facilitates simple crossover operations. Variable length representations may also be used, but crossover
implementation is more complex in this case. Tree-like representations are explored in genetic programming and graph-form representations are explored in evolutionary programming; a mix of both linear chromosomes and trees is explored in gene expression programming. Once the genetic representation and the fitness function are defined, a GA proceeds to initialize a population of solutions and then to improve it through repetitive application of the mutation, crossover, inversion and selection operators.
Merits
Provide better fault coverage than deterministic algorithm.
It can be applied to generate test patterns for complex combinational circuits.
Provides increase in system performance with reduced delay.
Applications
Satellite communication providing wireless communication.
Communication network that interconnects terminals for telecommunication.
Multi-core processor system.
Aircraft design that specifically targets network domain.
Wind shear which finds difference in wind speed and direction over shortest distance in atmosphere.
Figure10: GA based NoC architecture
Initialization Operation
successive generation, a proportion of the existing population is selected to breed a new generation. Individual solutions are selected through a fitness-based process, where fitter solutions (as measured by a fitness function) are typically more likely to be selected. Certain selection methods rate the fitness of each solution and preferentially select the best solutions. Other methods rate only a random sample of the population, as the former process may be very time-consuming.
Crossover Operation
In genetic algorithms, crossover is a genetic operator used to vary the programming of a chromosome or chromosomes from one generation to the next. It is analogous to reproduction and biological crossover, upon which genetic algorithms are based. Cross over is a process of taking more than one parent solutions and producing a child solution from them. There are methods for selection of the chromosomes. The crossover operator selects two solutions or parents from the previous generation and produces two new solutions or children. In this section, we discuss the crossover operation of strings at the trace, node, and router levels.
Figure 11: Crossover operation
Mutation Operation
Mutation is a genetic operator used to maintain genetic diversity from one generation of a population of genetic algorithm chromosomes to the next. It is analogous to biological mutation. Mutation alters one or more gene values in a chromosome from its initial state. In mutation, the solution may change entirely from the previous solution. Hence GA can come to better solution by using mutation. Mutation occurs during evolution according to a user-definable mutation probability. This probability should be set low. If it is set too high, the search will turn into a primitive random search. The classic example of a mutation operator involves a probability that an arbitrary bit in a genetic sequence will be changed from its original state. A common method of implementing the mutation operator involves generating a random variable for each bit in a sequence. This random variable tells whether or not a particular bit will be modified. This mutation procedure, based on the biological point mutation, is called single point mutation. Other types are inversion and floating point mutation. When the gene encoding is restrictive as in permutation problems, mutations are swaps, inversions and scrambles.
The purpose of mutation in GAs is preserving and introducing diversity. Mutation should allow the algorithm to avoid local minima by preventing the population of chromosomes from becoming too similar to each other, thus slowing or even stopping evolution. This reasoning also
explains the fact that most GA systems avoid only taking the fittest of the population in generating the next but rather a random (or semi-random) selection with a weighting toward those that are fitter.
The router level mutation operation is applied to every set of router allocations to generate new individuals. The router level mutation is applied to every router allocation in the current generation. As mentioned before, the router allocation is specified by an array of binary digits. Router level mutation is applied by the selection of a random location in the array, and the inversion of the corresponding bit. If a “0” is inverted to “1” a router is added and no change is applied to the lower levels. On the other hand, if a “1” is inverted to “0” a router is removed. Hence, all node level mappings that contain any ports belonging to the removed router and associated communication traces are regenerated similar to the initial population creation.
Figure 12: Mutation operation
Fitness Operation
Figure13: fitness operation
E. Critical path analysis
The critical path analysis section process is the main parameter for the NOC chip architecture for the wireless communication process. The path information is mainly used to find the shortest path for source to the destination section in the transmission time. This method used to very fast data transmission source to the destination and to reduce the path delay and increase the speed for NOC process. The critical path section to find the path allegation level in shortest path compare to the critical path.
F. Fault analysis
The fault analysis process is to identify the damaged routers in the NOC chip architecture and to reject the path for required damaged router. The damaged router is to block the input bit data for the transmission process and to modify the routers arrangement in NOC. By fault analysis process each routers are individually verified for fault. In case of presence of fault in router path for required damaged router is rejected and retransmitted and router arrangement in NoC is modified. The router faults identification process mainly used to missing the input data bits from source to destination section. In fault analysis process verification for fault present in each router in the determined shortest path is performed. This design technique solves multi objective problems as compared to existing work such as reduced transmission time, power, area, latency and delay.
Figure 14: block diagram of proposed methodology
Figure14 explains the working of fault analysis. When each router is tested individually in acts as master and remaining routers acts as slave. By this way each router saves information about transmission path and destination path and is overall controlled by NI (network interface) and switches. Network interface is a system's (software and/or hardware) interface between two pieces of equipment or protocol layers in a computer network. It has network address in which node information's are stored. Network interfaces provide standardized functions such as passing messages, connecting and disconnecting, etc. Network switch connects all devices together and manages the flow of data across the network. If data passes though the router (i.e, data passing through router is 1or 0) then the router is fault free and if data passes through router and if any undefined symbol arises other than 1or0 , then presence of fault is identified and data is retransmitted to next router. By this procedure fault analysis process is carried out.
Table III output comparison table of existing and proposed system
G. ALGORITHM DESCRIPTION Introduction
the search into the region of better performance within the search space. It is better than conventional AI in that it is more robust. Unlike older AI systems, they do not break easily even if the inputs changed slightly, or in the presence of reasonable noise.
Genetic algorithm
A GA is based on the biological phenomenon of genetic evolution. It maintains a set of solutions known as the population or a generation. GA operates in an iterative manner and evolves a new generation from the current generation by application of genetic operators. A new generation is created by first increasing the population by generating new individual solutions, and then selecting a constant number of solutions based on their fitness criteria. The fitness criteria are a cost function that captures the optimization goal. The selection of solutions based on their fitness criteria models the evolutionary behaviour known as the survival of the fittest. A GA-based technique typically applies three operators namely reproduction, crossover, and mutation to produce new members. Reproduction duplicates a solution across generations; crossover combines two solutions to generate two new solutions, and mutation modifies an existing solution to generate one new solution. The algorithm continues to operate in an iterative manner until the termination condition is reached.
A typical genetic algorithm requires:
1. a genetic representation of the solution domain,
2. a fitness function to evaluate the solution domain. Algorithm for GA
As a special kind of stochastic search algorithms, genetic algorithm is a problem solving method which is based on the concept of natural selection and genetics. In the 1970s, Holland first introduced genetic algorithms to explain the adaptive processes of natural systems and to design an artificial system, which retains the robust mechanism of natural systems.
Flow diagram of GA
Flow diagram shows the top level flowchart of our GA-based optimization technique. Our technique applies genetic operators at the three levels of solution hierarchy with different probabilities. For each genetic operation at a higher level of hierarchy, the GA explores several operations at the lower levels. This approach aids in a structured design space exploration for the problem. At each level the number of solutions produced by crossover is much larger than those produced by mutation. At each hierarchical level new individual solutions are produced by the application of the genetic operators. A new generation is produced by selection of the fittest members among the current generation and the new individual solutions
Figure15: Flow diagram of GA
Key terms for GA
Initialization: Initially many individual solutions are randomly generated to form an initial population. The population size depends on the nature of the problem, but typically contains several hundreds or thousands of possible solutions. Traditionally, the population is generated randomly, covering the entire range of possible solutions.
Crossover: is a process of taking more than one parent solutions and producing a child solution from them
Mutation: Mutation is a genetic operator used to maintain genetic diversity from one generation of a population of genetic algorithm chromosomes to the next.
Fitness Operation: Fitness is an important concept in genetic algorithms. The fitness of a chromosome determines how likely it is that it will reproduce. Fitness is usually measured in terms of how well the chromosome solves some goal problem
Algorithm 1: Choose initial population
4: Select best-ranking individuals to reproduce
5: Breed new generation through crossover and mutation (Genetic operations) and give birth to offspring
6: Evaluate the individual fitnesses of the offspring 7: Replace worst ranked part of population with offspring 8: end while
H. Advantages
Genetic algorithm is applied for solving the problem of faulty module prediction.
GA is also finds the most important attribute for fault occurrence.
The system finding the most important attributes for fault prediction and calculate the critical path and find the shortest path.
The results are measured in terms of Accuracy and Error in predicting by calculating probability of error detection.
The designer can specify a maximum length of the physical link that permits the single clock cycle data transfer.
IV. SIMULATEDOUTPUT
A. CRITICAL PATH ANALYSIS OUTPUT
Routing destination path
Node generation
B. FAULT ANALYSIS OUTPUT
C. RTL SCHEMATIC DIAGRAM
E. POWER CALCULATION
STATIC POWER
TOTAL ON-CHIP POWER
POWER = (TOTAL ON CHIP POWER) – (STATIC POWER)
= (0.095) – (0.091) = (0.004) W
V. PERFORMANCECHART
ON-CHIP Vs TYPICAL POWER
ON-CHIP DEVICE Vs POWER
VI. CONCLUSION
In this paper, genetic algorithm (GA) a metaheuristic technique is implemented in network-on-chip (NoC) router architecture. Integration of NoC design techniques with the computation architecture design stage is achieved. Thus effective identification of router path, path node based on fitness function and performance of fault analysis in NoC based on GA is obtained. Through this further processing in overall system is performed. This algorithm is used in all kind of routing architecture, which is now widely used in VLSI design process.
The paper is compared to existing technique. While existing system based on adaptive algorithm NoC suffer from high runtime and low performance solution quality respectively, which can be overcome by GA. Performance of fault analysis operation based on adaptive algorithm is low since it creates permanent and transient errors which does not arises in this GA based NoC architecture. Performance of NoC using GA is calculated where, optimal solutions with respect to area, delay, time, speed and latency is obtained by simulation process and is tabulated.
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