35
Copyright © 2016. Vandana Publications. All Rights Reserved.
Volume-6, Issue-6, November-December 2016
International Journal of Engineering and Management Research
Page Number: 35-40
Implementation of Fast Fourier Transform in Verilog
Anup Tiwari1, Samir Pandey2
1
Assistant Professor, ECE Department, Jharkhand Rai University,Ranchi, Jharkhand, INDIA
2
Assistant Professor, Mathematics Dept, XIPT, Ranchi, Jharkhand, INDIA
ABSTRACT
The use of FFT is very efficient and vast in the field of Digital signal Processing and Communication. The Discrete Fourier Transform(DFT)can be implemented very fast using Fast Fourier Transform(FFT). It is one of the finest operations in the area of digital signal and image processing. FFT is a luxurious operation in terms of DSP and Communication. To achieve FFT calculation with a many points and with maximum number of samples requirement could not be matched by efficient hardware’s like DSP. So a fine solution is to use dedicated hardware processor to perform efficient FFT working out at high sample rate, while the DSP could perform the less
concentrated parts of the processing. Verilog
implementation of floating point FFT with reduced generation logic is the proposed architecture, where the two inputs and two outputs of any butterfly can be exchangedence all data and addresses in FFT dispensation can be reordered.
Keywords---FFT, DSP, DFT
I.
INTRODUCTION
The fast and efficient computation for the purpose of reducing the hardware requirements has always been the field of interest of the designer. In this report, an efficient algorithm for the computation of fast fourier transform has been presented which requires less computations producing the same results.
In 1965, Cooley and Tucky developed very efficient algorithm to implement the discrete Fourier transform of a signal. This algorithm is called the Fast Fourier Transform (FFT). This FFT algorithm is very efficient in terms of computations of DFT. By using these algorithm, number of arithmetic operations involved in the computation of DFT is greatly reduced. According to the definition of DFT,
X(k) = ∑ ( ) -jkn
The need for high-speed data communication has been increased with the fast development of digital communication in modern years. The mobile telecommunications industries faces the difficulty of providing
the technology that be able to support a variety of services ranging from a few kbps bit rate in voice communication up to 2 Mbps bit rate in wireless multimedia. Many systems have been proposed and FFT system has gained much attention for different reasons. Although DFT (Discrete Fourier Transform) was first developed in the 1960s, only in modern time, it has been accepted as an exceptional technique for high-speed cellular data communication where its execution relies on very high-speed digital signal processing. This technique has only just happened to available with good performance of hardware implementation with reasonable prices.
II.
FAST FOURIER TRANSFORM
Before going further to discus on the FFT design, it is good to explain a bit on the FFT and IFFT process. The Inverse Fast Fourier Transform (IFFT) and Fast Fourier Transform (FFT) are derived from the major function which is known as Discrete Fourier Transform (DFT). The thought of using FFT instead of DFT is that the calculation of the function can be made quicker where this is the major criteria for implementation in the digital signal processing. In DFT the calculation for N-point of the DFT will compute one by one for each point. While for FFT, the calculation is done at the same time and this technique saves very much of time. Below is the equation showing the DFT and from here the equation is derived to get FFT function.
The number of complex multiplication and addition operations required by the uncomplicated forms both the DFT is of order N2 as there are N data points to calculate, every one of which needs N complex arithmetic operations. The DFT on a signal with n elements is given as:
fj =∑ ke -(j2πnk/N)
j = 0,1,2….., n-1
36
Copyright © 2016. Vandana Publications. All Rights Reserved.
Figure: Radix 2 Decimation in time FFT Algorithm for a length 8 signalThe radix-2 decimation-in-frequency algorithm:
The radix-2 decimation in frequency algorithm rearranges the Discrete Fourier transform (DFT) equation into two parts : calculation of even numbered discrete frequency
indices X(k) for k = [0,2,4,…., N-2] or X(2r) and computation of the odd numbered indices k = [1,3,5,7,…., N-1] (or X(2r +1).
X(2r) = ∑
(n)W2nrN
= ∑ (n)W2nrN + ∑
(n+ )W2r(n+N/2)N
= ∑ ( (n)+ (n++ )WnrN/2
=DFTN/2[x(n)+x(n+ )]
X(2r+1) = ∑
(n) W(2r+1)nN
= ∑ ( (n)+WN/2N x(n+ ))W(2r+1)nN
= ∑ (( (n)−x(n+ ))WnN)WrnN/2
= DFTN/2[(x(n)−x(n+ ))WnN]
The Radix 4 Algorithm:
The radix-4 time and decimation-in-frequency fast Fourier transforms (FFTs) increase their pace by
reusing the outcome of smaller, middle calculations to calculate numerous DFT frequency outputs.
X(k) =∑ (n)e−(j2πnk/N)
= ∑
(4n)e−(i2π×(4n)k/N) +∑ (4n+1)e−(j2π(4n+1)k/N
= ∑ (4n)e−(j2π×(4n)k/N) + ∑ (4n+1)e−(j2π(4n+1)k/N) + ∑ (4n+2)e−(j2π(4n+2)k/N) + ∑ (4n+3)e−(j2π(4n+3)k/N) = DFTN/4[x(4n)]+WkNDFTN/4[x(4n+1)]+W2kNDFTN/4[x(4n+2)]+W3kNDFTN/4[x(4n+3)]
III.
INTRODUCTION TO FPGA
DESIGN
Field Programmable Gate Arrays are called this as rather than having a structure same to a PAL or other programmable device, they are arranged very much similar to gate array ASIC. This makes FPGAs very good for application in prototyping ASICs, or in places where ASIC will finally be used. For illustration, an FPGA may be used in designs that need to get to market place fast in spite of price. Afterward an
ASIC can be used in place of the FPGA when the manufacture amount increases, in order to decrease price.
IV.
SYSTEM IMPLEMENTATION
37
Copyright © 2016. Vandana Publications. All Rights Reserved.
execute the design. As we know that, the FFT transmitterconsists of some modules or block to realize the system using the FFT function. After consulting various journal, books, and white paper, the planned transmitter design is consist of processing block, modulator bank, serial to parallel converter, parallel to serial converter and cyclic prefix block module. This module block diagram is close to the standard for all FFT systems. It was in close accordance with the systems described
in the primary textbooks. These sources and some technical papers, served as helpful tools to authenticate our design.
V.
PRESENT WORK
From the definition of DFT of size N:
X(k) = ∑ (n)WNnk , 0 < k < N
where WN denotes the primitive Nth root of unity, with its
exponent evaluated modulo N, x(n) is the input sequence and
X(k) is the Discrete Fourier Transform. A 3-dimensional linear index map was applied,
n = {( )n1 + ( )n2 + n3}N k = {k1 + k2 + 4k3} and to derive a set of 4 DFTs of length N/4 CFA (Common
factor algorithm) was used as,
X(K1 + 2k2 + 4k3) = ∑ H(k1,k2,n3)WN n3 (k1+2k2)] WN/4 n3k3
where n1,n2,n3 are the index terms of the input sample n and
k1,k2,k3 are the index terms of the output sample k and where H(k1,k2,k3) is expressed in equation below.
H(k1 , k2 ,n3) = [ x(n3) + (-1)k1 x(n3 + )] + (-j)(k1+2k2)[ x(n3 + ) + (-1)k1x(n3 + )
X(K1+2k2+4k3) = ∑ H(k1,k2,n3)WN n3(k1+2k2)
] WN/4 n3k3
So,
X(K1+2k2+4k3)=∑
x(n3)+(-1)k1x(n3+N/2)]+(-j)(k1+2k2)[ x(n3+N/4)+(-1)k1x(n3 +3N/4)] WNn3(k1+2k2)] WN/4n3k3
VI.
METHODOLOGY
The FFT is a computationally efficient algorithm for computing a discrete Fourier transform (DFT). The N-point DFT is defined asX(k) = ∑ (n)e−(j2πnk/N) , k = 0,1,2, .. .. , N-1
Where N is the transform size, or the number of points
DIF Radix – 8 Algorithm:
X(8k+l) = ∑
(n)WN(8k + l)n
= ∑ (∑
(n+
) WN(8k + l)(mN/8 + n) )
= ∑ (∑
(n+
) W8 lm )WN nl WN/8 nk = ∑ *
[x(n)+ x ( n +
) W4l + x ( n +
) W42l + x( n +
)W4-l] +[ x ( n + ) + x ( n +
) W4l + x ( n +
) W42l + x ( n +
) W4 -l
] W8 l
} WN nl
WN/8 nk
]
l = 0,1,2,3,4,5,6,7 ; k= 0 to N-1.
This could be broken into Radix 23 Algorithm. It is Given as
X(8k +4l3 + 2l2 + l1) = ∑ *[ x(n) + x(n + ) W2l1 + x( n +
) W212 W4l1 + x ( n +
) W2l1] + [ x(n + ) + x ( n +
) W2l1 + x ( n +
) W212 W4l1 + x ( n +
) W2l1]W82l2+l1} WNn(4l3+2l2+l1)WN/8nk
38
Copyright © 2016. Vandana Publications. All Rights Reserved.
VII.
RESULT
Xilinx Simulation Result for x(n) = [1 0 1 0 1 0 1 0]
39
Copyright © 2016. Vandana Publications. All Rights Reserved.
Internal connection of top module:40
Copyright © 2016. Vandana Publications. All Rights Reserved.
VIII. ANALYSIS OF RESULT &
CONCLUSION
Earlier when using DFT, the number of calculations that was required were:
(N/2)2+N complex multiplies
2(N/2)(N/2 −1)+N=(N2
/2) complex additions
Using FFT, the number of calculations were reduced to a much extent, ie.
(N/2)log2N complex multiplies
Nlog2N complex adds
By implementing special butterflies for these twiddle factors, the computational cost of the radix-2 decimation-in-time FFT can be reduced to
Nlog2N−7N+12 real multiplies
Nlog2N−3N+4 real additions
REFERENCES
[1] K.Harikrishna, T.Rama Rao, Vladimir A. Labay, (2011), ―FPGA implementation of FFT algorithm for IEEE 802.16e (Mobile WiMAX)‖, International journal of Computer Theory and Engineering, Page: 197-203.
[2] Lenart , Viktor Öwall(2006) ―Architectures for dynamic data scaling in 2/4/8k pipeline FFT cores‖. IEEE transactions on Very Large Scale Integration (VLSI) systems, Pages: 1286-1290.
[3] Mian Sijjad Minallah, Gulistan Raja, (2006),‖ Real Time FFT Processor Implementation‖. IEEE—ICET 2006 2nd International Conference on Emerging Technologies. Peshawar, Pakistan, Pages: 192-195.
[4] S Sukhsawas, K Benkrid,(2004), ―A High-level Implementation of a High Performance Pipeline FFT on Virtex-E FPGAs‖. Proceedings of the IEEE Comp. Society Annual Symp. on VLSI Emerging Trends in Systems Design (ISVLSI’04).
[5] E.H. Wold and A.M. Despain,(1984), ―Pipeline and parallel-pipeline FFT
processors for VLSI implementation.‖ IEEE Transaction on Computers‖, Pages: 414–426.
[6] A.M. Despain,(1974), ―Fourier transform computer using CORDIC iterations‖, IEEE Transaction on Computers, Pages:993–1001.
[7] Wang, A., Chandrakasan, (2005),‖ 180-mV subthreshold FFT processor using a minimum energy design methodology‖. IEEE J. Solid State Circuits 310–319
[8] A. Agarwal (1991) ―Limits on Interconnection Network Performance.‖ IEEE Trans. Parallel Distrib. Syst., 2(4):398– 412,.
[9]Weste, N., Eshraghian, K. (1985): Principles of CMOS VLSI Design: A Systems Perspective. Addison-Wesley, Reading, MA
[10] K. K. Parhi, ―VLSI Digital Signal Processing Systems: Design and Implementation,‖ John Wiley & Sons, 1999. [11] J. G. Proakis and D.G. Manolakis, ―Digital Signal Processing, Principles, Algorithms and Applications.‖ 3rd Edition, 1998, Prentice Hall India Publications.
[12] John G. Proakis and Dimitris K Manolakis (1995) Digital Signal Processing: Principles, Algorithms and Applications, Prentice-Hall, Inc.
[13] A. V. Oppenheim and R. W. Schafer, Digital Signal Processing, Prentice- Hall, 1975.
[14] http://www.xilinx.com/ [15] http://www.dspguide.com. [16] http://www.analog.com.
