NETWORK-ON-CHIP NETWORK ADAPTER
MOHD FARHAN SHA’ARI
A project report submitted in partial fulfillment of the requirements for the degree of Master of Engineering (Electrical – Microelectronics and Computer System)
Faculty of Electrical Engineering Universiti Teknologi Malaysia
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Specially dedicated to my parents,
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AKNOWLEDGEMENT
Thanks to Allah for His blessing which has encouraged and given me and giving strength to carry out my research until the final stage of this report writing. May Allah give blessing upon our holy prophet Muhammad S.A.W.
I would like to take this opportunity to express my sincere gratitude to all of those have contributed their effort, support and advise in accomplishing this project. My deeply gratitude is toward my project supervisor, Dr. Muhammad Nadzir Marsono who has always encouraged, given me confidence and most valuable guidance throughout the completion of this project.
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ABSTRACT
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ABSTRAK
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TABLE OF CONTENTS
CHAPTER TITLE PAGE
TITLE PAGE i
DECLARATION ii
DEDICATION iii
ACKNOWLEDGEMENT iv
ABSTRACT v
ABSTRAK vi
TABLE OF CONTENTS vii
LIST OF TABLES x
LIST OF FIGURES xi
LIST OF ABBREVIATIONS xiii
LIST OF APPENDICES xiv
I PROJECT OVERVIEW
1.1 Introduction 1
1.2 Problem Statement 2
1.3 Project Objectives 3
1.4 Scope of the Project 3
1.5 Thesis Organization 3
II NETWORK-ON-CHIP
2.1 NoC Overview 4
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2.2.1 NoC Architecture – Router 6 2.2.2 NoC Architecture – Network Adapter 6
2.3 Network-on-Chip Layers 7
2.4 NoC Layered Approach Benefits 10
2.5 Wishbone Protocol 12
2.5.1 Wishbone Basics 13
2.5.2 Wishbone Interface and Connection Type 14
2.5.3 Wishbone Bus Cycles 17
2.6 Chapter Summary 19
III METHODOLOGY AND IMPLEMENTATION
3.1 Introduction 20
3.2 Methodology 20
3.3 Type of Network Adapter 21
3.4 Message Segmentation and Reassembly 22 3.5 Best Effort and Flit Formatting 22 3.6 Wishbone Interface Network Adapter Overview 26 3.6.1 Network Adapter Components – Top View 26 3.6.2 Network Adapter Components –
Request Unit 29
3.6.3 Network Adapter Components –
Encapsulation Unit 31
3.6.3.1 Dual-Clock First-In-First-Out
(FIFO) Buffer 35
3.6.4 Network Adapter Components –
Decapsulation Unit 36
3.6.5 Network Adapter Components –
Response Unit 40
3.6.6 Network Adapter Components –
Master/Slave Controller Unit 42
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IV PROJECT RESULT AND ANALYSIS
4.1 Introduction 44
4.2 Simulation Result – BE Read Request Operation 44 4.3 Simulation Result – BE Read Response Operation 46 4.4 Simulation Result – BE Write Request Operation 48 4.5 Simulation Result – BE Read Response Operation 51
4.6 Operations Speed and Latency 53
4.7 Operations Resources Utilization and Power 54
4.8 Chapter Summary 55
V CONCLUSION AND FUTURE WORKS
5.1 Significance of Findings 56
5.2 Future Works 57
REFERENCES 59
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LIST OF TABLES
TABLE NO. TITLE PAGE
2.1 Wishbone signals for master and slave core 14
3.1 CMDcmp representation 38
4.1 BE operations latency in NA 53
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LIST OF FIGURES
FIGURE NO. TITLE PAGE
2.1 Topological illustration example for 4x4
mesh NoC. 5
2.2 NA implements two interfaces, the core interface
and network interface. 7
2.3 NoC abstraction layers. 8
2.4 NoC layer mapping to OSI reference stack 9 2.5 The flow of data from source to sink through
the NoC components with an indication of the
types of datagrams. 9
2.6 Wishbone interconnection system. 13
2.7a A point-to-point interconnection. 16
2.7b A data flow interconnection. 16
2.7c A shared-bus interconnection. 16
2.7d A switched bus interconnection. 17
2.8 Wishbone Single read and write operation. 18
3.1 Diagram of project methodology. 21
3.2 BE header format. 23
3.3 BE format for data, address or EOF flit. 24 3.4 Required flits for read request and write
response operation. 24
3.5 Required flits for write request and read
response operation. 25
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3.7 Request unit input-output block diagram. 29 3.8 Finite state machine for request unit. 30 3.9 ASM flow chart for encapsulation unit. 32 3.10 Encapsulation unit input-output block diagram 33 3.11 Datapath functional block diagram for
encapsulation unit. 34
3.12 Altera DCFIFO input-output block diagram. 36 3.13 ASM flow chart for decapsulation unit operation. 37 3.14 Decapsulation unit input-output block diagram. 38 3.15 Datapath functional block diagram for
decapsulation unit. 39
3.16 Response unit input-output block diagram. 40
3.17 FSM flow chart for response unit. 41
3.18 FSM for master/slave controller unit. 42 4.1 Read request operation from master core to router. 45 4.2 Read request operation from router to slave core. 46 4.3 BE read response operation from slave core
to router. 47
4.4 BE read response operation from router
to master core. 48
4.5 BE write operation from master core to router. 49 4.6 Write request operation from router to slave core. 50 4.7 BE write response operation from slave core
to router. 51
4.8 BE write response operation from router to
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LIST OF ABBREVIATIONS
NOC - Network-on-Chip
SOC - System-on-Chip
NA - Network adapter
IP - Intellectual property
HDL - Hardware description language FPGA - Field programmable gate array OSI - Open system interconnection
GALS - Globally asynchronous, locally synchronous
RMW - Read-modify-write
FSM - Finite state machine
OCP - Open core protocol
FIFO - First in first out
ASM - Algorithmic state machine
GS - Guaranteed services
BE - Best effort
EOF - End-of-flit
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LIST OF APPENDICES
APPENDIX TITLE PAGE
CHAPTER I
INTRODUCTION
1.1 Introduction
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several links. Routing decisions are made at the routers. The routers and links transport data from one destination to another, and network adapter (NA) decouples communication from computation by providing the intellectual property (IP) cores with a standard interface [4].
1.2 Problem Statement
The main problem in SoC is its interconnectivity. To address this issue, NoC has a reliable solution for this problem. It localizes the big SoC system into smaller systems that executes the tasks completely independent to each other [3]. In term of scalability and network reconfiguration, NoC offers vast opportunity for component reuse and plug-and-play functions [2]. Plug and play capability removes the need to adjust or reprogramming the core to make it works with SoC. In order to achieve this capability, a network adapter with a standardized and well-defined interface to the IP cores is definitely required.
1.3 Project Objectives
The main purpose of this project is to propose an architecture of a NoC network adapter. There are three sub-objectives to be achieved for this project.
(i) To propose a master/slave (duplex) NoC network adapter architecture. This architecture uses Wishbone as standardized communication protocol for attached Intellectual Property (IP) core.
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(iii) To verify for network adapter to ensure that the intended design specification and functionality are achieved.
1.4 Scope of the Project
The scope of this project covers the network adapter for duplex communication between IP cores in SoC, including their synchronization process. Network adapter only handles four types of best effort packets. There are read request, read response, write request, and write response. Request or response packets are sent to the network in pre-determined flit format that both router and network adapter able to interpret it. Flit is sent one by one to network. To simplify the design, router address is assumed to be similar as core address. Hence, network adapter will not have its own route table. Flits transmission and routing is done by the router. This architecture will be implemented using HDL and synthesis to a field-programmable gate array (FPGA) device.
1.5 Thesis Organization
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REFERENCES
1. Maria Elisabete Marques Duarte (2003). Network on chip : Design Challenges, 4th Internal Conference on Computer Architecture (ICCA) 2003. 31-1 Feb. Universidade do Minho, Portugal.
2. Juliana Pei Zhao (2004). An OCP compliant Network Adapter using MANGO. Master Degree, Technical University of Denmark.
3. L. Benini and G. De Micheli (2002). Networks on chips: A new SoC paradigm. IEEE Computer, 35(1):70–80.
4. Rasmus Grøndahl Olsen (2005). OCP Based Adapter for Network-on-Chip. Master Degree, Technical University of Denmark.
5. Tobias Bjerregaard & Shankar Mahadevan (2006). A survey of research and practices of network-on-chip. ACM Computing Surveys, March, volume 38, number 1,page 1-51.
6. Bei Yin (2005). Design and implementation of a wormhole router supporting multicast for Network-on-Chip. Master Degree, Royal Institute of Technology Stockholm.
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8. Tobias Bjerregaard, Shankar Mahadevan, Rasmus Grondahl Olsen and Jens Sparrso (2005). An OCP Compliant Network Adapter for GALS-based SoC Design Using the MANGO Network-on-Chip. Proceedings of the International Symposium on System-on-Chip, IEEE, November 2005.
9. Wishbone SoC Architecture Specification, Revision B3, 2003. Silicore and www.opencores.org.
10. SCFIFO and DCFIFO Megafunction User Guide, September 2009. Altera Corporation.
11. Quartus II Handbook version 9.0, Power estimation and analysis. Volume 3, Section III, March 2009. Altera Corporation.
