SC14404
Complete Baseband Processor for DECT Handsets
General Description
The SC14404 is a CMOS chip optimized to handle all the audio, signal and data processing needed within a DECT handset. An ADPCM transcoder, a very low power CO- DEC and Analog Frontend is integrated. Direct connec- tions towards microphone and a (dynamical) loudspeaker are provided. Duplex quality handsfree operation is inte- grated.
The SC14404 is designed to fit to any radio design.
A dedicated TDMA controller handles all physical layer slot formats and radio control.
National Semiconductors standard CompactRISCTM CR16B 16 bit microcontroller takes care of all the higher protocol stack. 4 kilobyte F lash is integrated for parameter and number storage.
Features
nIntegrated DECT Baseband transceiver optimized for GAP handsets according to ETS 300 175-2, 175-3 &
175-8.
nTwo on board low drop voltage regulators with 2.85V and 3.0- 3.8V (with external resistors the voltage can be determined) output.
n2V upto 3.6V battery input with onboard step up con- verter.
n3V upto 5.0V battery monitor input.
nAdvanced battery management unit nVery low power in active and paging mode.
nEmbedded 16 bit CompactRISCT M Micro Controller.
(CR16B) with programmable clock speeds.
n4k byte memory mapped Flash
n320 kbyte Flash or factory programmed ROM FLASH.
nACCESSBUSTM or MICROWIRET M interfaces n5,5 kilobyte on-chip Data Memory.
nOne full duplex ADPCM transcoder.
nOn-chip 14-bit linear CODEC.
n14 upto 44 dB gain differential microphone input buffer.
n100 Ω loudspeaker driver.
nSoftware controlled gain on audio input and output.
nPeak hold ADC for RSSI measurement.
nFive general purpose inputs can be multiplexed on an 8 bit ADC with selectable ranges.
nOn-chip dedicated TDMA instruction co-processor which supports 1.152 MHz, 0.576 MHz and 0.288 MHz bit rates.
nSeven programmable control signals for radio front end.
nFull and double slot, protected and unprotected B- fields.
nDuplex quality handsfree operation.
nTone generator. Tones consisting of 3 frequencies can be programmed
nLinear PCM interface for external codec.
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System Diagram
PRELIMINARY
FEBRUARY 2000
1 4 4 0 4 C o m p le te B a s e b a n d P ro c e s s o r fo r D E C T H a n d s e ts
T M T M T M
1 4 4 0 4 C o m p le te B a s e b a n d P ro c e s s o r fo r D E C T H a n d s e ts
1.0 CONNECTION DIAGRAMS
Order Number SC14404BFLAG (320kbyte Full FLASH, Boot mode A, 100 pins TQFP, Order Number SC14404BFLBG (320kbyte Full FLASH, Boot mode B, 100 pins TQFP Order Number SC14404BxxAG (320kbyte ROM FLASH, Boot mode A , 100 pins TQFP)
Order Number SC14404BxxBG (320kbyte ROM FLASH, Boot mode B, 100 pins TQFP) See NS Package Number VJG100A
AD0 AD1 AD2 AD3 RSTN AVS2
LRS+
AVD
VDDRF LRS-
VREF- MIC- AGND MIC+
VREF+
VBAT1 VBAT2 VBAT3 DC_stab
LDO1_CTRL DC_I AVS
AD18
CAP DAC PD7 PD1 PD5 PD4 PD3 PD2
Xtal1 RFCLK
RSSI
PCM_FSC/PD6/ADC3 PCM_CLK /DAC2/ ADC2 VSS
SK SO TDO CMPREF RDI
LE VDD
P0[3] P0[4] P0[5] P0[6] P0[7] P1[0] P1[1] P1[2] P1[3] P1[4] P1[5] P2[5]
VDD VSS DC_CTRL
P2[0] P2[1] P2[2]
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
SC14404
AD4 AD5 AD6 AD12 AD15 AD16 WRn AD17 AD14 AD13 AD9 AD11 RDn AD10 RCSn DAB7 DAB6 DAB5 VSS VDD DAB4 DAB3 DAB2
AD8
AD7 INT1n
INT0n INT2n INT3n INT4n PON
INT5n PWM0 PCM_DI PWM1 ADC0
P1[6] P1[7] SCLP2[4]
P2[3]PCM_D0 ADC1
AVD2
DC_Sense LDO_Sense LDO2_CTRL
P0[0] P0[1] P0[2]
UTX URX
DAB0 DAB1
P2[6]
CHARGE SDA
DC_DIS
P2[7]
1 4 4 0 4 C o m p le te B a s e b a n d P ro c e s s o r fo r D E C T H a n d s e ts
Order Number SC14404BFLBC (320kbyte Full FLASH, Boot mode B, 100 pins CSP Order Number SC14404BxxBC (320kbyte ROM FLASH, Boot mode B, 100 pins CSP
Note 1: All digital outputs can sink/source 2 mA unless otherwise specified. All digital inputs are Schmitt trigger types. After reset all I/Os are set to input and all pull-up or pull-down resistors are enabled unless otherwise specified.
PU = Pull-up resistor enabled, PD = Pull-down resistor enabled, I = input A-I, B-I = In Boot mode A or B input and pull-up or pull-down resistor disabled,
A-PD, B-PU = In Boot mode A, Pull-down resistor enabled. In Boot mode B, pull-up resistor enabled.
Note 2: Reset state of address and data bus and WRn, RDn pins:
If SC14404: Hi-Z/1 means Hi-Z if RSTn is LOW, if RSTn goes HIGH i t t akes 32 SCLK cycles = 25 usec before these pin drives a ‘1’.
Table 1: TQFP pin mapping onto CSP package (See table 2 for TQFP pin description)
1 2 3 4 5 6 7 8 9 10
A 1 99 96 93 89 88 86 85 83 76
B 8 2 98 95 92 90 87 80 77 74
C 10 5 3 97 94 84 82 78 73 71
D 11 12 7 6 100 79 81 72 70 68
E 13 15 9 4 16 91 75 69 67 64
F 14 17 19 25 41 66 54 59 65 63
G 18 20 22 31 29 50 56 57 62 61
H 21 23 28 32 34 44 47 53 55 60
J 24 27 30 37 40 42 45 48 52 58
K 26 33 35 36 38 39 43 46 49 51
1 2 3 4 5 6 7 8 9 10 A
B C D E F G H J K
SC14404 CSP pin diagram (TOP View)
1 4 4 0 4 C o m p le te B a s e b a n d P ro c e s s o r fo r D E C T H a n d s e ts
FIGURE 1. SC14404 Block diagram
BLOCK DIAGRAM
1 4 4 0 4 C o m p le te B a s e b a n d P ro c e s s o r fo r D E C T H a n d s e ts 2.0 Package information
FIGURE 2. 100 pins TP Quad Flat Pack. NS Package Number VJG100A
1 2 3 4 5 6 7 8 9 10
A B C D E F G H J K 0.8 TYP
(7.2 TYP) (1.4 TYP)
0.36 +- 0.05 TYP 1.4 0.1+
-
0.46 TYP 10+0.2
- 10 0.2+
-
A1 BALL PAD CORNER
A1 BALL PAD CORNER
Bottom view Top view
Dimensions are in milimeters Note 2
N Note 3
SEATING PLANE Note 3 0.1
0.15 M N 0.08 M N
L S M S NOTES: UNLESS OTHERWISE SPECIFIED
1. SOLDER BALL COMPOSITION: Sn 63%, Pb 37%
2. DIMENSIONS MEASURED AT MAXIMUM SOLDER BALL DIAMETER, PARALLEL TO PRIMARY DATUM N
3. PRIMARY DATUM N AND SEATING PLANE ARE DEFINED BY THE SPHERICAL CROWNS OF THE SOLDER BALLS
L M
4. NO JEDEC REGISTRATION AS OF JUNE 1998
1 4 4 0 4 C o m p le te B a s e b a n d P ro c e s s o r fo r D E C T H a n d s e ts
3.0 Product status definitions Definition of Terms
Data Sheet
Identification Product Status Definition
Advance Information Formative or In Design
This data sheet contains the design specifications for product development. Specifications may change in any manner without notice.
Preliminary First Production
This data sheet contains preliminary data. Supplementary data will be published at a later date. National Semiconductor Corporation reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
No Identification Noted Full Production
This data sheet contains final specifications. National Semiconduc- tor Corporation reserves the right to make changes at any time without notice in order to improve design and supply the best possi- ble product.
Obsolete Not In Production
This data sheet contains specifications on a product that has been discontinued by National Semiconductor Corporation. The datash- eet is printed for reference information only.
LIFE SUPPORT POLICY
NATIONAL’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF NATIONAL SEMICONDUCTOR CORPORATION. As used herein:
1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and whose failure to per- form, when properly used in accordance with instructions for use provided in the labeling, can be reasonably ex- pected to result in a significant injury to the user.
2. A critical component is any component of a life support device or system whose failure to perform can be rea- sonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness.
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