INSTALLATION and OPERATION MANUAL

I N S T A L L A T I O N

and

Table of Contents

Chapter 1: Introduction

1.1 General ………. 1

1.2 Data Port Interfaces ………. 2

1.3 G.703/64K Interface ……… 3

1.4 Features ……… 6

1.5 Specifications ………...… 6

1.6 Loop Back Diagnostics ……… 7

1.7 Timing Considerations ………. 7

Chapter 2: Installation and Operation

2.2 Site Preparation ……… 9

2.3 Mechanical Assembly ……….. 9

2.4 Electrical Installation ………... 9

2.5 Dip Switch and Jumper Settings ……….……. 11

2.6 Front Panel ………... 13

2.7 Loop Back Operation ………... 13

2.8 Auto Delay Feature ……….. 16

Chapter 3: Optional Rack Mounting

Appendix A: DIP Switch Setting Tables

A.1 DSW1 Setting (Clock Source Setup) ……….…. 19

A.2 DSW2 Setting (Data Port Setup) ……… 20

Table of Contents

Appendix B: Cable Pin Out Definition Tables

B.1 DB9 Connectors ……….. 23

B.2 User Data Port Connector for RS-232 ……….… 24

B.3 User Data Port Connector for RS-530 ………. 25

B.4 User Data Port Connector for V.35 ……….… 26

B.5 User Data Port Connector for X.21 ……….… 27

B.6 User Data Port Connector for RS-449 ……….… 28

Chapter 1: Introduction

1.1 General

The MUX128/2*64 Access Unit is used to multiplex two G.703/64Kbps bit flows to one 128K Synchronous Data Port or vice versa.

Referring to the Point-to-Point example below, no additional bandwidth is available for synchronization. Therefore, it is important that the transmission delay between the two units be less than half of a 64Kbps cycle.

Figure 1-1: Point to point connection diagram

The delay between A CH 64K and B CH 64K should be the same. Any delay may be manually nulled via DIP switch settings. The delay may also be automatically detected while in “Auto Delay” mode for automatic nulling. In either case, for normal operation, the delay between channels must remain fixed after setting.

Figure 1-2: Multiplex/De-multiplex Timing Diagram

1 2 3 4 5 6 7 8 9 1 3 5 7 2 4 6 8 128Kbps data A CH B CH 64Kbps 64Kbps

Chapter 1: Introduction

To achieve proper operation, the timeslot assignment of transmit and receive sides must be the same and sequential, otherwise, the multiplex and de-multiplex feature will not work reliably.

Figure 1-3: Typical Application of MUX128/2*64

1.2 Data Port Interfaces

The data port of the MUX128/2*64 is DCE and runs at a fixed rate of 128Kbps in synchronous mode only. At the receiving side, the incoming data is split equally, bit-for-bit, to the A and B channels of the G.703/64K interfaces. When receiving data from the G.703 channels, the data is recombined to form the outputted 128Kbps stream.

There are 6 interface standards supported by the Data Port. They are RS-530, RS-449, X.21, V.35, RS-232 and V.36. The output connector for the Data Port is a standard DB25F connector. Interface selection is provided by a combination of DIP switch settings and physical adapter cables. For exact DIP switch settings and cabling information, please refer to Appendices A and B respectively.

Chapter 1: Introduction

1.3 G.703/64K Interface

The G.703 Interfaces used in the MUX128/2*64 have a through rate of 64Kbps each and operate in co-directional mode only. The following will describe co-directional operation in more detail.

Co-directional

The term co-directional is used to describe an interface across which the information and its associated timing signal are transmitted in the same direction (see Figure 1-4).

Figure 1-4: Co-directional interface

This mode is the most popular for point-to-point applications. All timing modes (recovery, transparent, data port or internal oscillator) are possible in this mode.

Equipment

Data signal Timing signal

Chapter 1: Introduction

G.703 Co-directional Code Conversion Rules

Figure 1-5: G.703 Co-directional Code Conversion Rules Illustration

Step 1: A 64Kbps period is divided into four unit intervals. Step 2: A binary “one” is coded as a block of four bits “1100”. Step 3: A binary “zero” is coded as a block of four bits “1010”. Step 4: The binary signal is converted into a three-level signal. Step 5: A “Violation” block marks the last bit in an octet.

The next page displays a figure showing the boundaries for the standard pulse signals for proper operation and compatibility with other G.703 equipment.

7 1 8 0 1 3 4 5 1 6 1 7 1 8 0 1 0 1 0 2 0 1 Octet timing Step 5 Step 4 Steps 1 - 3 64 kbit/s data Bit number Violation Violation

Chapter 1: Introduction

Figure 1-6: Pulse Masks for the 64Kbps co-directional interface.

V 0 V 0 3 ,1 2_µs (3 ,9 – 0 ,7 8 ) 3 ,5 1 s (3,9 – 0,39) 3,9 s 4,29µs (3,9 + 2,6) 6 ,5 µs ( 3 ,9 + 0, 39 ) 7 ,8µs (3 , 9 + 3 , 9 ) 0,5 1 ,0 7 ,0 2_µs ( 7 ,8 – 0 ,7 8 ) 7,41µs ( 7 ,8 – 0 ,3 9 ) 7,8 s 8 ,1 9µs ( 7 ,8 + 2, 6 ) 1 0 ,4µs (7,8 + 0,39) 1 1 ,7 s (7 , 8 + 3 , 9 ) 1 ,0 0 ,5 µ

a)Mask for single pulse

Chapter 1: Introduction

1.4 Features

Primary G.703 Link l 2 channels (2x64Kbps)

l Interface: 64Kbps G.703 co-directional Synchronous mode Data Port interface

l 1 channel DCE-128Kbps: RS-530, RS-449, X.21, V.35, RS-232, or V.36 Data Port

l DSR constantly ON except in test l DCD constantly ON

l Data port Loop back (Loop back to DTE) l Self testing function

1-5 Specifications

l Complies with: ITU G.703 and G.823 (jitter) l Frame format: unframed only

l Line code: 64Kbps co-directional line code l Connector: DB9/F (proprietary)

User Data Interface Specifications

l Interface Types: RS530, RS-449, X.21, V.35, RS-232 and V.36 l Data rate: 128Kbps SYNC

Chapter 1: Introduction

1.6 Loop back Diagnostics

The MUX128/2*64 features V.54 diagnostic capabilities for performing local loopback and BERT testing. The operator at either end of the G.703 lines may test the MUX128/2*64 in the digital loopback mode. The loopback function is controlled by push-button switches, located on the MUX128/2*64 front panel.

When the “Test” push-button is activated, the unit generates a 511 test pattern, according to ITU, for direct end-to-end integrity testing. The Error indicator flashes for each bit error detected. Operation is described in Chapter 2.

1.7 Timing Considerations

Multiple clock source selection provides maximum flexibility in connecting both the G.703/64K link and user data interface. The G.703/64K link may be clocked from the recovered receive clock, from the user data port or from the internal oscillator.

The MUX128/2*64 has the flexibility to meet the timing requirements of various system configurations. The timing mode for the G.703/64K link and the user channel, is selected by DIP switch setting.

Chapter 1: Introduction

E1 link timing

The MUX128/2*64 G.703/64K link receive path always operates on the receive clock. The MUX128/2*64 recovers the receive clock from the received link data signal. The source of the MUX128/2*64 link transmit clock may be selected by the user. The following four transmit timing modes are available.

• Recovery timing:

The MUX128/2*64 G.703 link transmit clock is locked to the recovered receive clock. This is usually the timing mode selected for network operation.

• Internal timing:

The MUX128/2*64 G.703 link transmit clock is derived from the internal clock oscillator. This timing mode is necessary in point-to-point applications over leased lines. In this case, one MUX128/2*64 must use the internal oscillator, and the other must operate from the recovered clock.

• Transparent timing:

The MUX128/2*64 synchronous data channel accepts the recovered G.703 clock and provides the G.703 transmit clock from the DCE (Transparent timing).

• External timing:

The ETU-01A E1 link transmit clock is locked to the clock signal provided by the user DCE connected to the data channel.

Chapter 2: Installation and Operation

2.1 General

This chapter provides detailed instructions for mechanical installation and operation of the MUX128/2*64.

2.2 Site Preparation

Install the MUX128/2*64 within reach of an easily accessible grounded AC outlet. The outlet should be capable of furnishing 90 ~ 250 VAC. Allow at least 10 cm (4 inch) clearance at the rear of the MUX128/2*64 for signal lines and interface cables.

2.3 Mechanical Assembly

The MUX128/2*64 is designed for tabletop, bench, or optional rack mount installation, and is delivered completely assembled. No provision has been made for bolting the MUX128/2*64 to a tabletop. Rack mounting instructions are provided in Chapter 3.

2.4 Electrical Installation

2.4.1 Power connection

AC power is supplied to the MUX128/2*64 through a standard 3-prong IEC connector. (Refer to Figure 2-1) The MUX128/2*64 should always be grounded through the protective earth lead of the power cable. The power supply within the MUX128/2*64 is a switching power type, designed to operate from any AC voltage, 90 to 250 volts.

Chapter 2: Installation and Operation

Figure 2-1: MUX128/2*64 back panel

The line fuse is located in an integral-type fuse holder on the rear panel. Make sure that only fuses of the required rating are used for replacement. Do not use repaired fuses or short-circuit the fuse holder. Always disconnect the power cable before removing or replacing the fuse.

2.4.2 Rear panel connectors

The MUX128/2*64’s CH-128 DB25F connector, in combination with various DIP switch settings and adapter cables, provides for six interface types (RS-530, RS-449, X.21, V.35, RS-232 and V.36). The G.703/64K line connectors incorporate DB9F connectors. (Appendix B provides detailed pin out information on the various interface connectors).

IEC Connector and fuse holder

Data Port Connector

G.703/64K Connectors

Chapter 2: Installation and Operation

2.5 DIP Switches and Jumper Settings

2.5.1. Caution

To avoid accidental electrical shock, disconnect the MUX128/2*64 power cord prior to opening the cover.

2.5.2. Procedure

a. Turn power OFF. Disconnect the power cord from the AC outlet.

b. Loosen the thumb screws at the left/right of the rear panel. c. Remove the PCB assembly.

d. Adjust the DIP switches and jumper as required, according to the tables in Appendix A.

e. Replace the PCB and tighten the screws.

Referring to the following figure, three DIP switches are used for configuration and are labeled DSW1 to DSW3. If a DIP switch configuration is changed while the MUX128/2*64 is in a powered on state, the effect will not be realized until the unit is power cycled off then on.

The Logic Ground Jumper will connect (CON) or disconnect (DIS) the MUX128/2*64 logic ground from chassis ground. Chassis ground is connected directly to the ground post of the IEC power connector.

Chapter 2: Installation and Operation

CH-128 Data Port G.703/64K (x2)

Loop Back Test Sws. Indicator LEDs

DSW1

DSW2

DSW3

Chapter 2: Installation and Operation

2.6 Front Panel

The front panel of the MUX128/2*64 provides user access to the diagnostic loop back push-button switches as well as a visual reference of activity via LED display.

Figure 2-3: MUX128/2*64 front panel layout

Label Color Description

PWR green Lights when unit is powered on.

TD yellow Flashes when data is transmitted from the 128K data port.

RD yellow Flashes when data is received at the 128K data port.

RTS yellow Lights when the connected DTE equipment supplies RTS.

DCD yellow Normally, should be lit during operation.

Ta yellow Flashes when G.703 A-channel transmits data.

Ra yellow Flashes when G.703 A-channel receives data.

Tb yellow Flashes when G.703 B-channel transmits data.

Rb yellow Flashes when G.703 B-channel receives data.

Err red Indicates error in BERT or slip in A-B channel delay.

Test red Lights when any push-button switch is selected.

Table 2-1: Indicator LED descriptions

2.7 Loop Back Operation

The loop back test buttons and LED indicators built into the MUX128/2*64 allow for rapid checking of the data terminal, MUX128/2*64 and the G.703/64K lines. Before testing the operation of the data system equipment and line circuits, please ensure that all units are turned on and are configured correctly.

Chapter 2: Installation and Operation

Bit Error Rate Tester

When the “Test” push-button is depressed, the internal pattern generator and pattern tester will be activated and a 511 test pattern will be transmitted out the 64K co-directional lines. The “Test” LED will light. Referring to figure 2-4, if the remote MUX128/2*64 unit also has its “Test” push-button switch depressed, its internal pattern generator and tester will be activated and its signal will be received by the local unit. In this configuration, both units and the lines are tested. Both units will have their “Test” LEDs lit and “Err” LEDs should be off.

Figure 2-4: Back-to-back BERT testing

Referring to figure 2-5, if the remote MUX128/2*64 unit is placed into loop back by placing its “Loc ana loopbk” switch in the depressed position, the 511 pattern will be returned to the local unit and tested. This will test the local unit and lines. If there are no errors, the “Err” LEDs should be off.

Chapter 2: Installation and Operation

Figure 2-5: Remote loop back test

In the next example (refer to figure 2-6), a Datacom BERT tester, such as the HCT-6000 is connected to the MUX128/2*64 data port. The MUX128/2*64 is placed in DTE loop back mode by depressing the "DTE loopbk” push-button switch. This will enable testing of the data port interface.

Chapter 2: Installation and Operation

2.8 Auto Delay

A feature of the MUX128/2*64 is the auto delay function. If the two G.703/64K Co-directional signals arrive out of time at the receivers, the 128K data stream cannot be properly re-assembled. The delay between channels may be nulled by manually setting DIP switch 3 or by performing the auto delay function.

In order to perform auto delay, there must be someone at each end of the link (refer to figure 2-7).

Figure 2-7: Null Delay Feature

At the local and remote sites, depress the “Test” switches. Then depress the “Auto Delay” switches on each unit. When the “Err” LEDs go out, release the “Auto Delay” switches. The delay both ways has been calculated and saved in each unit. Now release the “Test” switches. The delay settings have been saved in EEPROM and are read whenever the unit is powered up. There is no need to re-calibrate unless the environment is changed.

Chapter 3: Optional Rack Mounting

All Standalone/Rack Series units have the option of adding standard EIA 19” rack mount capability. Two rack mount options provide for either mounting a single unit (half space) in a rack or for mounting two units in tandem (full space). In either situation, one standard rack unit space is required. Each rack mount kit provides all the necessary hardware for a complete installation.

Figure 3-1: Rack Mount Installation, ETU01-SS.

In single unit installations, the unit may be placed in the left or right side position simply by reversing the rack mounting “ears”. The kit includes, one (1) short and one (1) long rack adapter, four (4) 3x8mm self-tapping screws, and four (4) #12-24x0.5” screws.

Chapter 3: Optional Rack Mounting

In order to save rack mount space, units may be mounted in tandem. Please refer to the following drawing examples for this application.

Figure 3-2: Tandem Units Mounting (Exploded)

Figure 3-3: Tandem Units Mounting Detail

The tandem kit includes two (2) rack mount adapters, one (1) each of inner and outer central mounting adapters, twenty (20) 3x8mm self-tapping screws, and four (4) #12-24x0.5” screws.

Appendix A: DIP Switch Setting Tables

A.1 DSW1 Setting (Clock Source Setup)

DSW1 STATE FUNCTION

OFF OFF RX timing from recovery, TX timing from data port.

ON OFF RX and TX timing both from recovery. OFF ON RX and TX timing both from data port. -1 -2

ON ON RX and TX timing both from internal oscillator.* OFF Recovery timing source: Channel A.*

-3

ON Recovery timing source: Channel B. -4 Reserved.

-5 Reserved. -6 Reserved. -7 Reserved. -8 Reserved. * note: Factory setting.

Appendix A: DIP Switch Setting Tables

A.2 DSW2 Setting (Data Port Setup)

DSW2 STATE FUNCTION

OFF OFF Data port type: RS-530, RS-449, X.21* ON OFF Data port type: V.35

OFF ON Data port type: RS-232 (SYNC ONLY) -1 -2

ON ON Data port type: V.36

OFF RX clock polarity: NORMAL* -3

ON RX clock polarity: INVERTED OFF TX clock polarity: NORMAL* -4

ON TX clock polarity: INVERTED OFF CTS: Always ON*

-5 ON CTS: Follow RTS OFF Reserved. -6 ON Reserved. OFF Reserved. -7 ON Reserved.

OFF Front panel switches: DISABLE -8

ON Front panel switches: ENABLE* *note: Factory setting.

Appendix A: DIP Switch Setting Tables

A-3 DSW3 Setting (Delay)

DSW2 STATE

-1 -2 -3 -4 -5 FUNCTION

OFF OFF OFF OFF OFF Delay clock cycle: 0

ON OFF OFF OFF OFF Delay clock cycle: 1

OFF ON OFF OFF OFF Delay clock cycle: 2

ON ON OFF OFF OFF Delay clock cycle: 3

OFF OFF ON OFF OFF Delay clock cycle: 4

ON OFF ON OFF OFF Delay clock cycle: 5

OFF ON ON OFF OFF Delay clock cycle: 6

ON ON ON OFF OFF Delay clock cycle: 7

OFF OFF OFF ON OFF Delay clock cycle: 8

ON OFF OFF ON OFF Delay clock cycle: 9

OFF ON OFF ON OFF Delay clock cycle: 10

ON ON OFF ON OFF Delay clock cycle: 11

OFF OFF ON ON OFF Delay clock cycle: 12

ON OFF ON ON OFF Delay clock cycle: 13

OFF ON ON ON OFF Delay clock cycle: 14

ON ON ON ON OFF Delay clock cycle: 15

OFF OFF OFF OFF ON Delay clock cycle: 16

ON OFF OFF OFF ON Delay clock cycle: 17

OFF ON OFF OFF ON Delay clock cycle: 18

ON ON OFF OFF ON Delay clock cycle: 19

OFF OFF ON OFF ON Delay clock cycle: 20

ON OFF ON OFF ON Delay clock cycle: 21

OFF ON ON OFF ON Delay clock cycle: 22

ON ON ON OFF ON Delay clock cycle: 23

OFF OFF OFF ON ON Delay clock cycle: 24

ON OFF OFF ON ON Delay clock cycle: 25

OFF ON OFF ON ON Delay clock cycle: 26

ON ON OFF ON ON Delay clock cycle: 27

OFF OFF ON ON ON Delay clock cycle: 28

ON OFF ON ON ON Delay clock cycle: 29

OFF ON ON ON ON Delay clock cycle: 30

ON ON ON ON ON Delay clock cycle: 31

OFF Delay channel: B

-6 _ON

Delay channel: A

-7 Reserved.

Appendix A: DIP Switch Setting Tables

Appendix B: Cable Pinout Definition Tables

B.1 DB9 Connectors

The MUX128/2*64 analog port physical interface is a 9-pin female D-type connector wired in accordance with Table B-1.

Pin Designation Direction Function

1 TTIP From

MUX128/2*64

Transmit data (+)

2 -- --

--3 RTIP To MUX128/2*64 Receive data (+)

4 -- -- --5 FG ↔ Frame ground 6 TRING From MUX128/2*64 Transmit data (-) 7 -- --

--8 RRING To MUX128/2*64 Receive data (-)

9 -- --

Appendix B: Cable Pinout Definition Tables

B.2 User DATA Port Connector For RS-232

The MUX128/2*64 user data channel for RS-232 physical interface is a 25-pin female D-type connector wired in accordance with Table B-2.

Abbr. Pin Direction Description FG 1 ↔ Chassis ground.

May be isolated from signal ground. SG 7 ↔ Signal Ground.

TD 2 To

MUX128/2*64

Serial digital data from DTE. RD 3 From

MUX128/2*64

Serial digital data at the output of the

MUX128/2*64/2*64K receiver.

RTS 4 To

MUX128/2*64

Supply an ON signal to the

MUX128/2*64/2*64k when data

transmission is desired. CTS 5 From

MUX128/2*64

Constantly ON or follow RTS. (by DIP SW setting).

DSR 6 From

MUX128/2*64

Constantly ON,

Except during test loops. DTR 20 To MUX128/2*64 Not used. DCD 8 From MUX128/2*64 Constantly ON. ETC 24 To MUX128/2*64

A transmitted data rate clock input from the data source.

TC 15 From

MUX128/2*64

A transmitted data rate clock for use by an external data source.

RC 17 From

MUX128/2*64

A received data rate clock for use by an external data source.

Appendix B: Cable Pinout Definition Tables

B.3 User Data Port Connector For RS-530

The MUX128/2*64 user data channel for RS-530 physical interface is a 25-pin female D-type connector wired in accordance with Table B-3.

Abbr. Pin Direction Description FG 1 ↔ Chassis ground.

May be isolated from signal ground. SG 7 ↔ Signal Ground. TD(A) TD(B) 2 14 To MUX128/2*64

Serial digital data from DTE. RD(A) RD(B) 3 16 From MUX128/2*64

Serial digital data at the output of the

MUX128/2*64/2*64K receiver. RTS(A) RTS(B) 4 19 To MUX128/2*64

ON signal to the MUX128/2*64/2*64k when data transmission is desired. CTS(A) CTS(B) 5 13 From MUX128/2*64

Constantly ON or follow RTS. (DIP SW setting). DSR(A) DSR(B) 6 22 From MUX128/2*64 Constantly ON,

Except during test loops. DTR(A) DTR(B) 20 23 To MUX128/2*64 Not used. DCD(A) DCD(B) 8 10 From MUX128/2*64 Constantly ON. ETC(A) ETC(B) 24 11 To MUX128/2*64

A transmitted data rate clock input from the data source.

TC(A) TC(B) 15 12 From MUX128/2*64

A transmitted data rate clock for use by an external data source.

RC(A) RC(B) 17 9 From MUX128/2*64

A received data rate clock for use by an external data source.

Appendix B: Cable Pinout Definition Tables

B.4 DB25 to MB34 Cable Pin Out for V.35

The MUX128/2*64 user data channel for V.35 physical interface is a cable adapter with a 34-pin female MB-type connector wired in accordance with Table B-4.

Abbr. DB25 PIN# MB34 PIN# V.35 Circuit FG 1 ↔ A Chassis ground. May be isolated from signal ground. SG 7 ↔ B Signal Ground TD(A) TD(B) 2 14 ↔ ↔ PS TD(A) TD(B) RD(A) RD(B) 3 16 ↔ ↔ R T RD(A) RD(B) RTS(A) 4 ↔ C RTS CTS(A) 5 ↔ D CTS DSR(A) 6 ↔ E DSR DTR(A) 20 ↔ H DTR DCD(A) 8 ↔ F DCD ETC(A) ETC(B) 24 11 ↔ ↔ WU ETC(A) ETC(B) TC(A) TC(B) 15 12 ↔ ↔ AAY TC(A) TC(B) RC(A) RC(B) 17 9 ↔ ↔ VX RC(A) RC(B)

Appendix B: Cable Pinout Definition Tables

B.5 DB25 to DB15 Cable Pin Out for X.21

The MUX128/2*64 user data channel for X.21 physical interface is a cable adapter with a 15-pin female DB-type connector wired in accordance with Table B-5.

Abbr. DB25 PIN# DB15 PIN# X.21 Circuit FG 1 ↔ 1 Chassis ground.

May be isolated from signal ground. SG 7 ↔ 8 Signal Ground TD(A) TD(B) 2 14 ↔ ↔ 29 Transmit(A) Transmit(B) RD(A) RD(B) 3 16 ↔ ↔ 4 11 Receive(A) Receive(B) RTS(A) RTS(B) 4 19 ↔ 3 10 Control(A) Control(B) DCD(A) DCD(B) 8 10 ↔ 5 12 Indication(A) Indication(B) ETC(A) ETC(B) 24 11 ↔ ↔ 147 External Timing(A) External Timing(B) RC(A) RC(B) 17 9 ↔ ↔ 136 Signal Timing(A) Signal Timing(B)

Appendix B: Cable Pinout Definition Tables

B.6 DB25 to DB37 Cable Pin Out for RS-449

The MUX128/2*64 user data channel for RS-449 physical interface is a cable adapter with a 37-pin female DB-type connector wired in accordance with Table B-6.

Abbr. DB25 PIN# DB37 PIN# RS-449 Circuit FG 1 ↔ 1 Chassis ground.

May be isolated from signal ground. SG 7 ↔ 19,20,37 SG,RC,SC TD(A) TD(B) 2 14 ↔ ↔ 224 SD(A) SD(B) RD(A) RD(B) 3 16 ↔ ↔ 6 24 RD(A) RD(B) RTS(A) RTS(B) 4 19 ↔ ↔ 7 25 RS(A) RS(B) CTS(A) CTS(B) 5 13 ↔ ↔ 279 CS(A) CS(B) DSR(A) DSR(B) 6 22 ↔ ↔ 1129 DM(A) DM(B) DTR(A) DTR(B) 20 23 ↔ ↔ 1230 TR(A) TR(B) DCD(A) DCD(B) 8 10 ↔ ↔ 1331 RR(A) RR(B) ETC(A) ETC(B) 24 11 ↔ ↔ 1735 TT(A) TT(B) TC(A) TC(B) 15 12 ↔ ↔ 235 ST(A) ST(B) RC(A) RC(B) 17 9 ↔ ↔ 268 RT(A) RT(B)

Appendix B: Cable Pinout Definition Tables

B.7 DB25 to DB37 Cable Pin Out for V.36

The MUX128/2*64 user data channel for V.36 physical interface is a 25-pin female D-type connector wired in accordance with Table B-7.

Abbr. Pin Direction Description FG 1 ↔ Chassis ground.

May be isolated from signal ground. SG 7 ↔ Signal Ground. TD(A) TD(B) 2 14 To MUX128/2*64

Serial digital data from DTE. RD(A) RD(B) 3 16 From MUX128/2*64

Serial digital data at the output of the

MUX128/2*64/2*64K receiver.

RTS 4 To

MUX128/2*64

ON signal to the MUX128/2*64/2*64k when data transmission is desired. CTS 5 From

MUX128/2*64

Constantly ON or follow RTS. (DIP SW setting).

DSR 6 From

MUX128/2*64

Constantly ON,

Except during test loops. DTR 20 To MUX128/2*64 Not used. DCD 8 From MUX128/2*64 Constantly ON. ETC(A) ETC(B) 24 11 To MUX128/2*64

A transmitted data rate clock input from the data source.

TC(A) TC(B) 15 12 From MUX128/2*64

A transmitted data rate clock for use by an external data source.

RC(A) RC(B) 17 9 From MUX128/2*64

A received data rate clock for use by an external data source.

CTC Union Technologies Co., Ltd.

Far Eastern Vienna Building (Neihu Technology Park) 8F, No. 60 ZhouZi St. Neihu, Taipei, Taiwan