September 22, 2004
Table of Contents
Introduction ... Page 1 List of Figures ... Page 2 Device Identification
Major Microstructural Analysis Transistor Microstructural Analysis
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AMD
AXDA3000DKV4D
Athlon
TMXP Microprocessor
Structural Analysis
Table of Contents
© 2003 Chipworks Incorporated
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AMD AXDA3000DKV4D Athlon
TMMicroprocessor
Structural Analysis
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Introduction
The AMD AXDA3000DKV4D is an Athlon™ XP microprocessor tailored for Microsoft® Windows® XP. The device runs at 2.167 GHz and incorporates 640 KB of total on die cache. Maximum system bus speed is rated at 333 MHz. The reported die size is 101 mm² and features approximately 54.3 million transistors. The device is packaged in a 462-pin Socket A OPGA (Organic Pin Grid Array) package.
The AXDA3000DKV4D was reportedly manufactured in Dresden, Germany at AMD’s Fab 30 using 0.13 micron copper process technology. The process design featured a full CMP process with nine levels of damascene copper, and one level of polycide. The device analyzed features physical gate lengths measuring 0.07 micron. The device employs Shallow Trench Isolation (STI), and twin wells in a P-epi on a P-type substrate. Cobalt silicide is present on the polysilicon and diffusions (salicide process).
The passivation layer consisted of oxynitride over nitride. All interlevel dielectrics consisted of a thin nitride capping layer over the previous copper layer followed by various depositions of oxide, oxynitride, and nitride. The copper lines and final layer of glass were subjected to CMP. The pre-metal dielectric consisted of an oxynitride sealant dielectric followed by a thick oxide layer.
Cross-sectional analysis of the device structure was performed using a Field Emission Scanning Electron Microscope (FESEM) and a Transmission Electron Microscope (TEM). Analysis of the material composition was achieved with X-ray Energy Dispersive Spectroscopy (EDS).
This report contains the following detailed information:
• Package photographs and x-ray • Die markings and die photograph
• Measurement of vertical and horizontal dimensions of major microstructural features
• FESEM and TEM cross-sectional micrographs of dielectric materials, major features, and
transistors
All the information was derived by Chipworks from the following sample:
Package Markings: AMD Athlon™ AXDA3000DKV4D 9576373250671 AQXCA 0308VPBW
M©1999 AMD
List of Figures
Device Identification 0.1.1 Package Markings 0.1.2 Package X-Ray 0.2.1 Die Markings 0.2.2 Die Photograph 0.3.1 Die Corners0.3.2 Die Corners (Continued)
0.3.3 Bond Pad Layout
0.3.4 Bus Line Layout
Major Microstructural Features
2.1.1 Die Edge
2.1.2 Detail of Edge Seal Ring
2.1.3 Etch Uniformity Patterns
2.1.4 General Device Structure
2.1.5 General Device Structure
2.1.6 Bond Pad to Metal 9 Via
2.1.7 Detail of Bond Pad to Metal 9 Via
2.1.8 Metal 9 Profiles
2.1.9 Detail of Metal 9 Profile
2.1.10 Metal 9 to Metal 8 Vias
2.1.11 Detail of Metal 9 to Metal 8 Vias
2.1.12 Metal 8 Profiles
2.1.13 Detail of Metal 8 Profiles
2.1.14 Metal 8 to Metal 7 Vias
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TMMicroprocessor
Structural Analysis
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2.1.16 Metal 7 Profiles
2.1.17 Detail of Metal 7 Profiles
2.1.18 Metal 7 to Metal 6 Vias
2.1.19 Detail of Metal 7 to Metal 6 Vias
2.1.20 Metal 6 Profiles
2.1.21 Detail of Metal 6 Profiles
2.1.22 Metal 6 to Metal 5 Vias
2.1.23 Detail of a Metal 6 to Metal 5 Via
2.1.24 Metal 5 Profiles
2.1.25 Detail of Metal 5 Profiles
2.1.26 Metal 5 to Metal 4 Via
2.1.27 Detail of a Metal 5 to Metal 4 Via
2.1.28 Metal 4 Profiles
2.1.29 Detail of Metal 4 Profiles
2.1.30 Metal 4 to Metal 3 Via
2.1.31 Detail of a Metal 4 to Metal 3 Via
2.1.32 Metal 3 Profiles
2.1.33 Detail of Metal 3 Profiles
2.1.34 Metal 3 to Metal 2 Via
2.1.35 Detail of a Metal 3 to Metal 2 Via
2.1.36 Metal 2 Profiles
2.1.37 Detail of Metal 2 Profiles
2.1.38 Metal 2 to Metal 1 Via
2.1.39 Detail of a Metal 2 to Metal 1 Via
2.1.40 Metal 1 Profiles
2.1.41 Detail of Metal 1 Profiles
2.1.42 Metal 1 to Polycide Contacts
2.1.43 Detail of a Metal 1 to Polycide Contact
2.1.45 Metal 1 to P+ Diffusion Contact
2.1.46 N-Channel Transistors
2.1.47 P-Channel Transistors
2.1.48 Polycide Structure
2.1.49 Minimum Polycide Spacing
2.1.50 STI/Gate Oxide Transition
2.1.51 STI/Gate Oxide Transition
2.1.52 Minimum Isolation
2.1.53 Polycide on Minimum Isolation
2.1.54 Cache Array
2.1.55 Cache Array
2.1.56 Epi and Well Structure
2.1.57 Detail of N-Well Structure
Transistor Microstructural Analysis
3.1.1 FESEM Micrograph – N-Channel Transistors (Si Etch)
3.1.2 FESEM Micrograph – P-Channel Transistor (Si Etch)
3.1.3 FESEM Micrograph – Polycide Structure (Oxide Etch)
3.1.4 FESEM Micrograph – Polycide Structure (Oxide Etch)
3.2.1 TEM Micrograph – General Device Structure
3.2.2 TEM Micrograph – Detail of ILD Structure
3.2.3 TEM Micrograph – Detail of ILD Structure
3.2.4 TEM Micrograph – Detail of ILD Structure
3.2.5 TEM Micrograph – Detail of ILD Structure
3.2.6 TEM Micrograph – General Device Structure
3.2.7 TEM Micrograph – Detail of Device Structure
3.2.8 TEM Micrograph – Detail of Device Structure
3.2.9 TEM Micrograph – M1 Profile
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TMMicroprocessor
Structural Analysis
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3.2.11 TEM Micrograph – Tungsten Plug – S/D Contact
3.2.12 TEM Micrograph – Detail of Tungsten Plug – S/D Interface
3.2.13 TEM Micrograph – Detail of Tungsten Plug Liner
3.2.14 TEM Micrograph – Tungsten Plug Liner (Half Height)
3.2.15 TEM Micrograph – Detail of Polycide Gate
3.2.16 TEM Micrograph – Gate Oxide
3.2.17 TEM Micrograph – Detail of Polycide Gate
3.2.18 TEM Micrograph –Gate Oxide
3.2.19 TEM Micrograph – Detail of Polycide Gate
3.2.20 TEM Micrograph – Gate Oxide
3.2.21 TEM Micrograph – Detail of Nitride Sidewall Spacers