sta_aot_v07

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Product Version: Virtuoso IC 6.1.6 ISR6, Innovus 15.11- s048_1, QRC 14.23.099,

Tempus 15.11s049_1, Liberate 14.11-s005_1 & Spectre 14.1 ISR10 Workshop Version: 0.7

Date: April 2016

Static Timing Analysis on

Schematic-based Mixed-Signal

Design: Workshop User Guide

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1 Workshop Overview

1.1 Objective of the Workshop

In the analog mixed signal (AMS) designs, digital logic is commonly embedded deep inside the design hierarchy. To analyze the timing of these digital logic paths across different sub-blocks, the AMS design with certain physical and logical levels has to be brought into Innovus to perform static timing analysis (STA).

The main purpose of this workshop is to illustrate how to perform STA on the designs that are in OA database format and are Virtuoso XL-compliant.

First, to verify whether the designs meet the requirements to run STA, it is recommended to run a SKILL utility called OADBChecker in Virtuoso to check the designs prior to running STA. This workshop is intended to help you acquire basic understanding in running the OADBChecker and fixing simple issues to make the design ready for timing analysis.

There are two ways of running STA on the AMS designs. These are explained in this workshop in detail. The first is to flatten the design to a certain physical level so that the timing paths to be analyzed are visible and extractable by Innovus. The second approach is to generate the full timing models (FTM) for the blocks containing the timing paths to be analyzed. The FTM contains the full logical netlist

information and RC parasitic information of the blocks that enable STA to be done in Innovus without the need to feed Innovus the physical layout of the blocks.

After going through this workshop, you will learn how to run STA on an AMS design using the flat approach or the full timing model (FTM) approach. For a design with simple custom logic gates, this workshop has a module to show how to use Liberate to generate timing library for a simple custom logic gate. Finally, there is also an exercise to help you understand how to run STA in Tempus with the OA design to sign off the timing.

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1.2 Overview of the Modules

There are seven modules to run exercises to help you understand the various aspect of running STA on an analog-on-top (AOT) design. In this workshop, there is only one placed-and-routed block not represented by a schematic, and hence not implemented using Virtuoso. The top-level design and all the other blocks are implemented in Virtuoso chip level. Through OA database, the blocks to be analyzed are brought into Innovus to run STA.

One of the main requirements for an OA design to be analyzed and timed by Innovus is XL compliance. For example, XL compliance requires a design to have the PRBoundary object and the wires to have net connection or logical connectivity information. The first module shows how a SKILL-based utility called OADBChecker is used to check the designs for VXL compliance. It also shows how to use

OADBChecker to check for the pipeline character in the instance names. It is quite common to see the name of the instances in the physical layout implemented by Virtuoso containing the pipeline character. For each statement in the timing constraint file, if the timer cannot not find the specified instance name in the layout, the particular constraint statement will get rejected. Thus, you need to ensure that the instance names referenced in the timing constraint file match with the corresponding names in the physical layout. Other important checks shown in this module using OADBChecker are the checks for bus annotation and mosaics.

Generally, you might have two issues when bringing an AOT design into Innovus. The first issue is the handling of Pcells (Parameterized cells) in the design. If certain settings are not done and the Pcell cache is not present, Innovus will not be able to load in the design successfully. The second issue is that of bus annotation when the blocks have bus terminals. The bus annotation affects the connectivity of the design when the loaded design is saved in Innovus. This issue typically occurs on the designs implemented using the older versions of Virtuoso (older than IC615 ISR11). The second module shows how to resolve these issues. The second module also shows how the simple XL compliance issues, such as missing

PRBoundary object and missing net connection for a wire, can be resolved in Virtuoso. Advanced users can go directly to the third module.

The third module provides the step-by-step guidance on how to physically flatten the design to a certain level so that the logical timing paths to be analyzed can be extracted and timed by Innovus. There is detailed explanation on how the flattening process affects the logical and physical hierarchies of the design. In its last section, this module shows how Global Timing Debug, a debugging feature in Innovus, is used to do timing debugging and cross-probing between timing paths and the layout.

The fourth module shows the steps to generate FTM for the sub-blocks and how to run STA at the top level in Innovus using these FTMs. There are some similarities between the flat approach (third module) and the FTM approach (fourth module). Both approaches might require you to use the same Innovus command to perform physical flattening on the design. However, the steps and commands to run timing analysis are different for the two approaches. Major differences between the two approaches will be described in the fourth module.

The fifth module demonstrates a new enhancement introduced in Innovus 14.2. The third module is about selectively specifying the block (names) to be flattened. In this module, you let Innovus identify the list of blocks and sub-blocks of lower levels to be flattened. Innovus is able to automatically flatten the blocks

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that either have the cells bound with the timing libraries or sub-blocks at lower level containing the cells bound with the timing libraries. This new feature makes the run of flattening flow easier.

In the sixth module, there is a custom logic gate in the design that requires the timing library file to be generated in order to run STA. This module shows the steps to run Liberate to characterize this logic gate into a timing library file, and how to add this newly created timing library file to the existing scripts to run STA.

The seventh module illustrates how to run STA in Tempus with the OA-based design. To prepare the design for Tempus, the top-level design is loaded into Innovus and the blocks of interest are flattened. After the flattened design is saved by Innovus, Tempus is invoked to load the saved design. Through the interface provided by Tempus, standalone QRC is selected to run the signoff grade RC parasitic

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1.3 Design and process node

The mixed signal design used in this workshop is a PLL design called Zambezi. It is an analog-on-top (AOT) design consisting mostly of analog blocks and a few digital blocks. In this design, one digital block (LP_pll_dig_wSPI) is implemented using Innovus with a Verilog netlist as input. The rest of the blocks are implemented using Virtuoso with schematic views as input.

The technology process node is GPDK045, based on a 45nm process development kit developed by the internal Flow team at Cadence. It has a standard cell library, gsclib045, which consists of typical standard cells and low power cells such as always-on-buffers, level shifters, and so on. The following diagram shows the physical hierarchy of Zambezi design:

1.3.1 Blocks of interest

The blocks of interest in this workshop are LP_pll_dig_wSPI, pll_fbdiv, LP_pll_dig_combo, and LP_pll. LP_pll_dig_wSPI is a pure digital block. It consists of standard logic cells and is placed and routed in Innovus. This digital block is a low power block with two power domains. The default power domain is an always-on power domain, while the other domain can be shut off. In this workshop, there are logical timing paths to be analyzed, which start from the registers inside this block.

pll_fbdiv is a custom digital block. It consists of standard logic cells and is implemented in Virtuoso. In this workshop, the logical timing paths to be analyzed stop at the registers inside this block.

LP_pll_dig_combo is the parent block of LP_pll_dig_wSPI. It has level shifters that connect the digital block, LP_pll_dig_wSPI to its outside world.

LP_pll is the “top level” design. The LP_pll as the “top level” in Innovus is chosen because this is high enough level to contain the logical timing paths to be analyzed.

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1.3.2 Timing paths of interest

The diagram shows one of the timing constraints. This type of path to be measured is from a register inside a digital block (LP_pll_dig_wSPI) to a register inside a custom digital block (pll_fbdiv). This type of path traverses through a few physical hierarchies, with instances and wires at different levels.

The content of timing constraint to analyze this type of paths in this design is:

set_max_delay 1 -from I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[0]/CK -to |u_fbdiv/u_0_0/D set_max_delay 1 -from I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[1]/CK -to |u_fbdiv/u_1_0/D set_max_delay 1 -from I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[2]/CK -to |u_fbdiv/u_2_0/D set_max_delay 1 -from I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[3]/CK -to |u_fbdiv/u_3_0/D set_max_delay 1 -from I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[4]/CK -to |u_fbdiv/u_4_0/D set_max_delay 1 -from I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[5]/CK -to |u_fbdiv/u_5_0/D You might wonder why there is a “|” (pipeline) character in the timing constraint statements. This is because, in this workshop, the instance names in the layout view have the pipeline character. Innovus builds the connectivity for the design from the layout view. Thus, the instance and pin objects (for

example, |u_fbidv/u_5_0/D) referenced in the timing constraint file must match the actual instance names in the physical layout. If not, Innovus will reject these timing constraint statements.

Another timing path of interest is a register-to-register path inside the pll_fbdiv block. The timing constraint statement for this path is:

create_clock –name clk_in –period 5 [get pins |u_fbdiv/clkin] set_propagated_clock [get_clocks clk_in]

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Note: Timing analysis for this block can also be done at a lower physical design level (pll_fbdiv instead

of LP_pll) because the timing path is local to this block.

The last timing path of interest involves a custom logic gate that has no timing library file initially.

Without the timing library, Innovus sees a broken path between the two registers. There is guidance in the workshop showing how the library characterization can be done on this custom NOR gate.

In summary, this workshop illustrates how you can do static timing analysis on: 1) Timing paths at a global level between different blocks.

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1.4 Database structure

This workshop is built off the AMS Foundation Flow (AMSFF) database, which includes the reference

libraries and design libraries.

Reference libraries (OA) for this workshop are gpdk045 and gsclib045, located at:

LPAMS45_*/TECH/GPDK045/gpdk045 LPAMS45_*/LIBS/GPDK045/gsclib045 LPAMS45_*/LIBS/GPDK045/giolib045

Design Libraries (OA) are zambezi45 located at:

LPAMS45_*/DESIGNS/GPDK045/FRACNPLL/oa/zambezi45

Workshop modules are executed underneath:

LPAMS45_*/WORK/zambezi45/LPMS_WS/AOT_STA

The following terminology convention has been used throughout the document: • Chip level - Refers to LP_pll_chip cell, which has LP_pll block and bondpads

• Top level - Refers to the Current Level of the block you are working on (for example, LP_pll block)

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1.5 Workshop setup

ACTION 1: Untar the database to generate sta_aot_v07/LPAMS45_*/ directory (* stands for

yymmdd_hhmm, the time this DB was built). In the command line, type:

% tar zxf <your download path>/sta_aot_v07.tar.gz

ACTION 2: Initialize the database by fixing any absolute path issues. Configure the database. In the

command line, type:

% cd sta_aot_v07/LPAMS45_*/WORK/zambezi45/LPMS_WS % ./scripts/init.sh

ACTION 3: In the command line, type:

% source proj.cshrc

You have to set the environment variables for product installation paths to your tools path. The tools you have to set are Innovus, Tempus, Virtuoso, Spectre, Liberate and QRC.

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2 Workshop Modules

2.1 Running OADBChecker

In this module, you will learn how to:

1) Find the location of the oaDBChecker SKILL script.

2) Run the oaDBChecker to check for the pipeline character in instance names, bus annotation and VXL compliance such as the presence of PRBoundary object, and whether the wires have the logical connectivity information.

3) View and understand the report generated by the oaDBChecker.

The OADBChecker is a SKILL-based utility that can be run in the Virtuoso environment. It is a file called oaDBChecker.il, which can be found at the sub-directory of the Innovus installation directory:

base_dir/release_number/lnx86/share/innovus/gift/AoT/OAChecker/oaDBChecker.il

Here, base_dir specifies the Innovus installation path, and release_number specifies the Innovus

Implementation System version number.

You will run the oaDBChecker check on three cellviews. Each cellview is modified intentionally to fail certain checks:

1) LP_pll_dig_combo: For this cellview, the OADBChecker will flag the messages on the instances with the pipeline character in names. Some of the bus terminals for this cellview have no bus order (ascending or descending) information. The OADBChecker will flag such a design condition.

2) pll_fbdiv: There is no PRBoundary object in this cellview. It will fail the XL compliance check of the OADBChecker.

3) LP_pll: In this cellview, some shapes (wire) that are part of timing path have no net connection or logical connectivity information. It will fail the XL compliance check of the OADBChecker. There are some mosaics present in the cellview. Although mosaics are not fully interoperable between Innovus and Virtuoso, because of not being part of timing path in this design, the messages flagged by the OADBChecker about these can be ignored.

In summary, some results of the checks done by the OADBChecker indicate the real issue for timing analysis and must be fixed. If not, timing analysis cannot be performed. On the other hand, there are some checks that will not affect timing analysis and are meant more for the interoperable flow that involves changing the design and round tripping between Innovus and Virtuoso.

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2.1.1 Finding the location of oaDBChecker SKILL script

ACTION 1: cd to the working directory for this module and set up cds.lib and others.

% cd AOT_STA/_check_oadb % make setup

% source scripts/oadb_checker.cshrc

ACTION 2: View the content of oadb_checker.cshrc sourced in the previous step. In the UNIX

command line, type:

% more scripts/oadb_checker.cshrc

The content of this file is:

#!/bin/csh -f

setenv OADB_CHECKER_DIR `which innovus |\

sed 's?/tools/bin/innovus?/share/innovus/gift/AoT/OAChecker?'`

ACTION 3: The sourced C-shell script (oadb_checker.cshrc) is written to help locate the

oaDBChecker SKILL script. Verify that the SKILL script, oaDBChecker.il, is found. In the UNIX

command line, type:

% ls $OADB_CHECKER_DIR

The system should return:

oaDBChecker.il

ACTION 4: To see how the locations of the Innovus binary and OADBChecker SKILL script relate

with each other, in the UNIX command line, type the following two statements:

% which innovus

% echo $OADB_CHECK_DIR

Suppose the binary code of Innovus is in:

/icd/flow/INNOVUS/INNOVUS151/15.11-s048_1/lnx86/tools/bin/innovus

As a result, the SKILL script of OADBChecker will be in:

/icd/flow/INNOVUS/INNOVUS15115.11-s048_1/lnx86/share/innovus/gift/AoT/OAChecker

ACTION 5: Copy the SKILL script to current working directory. Type:

% cp $OADB_CHECKER_DIR/oaDBChecker.il .

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2.1.2 Loading oaDBChecker SKILL script into CIW

ACTION 1: Invoke Virtuoso. In the UNIX command line, type:

% virtuoso –log CDS.log1 &

After all the windows are opened, you might want to close What's New in IC6.1.6 Overview by LMB

File from the top menu of its window followed by selecting Close.

ACTION 2: In the Command Interpreter Window (CIW), enter the following:

load "oaDBChecker.il"

The system will respond by showing a t in the CIW. The script is parsed and compiled.

ACTION 3: In the top menu of CIW, select Tools followed by OA DB Checker.

The Innovus Interoperability Checker form will appear. Tools => OA DB Checker

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2.1.3 Running oaDBChecker on LP_pll_dig_combo block

ACTION 1: LMB Design tab near the top-left of the Innovus Interoperability Checker form.

LMB Design Library Checker.

LMB the browser buttons (red boxes with white arrow) to select the following:

Lib: zambezi45

Cell: LP_pll_dig_combo View: layout

In the Report File Name field, edit the filename from oaDBChecker.rpt to oaDBChecker_combo.rpt.

ACTION 2: LMB the OK button near the bottom-right of the form to perform the check.

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ACTION 3: Close the form of Non-Default Rules Report by LMB the Close button at the bottom-right of the form.

ACTION 4: If you prefer using any other type of the text editor, you can close the report file by doing the

following:

Move the mouse cursor to the report file. Type :q and hit the Enter key to close the file.

ACTION 5: Use your preferred text editor to view the report. Look at the first section of the report. It checks for the "|" character in instance names. You will see something like the following:

Performing Check for existence of leading '|' char in instance names.... INFO : Instance '|u_cdmiso' has leading '|' char in its name.

INFO : Instance '|u_pll_dig_wSPI' has leading '|' char in its name. INFO : Instance '|u_ls_rst' has leading '|' char in its name.

This section provides a list of instances that have "|" as the leading character of names. If you continue to scroll down the report, you will see the following:

INFO : Found instances with leading '|' character in the names. This can cause mismatch with names specified in a SDC file. Use envSetVal("layoutXL"

"prefixLayoutInstNamesWithPipe" 'boolean nil) before running schematic driven layout generation process in VLS-XL to avoid creation of such names.

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ACTION 6: In the UNIX command line, type:

% head scripts/LP_pll.sdc –n 3

set_max_delay 1 -from I1/|u_pll_dig_wSPI/u_pll_dig/u_dsm/ls_ndiv_reg[0]/CK -to |u_fbdiv/u_0_0/D

You will notice that the timing constraint file has "|" (for example, |u_pll_dig_wSPI) in the constraint statement. Without the "|" character in the hierarchical name of the instance, the constraint statement will not be accepted by the timer of Innovus. Innovus will report that it cannot find the specified instance in the layout cellview.

ACTION 7: Scroll down to view the next section that checks for bus annotation:

Checking for correct Bus information...

INFO : Found busterm scan_in<1> with busOrder "none" INFO : Found busterm scan_in<0> with busOrder "none" INFO : Found busterm scan_out<1> with busOrder "none" INFO : Found busterm scan_out<0> with busOrder "none" …

This section reports bus terminals that have no bus ordering (ascending or descending) information in the layout database. Without the bus ordering information, Innovus will not be able to make the right

connection.

The next module (module 2.2) will describe how to detect and fix this issue in Innovus.

ACTION 8: Scroll down to view the section that checks for the presence of textDisplay objects.

Because the presence of these objects does not affect static timing analysis, you can disregard the reported error:

Checking for presence of textDisplay objects in the design....

ERROR : Design has textDisplay objects. textDisplay is not supported in Innovus and so it won't be round tripped.

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ACTION 9: Scroll down to view the next section that checks for incompatible wires/wire segments. Again, because the conversion of unsupported wires/wire segments to SPECIALNETS does not affect the static timing analysis (as long as Quantus is able to extract the RC parasitics from the special wires), you can ignore this section:

Checking the incompatible wires/wire segments....

INFO : Signal route from begin point (105.485 48.305) to end point (101.035 48.305) on layer 'Metal3' for net 'ls_atbdec<2>' has variable begin style but the begin width is not valid (For variable style, either the width should be equal to zero or half width of the segment or the minWidth constraint from technology for that layer. …

FAILED: Incompatible wires/ wiresegments found in the design. Unsupported wires/wire segments will be converted into DEF SPECIALNETS. Please look into

"incompatibleWires.rpt" for all the unsupported wire and wire segments.

ACTION 10: Scroll down until the Final Summary is shown:

Final Summary

Type of checks PASSED FAILED --- Design Library Checks:

'|' char in instance names FAILED Bus Annotation check FAILED Power/Ground Checks PASSED

Shapes on drawing purpose PASSED Pins on drawing purpose PASSED Pins on non-routing layer check PASSED

Presence of textDisPlay object check FAILED Validity of gapFill/fill/fillOPC PASSED

Presence of conic shape check PASSED Status of interface bit check PASSED

Unsupported routing shapes FAILED Non default rules check PASSED

Show non default rules PASSED MS constraints check PASSED PCell cache check PASSED Presence of Mosaic check PASSED XL Compliancy check PASSED

The final summary reports show that only four checks failed. Out of this four failures, only two failures (pipeline character and bus annotation) are of concern during static timing analysis.

ACTION 11: Close the text report. For VI editor, enter :q.

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2.1.4 Running oaDBChecker on pll_fbdiv block

ACTION 1: Open the OADBChecker GUI form again from the Tools menu of CIW.

ACTION 2: Make sure the Design tab is selected and Design Library Checker is ticked.

Lib: zambezi45 Cell: pll_fbdiv View: layout

In the Report File Name, edit it to change to oaDBChecker_fbdiv.rpt. Tools => OA DB Checker

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ACTION 3: LMB the OK button near the bottom-right of the form to start the check.

ACTION 4: You can choose to browse the report, oaDBChecker_fbdiv.rpt, if you are familiar with the

VI text editor. Else, you can close the report and use your preferred text editor to open and view the report. Close the Non-Default Rules Report by LMB the Close button at the bottom-right of the form.

ACTION 5: Scroll down the report until you see the following:

Performing Check for existence of non-drawing shapes.... INFO : Routing layer 'Metal4' has shape with purpose 'pin'. INFO : Routing layer 'Metal2' has shape with purpose 'pin'.

INFO : Routing layer 'Metal2' has total 2 shape(s) with purpose other than drawing. INFO : Routing layer 'Metal4' has total 12 shape(s) with purpose other than drawing.

For this cellview, the reported shapes do not affect timing analysis. There are 12 shapes of Metal4 layer used as Labels. There are 2 shapes of Metal2 layer used as the pin shape for power terminals that will also be reported in the next section. You might want to open the cellview {zambezi45 pll_fbdiv layout} to view these.

ACTION 6: Scroll down the report to the next section:

Performing Check for existence of non-drawing pin shapes....

INFO : Terminal 'VDD' has pin shapes with purpose other than drawing. These pin shapes are not inter-operable with Innovus.

INFO : Terminal 'VSS' has pin shapes with purpose other than drawing. These pin shapes are not inter-operable with Innovus.

Innovus will convert to 'drawing' purpose the shapes of terminal (port) that uses 'pin' purpose. Such a conversion does not affect timing analysis. It only affects the round trip back to Virtuoso if the design is opened and saved in Innovus.

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Checking for XL compliancy...

INFO : CellView does not have an associated PRBoundary.

In this case, the cellview fails the XL compliance check because it does not have a PRBoundary object.

ACTION 8: Scroll down to view the Final Summary:

Final Summary

'|' char in instance names PASSED Bus Annotation check PASSED Power/Ground Checks PASSED

Shapes on drawing purpose FAILED Pins on drawing purpose FAILED Pins on non-routing layer check PASSED

Presence of conic shape check PASSED Status of interface bit check PASSED

Unsupported routing shapes FAILED Non default rules check PASSED

Show non default rules PASSED MS constraints check PASSED PCell cache check PASSED Presence of Mosaic check PASSED

XL Compliancy check FAILED

For this cellview, the only concern is failure of the XL compliance check, which is due to the missing PRBoundary object. The next module (2.2), explains how to detect and fix this issue in Innovus.

ACTION 10: Exit Virtuoso. LMB File in CIW and select Exit…. LMB Yes when prompted to exit

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2.1.5 Running oaDBChecker on LP_pll block

ACTION 1: Use your preferred text editor to edit the .cdsinit file. For example, if you prefer to use VI

editor, use:

% vi .cdsinit

ACTION 2: Append the following into the last line of this file. Close the file (:wq for VI editor) once it is done.

load "oaDBChecker.il"

Before appending, the last statement is:

ddsOpenLibManager()

After appending, the last two statements are:

ddsOpenLibManager() load "oaDBChecker.il"

Entering the load statement into .cdsinit ensures that the OADBChecker menu is always available on the CIW when you invoke Virtuoso.

ACTION 3: Invoke Virtuoso. In the UNIX command line, type:

After all the windows are opened, you might want to close What's New in IC6.1.6 Overview by LMB

File from the top menu of its window followed by selecting Close.

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The Innovus Interoperability Checker form will appear.

ACTION 5: LMB the Design tab and tick the box next to Design Library Checker.

Lib: zambezi45 Cell: LP_pll View: layout

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ACTION 6: LMB the OK button near the bottom-right of the form to start the check.

ACTION 7: Close the form of Non-Default Rules Report by LMB the Close button at the bottom-right

of the form.

ACTION 8: You can choose to browse the report, oaDBChecker_lppll.rpt, if you are familiar with the

VI text editor. Else, you can close the report and use your preferred text editor to open and view the report. The results of the following checks will be skipped because these have done in the previous sections:

1) Checking of the pipeline character : Has impact on timing constraint 2) Presence of textDisplay object : No impact on MS-STA

3) Unsupported routing shapes : No impact on MS-STA

Checking for correct Bus information...PASSED.

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ACTION 10: Scroll down the report to view the result of the interface bit check:

Checking for status of interface bit for all blocks in the current view... INFO :Interface bit on terminal 'atbdec_h<1>' of cell 'pll_cp' is set to false. INFO :Interface bit on terminal 'atbdec_h<0>' of cell 'pll_cp' is set to false. INFO :Interface bit on terminal 'atbdec_h<0>' of cell 'pll_reg' is set to false.

…

Setting the Interface bit on terminal to false might affect the connectivity (If there is a connectivity issue, the generated Verilog netlist from Innovus might show missing connection). However, in this design, because you are not going to time any path between the two cellviews (pll_reg and pll_cp) so that the result does not impact MS-STA. In addition, because there is no bus annotation issue reported, it is okay that the interface bit of the bus bit terminal is false.

ACTION 11: Scroll down the report to view the results of NDR check:

Performing Check for completeness of all Constraint Groups (NDRs) in the design.... Checking 'catenaDesignRules' Constraint Group for valid layers, appropriate spacing values etc...

INFO : 'catenaDesignRules' Constraint Group is empty.

WARNING : NDR catenaDesignRules does not have valid layers defined, hence this NDR will not be usable in Innovus.

For MS-STA, this result does not matter because the STA does not involve any routing (re-routing) of nets.

ACTION 12: Scroll down the report to view the results of checking for the presence of mosaics:

Checking for presence of mosaics ...

INFO: Mosaics found in the design. The mosaics will be read in Innovus as scalar instances and will cause loss of connectivity on the instance terminals.

This section of the report indicates that there are mosaic instances in the design. Mosaics are not fully interoperable between Innovus and Virtuoso. View the layout to see the mosaics.

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ACTION 13: Use Library Manager to open up the cellview. LMB the + sign on the left of

FracN_PLL_45 in the Library section to expand it. zambezi45 will appear. LMB zambezi45 to show

the available cells in the Cell section. LMB LP_pll to display all its associated views in the View section. RMB layout in the View section and select Open With… to invoke the Open File form.

Once the Open File form appears, select Open with Layout XL and LMB the OK button near the bottom-right of the form.

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ACTION 14: From the top menu of the layout canvas, LMB Window followed by Workspaces and then select Floorplan. You will see Navigator and Property Editor appear on the left side of the layout canvas. Window Basic Classic Assistants Constraints Toolbars EAD Workspaces Floorplan

ACTION 15: From the top menu of the layout canvas, LMB Tools and select Find/Replace... .

ACTION 16: In the Find/Replace form, use the red button (with white arrow) to select the following

two fields:

Search for array in the current cellview.

LMB Zoom to Figure to enable the zooming to the found figure. LMB Find.

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ACTION 17: LMB Add Select of the Find/Replace form to highlight the figure found first. You will see the tool zoom in and highlight the mosaic found first.

On the left side, the Navigator will indicate that the cell name of the mosaic is pll_bypclf. The Property

Editor also shows some attributes of the mosaic. You might need to expand these to view the entire line.

ACTION 18: In the Find/Replace form, LMB Deselect All followed by the Next button.

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ACTION 19: LMB Add Select of the Find/Replace form to highlight the figure found first. You will see the tool zoom in and highlight the second found figure.

On the left side, the Navigator will indicate that the cell name of the mosaic is pll_bypclf, and the

Property Editor also shows some attributes of the mosaic.

Because all the mosaics found are of the cell, pll_bypclf, and there is no timing path from or to this cell, you do not have to worry about the presence of these. Proceed to view the result of the next check.

ACTION 20: Scroll down the report to view results of the XL compliance check. The first and the last

few statements are shown:

Checking for XL compliancy...

INFO : Shape ((118.83 517.505) (120.04 517.585)) on layer Metal3 found without net connection.

…

ACTION 21: On the layout window, view the wire shape pointed by the last statement of the report by

zooming in (click the right mouse button, hold and draw a box) near the following coordinate: X = 200.0 Y= 395.88

LMB the wire shape (highlighted if clicked) shown on the next page and type q to query the shape Mosaic

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The Route Properties form will appear.

ACTION 22: LMB the Connectivity tab if not already selected.

You will see that the Route Net Name field is empty. This means that this wire has no connectivity information. It will be viewed as a floating net or wire when this cellview is opened in Innovus.

If you further trace this wire, you will notice that these shapes physically connect the terminal ndiv<2> of the pll_fbdiv block to terminal ndiv<2> of the LP_pll_dig_combo block.

Click this piece of wire to query.

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ACTION 23: Move the mouse pointer to the layout window and type f to fit the window. LMB the block

pll_fbdiv. Alternatively, you can LMB the block/instance using the Navigator.

ACTION 24: Under Connectivity of the top menu of the layout canvas, select Nets followed by

Propagate.

The Propagate Nets form will appear.

Select this block. Or click this line.

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ACTION 25: LMB Cancel to close the Propagate Nets form.

ACTION 26: LMB the LP_pll_dig_combo block or select I1 (LP_pll_dig_combo) using Navigator.

Propagate.

The Propagate Nets form will appear.

You might have to scroll down the form to check the connection of terminal ndiv<2>. It can be seen that

ndiv<2> terminal of the LP_pll_dig_combo block is not connected logically either.

Select this block. Or click here.

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ACTION 29: Finally, take a quick look at the Final Summary of the OAChecker report:

Final Summary

'|' char in instance names FAILED Bus Annotation check PASSED

Power/Ground Checks PASSED Shapes on drawing purpose PASSED Pins on drawing purpose PASSED Pins on non-routing layer check PASSED

Presence of conic shape check PASSED

Status of interface bit check FAILED Unsupported routing shapes FAILED Non default rules check FAILED Show non default rules PASSED

MS constraints check PASSED PCell cache check PASSED

Presence of Mosaic check FAILED XL Compliancy check FAILED

For this cellview, you learned how to look for mosaics and wires that have no connectivity information.

ACTION 31: Exit Virtuoso. LMB File in CIW and select Exit…. LMB Yes if prompted to exit Virtuoso.

In this module, you learned to run the OADBChecker to perform several checks on three cellviews and flag out issues that will affect timing analysis. Next module will cover fixing of these issues.

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2.2 Setting up the design for analysis in Innovus

In this module, you will learn how to:

1) Load an AOT design into Innovus using the GUI form. 2) Load an AOT design into Innovus using TCL commands.

3) Set the environment variables to load an AOT Design with Pcells into Innovus.

4) Generate a P-cell cache using Virtuoso and enable Innovus to read a design that has Pcells. 5) Create a Verilog stub netlist using Virtuoso and run verilogAnnotate to handle the bus annotation

issue.

6) Add PRBoundary object to a cellview that has no PRBoundary object, which prevents the cellview from being loaded into Innovus successfully.

7) Fix a simple wire connectivity issue by adding connectivity information to wires in a cellview that makes it XL compliant.

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2.2.1 Loading an AOT design with PCell into Innovus using GUI

% cd AOT_STA/_setup_design % make setup

ACTION 2: Start Innovus. In the UNIX command line, type:

% innovus

ACTION 3: On the top menu of Innovus, LMB File and select Import Design ….

The Design Import GUI form will appear.

ACTION 4: In the Design Import form, under the Netlist: section, select the OA radio button. You can

either type in or use the arrow button (red button with white arrow) on the right to fill in the following for

Netlist: section: Library: zambezi45 Cell: LP_pll View: layout

Under the Technology/Physical Libraries section, fill in the following for OA sub-section: “Reference Libraries:” gsclib045

Alternatively, you can LMB the ellipsis button (…) on the right to open up the Select OA Library form.

LMB the Add… button of the Select OA Library form to open up the Add OA Library form.

Move the scroll bar to select gsclib045 and LMB the OK button of the Add OA Library form. When this is done, gsclib045 will appear in the Select OA Library form (LMB the OK button of the Select OA

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After these steps are done, the Design Import form will look similar to the following. LMB the OK button to start the import.

After the OK button is hit, Innovus starts to load the physical libraries and the design. You will see an ERROR message box pop up after a short while.

You will see the following ERROR message appear in the log file:

**ERROR: (IMPOAX-949): Express Pcell feature is disabled. Check

'CDS_ENABLE_EXP_PCELL' environment variable and any previous messages. .

**ERROR: (IMPOAX-931): Found Pcell instances in the design but Express Pcells are not enabled (Environment variable CDS_ENABLE_EXP_PCELL is not defined). Layout data for the pcell instances can not be read from the pcell cache directory. Enable Express Pcells in the environment and retry.

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These messages mean that the design has Pcells and you need to run some steps before you can invoke Innovus to read the design. You will learn how to generate an ExpressPcell cache and enable ExpressPcell feature in the next section.

ACTION 5: Exit Innovus. In the Innovus command line, type:

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2.2.2 Setting the Pcell environment variables and generating an

ExpressPcell cache

% source scripts/pcell.cshrc

The first step is to set the environment variables. If you open up the file pcell.cshrc in the scripts directory, you will see it basically contains the setting of two environment variables.

setenv CDS_ENABLE_EXP_PCELL true

setenv CDS_EXP_PCELL_DIR ./.expressPcells

The first statement enables the ExpressPCell feature. The second statement instructs Innovus to find the pcell cache in the current .expressPcells directory. You might want to type the following in the UNIX command line to verify these environment variables are stored in the system now:

% env

CDS_ENABLE_EXP_PCELL=true

CDS_EXP_PCELL_DIR=./.expressPcells

ACTION 2: Start Virtuoso to generate the PCell cache. In the UNIX command line, type:

ACTION 3: Use Library Manager to open the cellview zambezi45 LP_pll layout. LMB the + sign on

the left side of FracN_PLL_45 in the Library section to expand it. zambezi45 will appear. LMB

zambezi45 to show the available cells in the Cell section. LMB LP_pll to display all its associated views

in the View section. RMB layout in the View section and choose Open With… to invoke the Open File form.

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ACTION 4: On the top menu of layout window, LMB Tools and select Express Pcell Manager…

The Express Pcell Manager GUI form will appear.

ACTION 5: In the Express Pcell Manager form, enable the two buttons if these are not already enabled:

Enable Express Pcells and Auto Save. You need to keep the Express Pcells directory as

./.expressPcells (to be consistent with the environment variable you set in the previous step). LMB Save Cache to generate the ExpressPcell cache. The form will get updated:

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You might want to run the following optional step in the UNIX command line to verify that there is new data created in the .expressCells directory.

% ls .expressPcells 1ec349a0e31c8c8b11ec49cdb629d61d.cds 3c45bafcc3d0ddd4a1335b40195bb099.cds 98332dc98f1e363d705bf8bd4d4d3ab8.cds cachedPCell_index.cds 30e464275f77faed8ec0f3fbddbc4b2a.cds 483b4e1cfe107a32f01b40def033eb2f.cds 9a3e253122a5a9f8608cf7f847ee1332.cds d0ade7a4fedbf2c23affb0b1fbfc833b.cds 325a6a779dc6a1b1b952fefeeaa0001f.cds 7268cea137c46d4eb6be1acd4aa17943.cds a788211680b89595c06da63442697ee2.cds e1a05f4dfa246a91875022e71c303ab6.cds 367872604d2c8e9d1d90abb47c77907e.cds 83ffc7b5f457e7b5cb45cfa569262133.cds a924b219c2b0b2703044808e9c78c6c1.cds eedde47e45fd3f3011978e98b262eb21.cds 3a4f1c20502136132d4b9cc01cd2642f.cds 87251ab700a93bc8b3a4a73cd0808412.cds c1ac6250ba2c905348e07361cda31185.cds f3bfd69e7789b96069c7777a73ae7ad0.cds 3b1a56cae7c77434c7806db94ed48fdf.cds 8ee98622c327ca8c32ddcd44009f3d29.cds c24c7b906f296f7630648cc06f3b4e68.cds

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2.2.3 Importing an AOT design into Innovus using the TCL command

% innovus –init scripts/load_init.tcl

You have learned how to start Innovus using the GUI form previously. In this section, you will learn how to start Innovus using the TCL command. You need a text file that stores the “init” variables that you entered in the GUI form in the previous exercise. You can open up the load_init.tcl file and see it contains two lines of the TCL command:

source scripts/LP_pll.globals init_design

Open up the “global” file, LP_pll.globals, and you will see the following:

set init_design_netlisttype {OA} set init_oa_design_lib {zambezi45} set init_oa_design_cell {LP_pll} set init_oa_design_view {layout} set init_oa_ref_lib {gsclib045}

The init_design command is to instruct Innovus to read all the “init” variables and start initializing the design.

After Innovus loads the design, you will see a summary of messages:

*** Summary of all messages that are not suppressed in this session:

Severity ID Count Summary WARNING IMPFP-3961 1 The techSite '%s' has no related cells i...

WARNING IMPSYT-7328 1 The design has been initialized in physi... WARNING IMPDB-1256 4 Pin %s of instance '%s' is a POWER type ... WARNING IMPPP-547 5 Cut '%s' does not fit in viaRule '%s'. WARNING IMPOAX-1037 1 There were %d cells with a total of %d p... WARNING IMPOAX-571 1 Property '%s' from OA is a hierarchical ... WARNING IMPOAX-1218 1 Path segment from (%g,%g) to (%g,%g) ass... WARNING IMPOAX-252 1 Found busBit terminals of bus '%s' of ce... …

One WARNING message to be concerned about is IMPOAX-252. The message will be looked into in detail later.

ACTION 2: Open the Innovus main window. In the Innovus command line, type:

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ACTION 3: LMB Log Viewer… under the Tools top menu of the layout window of Innovus.

A GUI form will appear to prompt you to select the log file to view.

ACTION 4: LMB the current Innovus log file. If this is the second time Innovus is running in the current

working directory, select innovus.log1 and LMB Open.

The Log Viewer window will appear. It shows all the TCL commands executed so far.

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ACTION 6: Enter OAX-252 in the Find Text: field. LMB the Find Next button after the entry is done.

The Log Viewer will show more messages now.

Expand the Log Viewer if necessary. You will see the warning message of ENCOAX-252:

**WARN: (IMPOAX-252): Found BusBit terminals of bus 'scan_in[1]' of cell

'LP_pll_dig_combo' without bus ordering information in OA library 'zambezi45'. This may lead to problems during saveOaDesign. It is recommended to run verilogAnnotate on the library for annotating bus ordering information to such terminals.

You see this type of message because, in this Zambezi design, the LP_pll_dig_combo block

implemented by Virtuoso has bus terminals with no bus ordering (ascending or descending) information in the corresponding layout database. Without the bus ordering information, Innovus will not be able to make the right connection. To resolve this issue, you need to generate a Verilog stub netlist for this block. After that, you run an OA utility to annotate the right bus ordering information into the layout database using the Verilog stub netlist as a source.

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ACTION 7: In the Innovus command line, type:

saveDesign –cellview {zambezi45 LP_pll layout_t1}

If you scroll back, you will notice some warning messages similar to the following:

**WARN: (IMPOAX-684): cannot find definition of BUS Term 'vcobnd' of Cell 'LP_pll_dig_combo' in reference library. This could lead to further errors while saving the OA database. Possible reasons could be that VerilogAnnotate is not run on the OA reference library that has the definition for this cell. Either run

VerilogAnnotate on the reference library to fix this problem or use command

'setOaxMode -allowBitConnection true' before saving design to make bitwise connection of terminals.

...

Without resolving the bus annotation issue, you cannot save the design properly into a new cellview in Innovus.

zoomBox 198 395 201 397

You will see the wire connecting to ndiv[2] terminal of the pll_fbdiv block is marked as

_FLOATING_NET_RESERVED. Compared to the wire on its left (ndiv[1]), which connects to the terminal ndiv[1] of the pll_fbdiv block, Innovus does not recognize this net, and will not able to see a connectivity between pll_fbdiv and the other block.

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ACTION 9: LMB the wire (highlighted in the diagram) and enter q to see its attribute.

> savenetlist debug.v

Examine the netlist debug.v. Search for pll_fbdiv and it can be seen that Innovus does not see a

connection between ndiv[2] terminal of the pll_fbdiv block. It becomes FE_UNCONNECTED$1 and

FE_UNCONNECTED$0. LP_pll_dig_combo I1 (.vcocalen(vcocalen), .ndiv({ ndiv[6], ndiv[5], ndiv[4], ndiv[3], FE_UNCONNECTED$1, ndiv[1], ndiv[0] }), … pll_fbdiv \|u_fbdiv (.rst_n(rst_fn), .oclk(oclk), .ndiv({ ndiv[6], ndiv[5], ndiv[4], ndiv[3], FE_UNCONNECTED$0, ndiv[1], ndiv[0] }),

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In this section, you learned how Innovus responds to missing bus order information and the wire that does not have net connectivity. In the following sections, you will learn how to:

1) Generate a Verilog stub netlist using Virtuoso.

2) Annotate the bus ordering information to the design using an OA utility called

VerilogAnnotate so that Innovus can read the bus terminals with the right order.

3) Fix the connectivity issue for the wire connecting ndiv[2] terminals of the pll_fbdiv and

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2.2.4 Generating a Verilog stub netlist and adding net connection to

wire

ACTION 1: Start Virtuoso. In the UNIX command line, type:

ACTION 2: Open up the cellview: zambezi45 LP_pll_dig_combo schematic.

Open with: Schematics L.

After LMB the OK button of the Open File GUI form, the schematic window will appear.

ACTION 3: On the top menu of Virtuoso Schematic Editor, LMB Create and select Cellview, followed

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The Cellview From Cellview form will appear.

ACTION 4: In the Cellview From Cellview form, select Verilog-Editor for Tool/Data Type. In To

view Name field, enter verilog_stub as shown in the following screenshot. LMB the OK button.

The steps are to create a new cellview (zambezi45 LP_pll_dig_combo verilog_stub).

ACTION 5: If the following message box appears, LMB Close to close it.

You will see a window similar to the screenshot in the following page. Basically, it shows the content of a Verilog netlist that contains only the input and output port definitions of the LP_pll_dig_combo module.

% ls stubs

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There are two stub files created for the LP_pll and LP_pll_dig_combo cellviews. If you open up

LP_pll_dig_combo_stub.v, you will see the same content as before. These Verilog stub files in the stubs

directory are pre-created files generated by running the previous steps.

ACTION 7: Use Library Manager to open up the cellview:

Library: zambezi45 Cell: LP_pll View: layout

Open with: Layout XL.

LMB the OK button near the bottom-right of the Open File form.

ACTION 8: From the top menu of the layout canvas, LMB Window followed by Workspaces and then

select Floorplan.

Window

Basic Classic Assistants Constraints

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You will see Navigator and Property Editor appear on the left side of the layout canvas. If necessary, expand the width of Navigator to clearly see the instance and cell name.

ACTION 9: Zoom in the layout window to view a floating wire. The coordinate of its lower left corner is

X = 200.0 Y= 395.88.

LMB the wire shape (highlighted if clicked) shown on next page and type q to query the shape property.

The Route Properties form will appear.

ACTION 10: LMB the Connectivity tab if not shown.

You will see similar thing in the Property Editor. The right field of + Route Net … is empty. LMB this piece of wire to query.

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ACTION 11: Enter ndiv<2> into the Route Net Name field and LMB the OK button.

By adding the net connectivity information, the tool will be able to trace and see the connectivity between the terminals ndiv<2> of the pll_fbdiv and LP_pll_dig_combo blocks. Verify these in the next few steps.

Now the Property Editor shows that the wire has a net name:

ACTION 12: Move the mouse to the canvas and type f to fit the window. LMB the block pll_fbdiv as

shown in the following image (Alternatively, you can LMB the block/instance using the Navigator):

Select this block. Or LMB here.

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Propagate.

You will see that the terminal ndiv<2> of the pll_fbdiv block is now connected to the net ndiv<2>.

ACTION 15: LMB the LP_pll_dig_combo block, or select it through Navigator.

Select this block. Or LMB here.

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Propagate.

You might have to scroll down the form to check the connection of terminal ndiv<2>. It will now be connected to ndiv<2>.

ACTION 17: LMB File from the top menu of the layout window and select Save to save the cellview.

ACTION 18: Close the windows of all schematic, layout cellview and Library Manager by LMB File of

the top menu and selecting either Close or Exit. Exit Virtuoso by LMB File in CIW and selecting Exit…. LMB Yes when prompted to exit Virtuoso.

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2.2.5 Running verilogAnnotate

In this section, you will learn to run verilogAnnotate to annotate the bus order information for the

LP_pll_dig_combo block using the Verilog stub file in the stubs directory.

%source scripts/verilog_annotate.cshrc

*********************************************************************** Tool: verilogAnnotate 22.43.033

***********************************************************************

Running: verilogAnnotate -verilog "stubs/LP_pll_dig_combo_stub.v" -libDefFile cds.lib -refLibs "zambezi45" -refViews "layout"

Started: xxx xx xx:xx:xx 2015 (Hostname: xxxx-xxxxxx) Finished: verilogAnnotate

Time elapsed: x.xx seconds CPU Time: x.xxxxxx seconds System Time: x.xxxxxx seconds Peak VM: xxxxxxx bytes

Messages: 0 errors, 0 warnings

When you open up verilog_annotate.cshrc, you will see the following content:

verilogAnnotate -verilog stubs/LP_pll_dig_combo_stub.v -refLibs zambezi45 -libDefFile cds.lib -refViews "layout"

% innovus –init scripts/load_init.tcl

By looking at the message summary, verify that Innovus no longer issues the IMPOAX-252 message.

win

zoomBox 198 395 201 397

LMB this wire and type q to verify that the wire has net information. Not floating anymore

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> savenetlist debug.v

Examine the debug.v netlist and it can be seen that Innovus now sees a connection between ndiv[2] terminals of the pll_fbdiv and LP_pll_dig_combo blocks:

wire [6:0] ndiv; LP_pll_dig_combo I1 (.vcocalen(vcocalen), .ndiv(ndiv), … pll_fbdiv \|u_fbdiv (.rst_n(rst_fn), .oclk(oclk), .ndiv(ndiv),

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2.2.6 Opening a cellview with no PRBoundary

% innovus –init scripts/pll_fbdiv_init.tcl

The purpose is to load the cellview of {zambezi45 pll_fbdiv layout} into Innovus. The content of pll_fbdiv_init.tcl is:

source scripts/pll_fbdiv.globals init_design

And the content of the pll_fbdiv.globals file is:

set init_design_netlisttype {OA} set init_oa_design_lib {zambezi45} set init_oa_design_cell {pll_fbdiv} set init_oa_design_view {layout} set init_oa_ref_lib {gsclib045}

> win

Due to insufficient data, there is nothing to see in the main window. In the log file, there is an error message:

**ERROR: (IMPOAX-815): PRBoundary is not present in OA design. Cannot restore the design from given OA database. Add the PRBoundary information to the cellview and retry loading the database.

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> man IMPOAX-815

You will see a more detailed description of the error message:

DESCRIPTION

While reading an OpenAccess database into Innovus from the layout in Virtuoso, user gets the above error with the oaIn command and is unable to load the OpenAccess database into Innovus.

The error is stating that the PRBoundary object is not present in the OpenAccess database.

In order to resolve this, user needs to add the PRBoundary object. Adding a shape on prBoundary:boundary LPP (layer purpose pair) to the Layout does not work, the boundary must be the correct object type. User needs to add it interactively through this Virtuoso menu command in the layout.

Example on Virtuoso menu command in the layout : Create -> P&R Objects -> P&R Boundary.

This is equivalent to the DIEAREA in DEF.

In the section, you will fix the problem by following the instructions in this message.

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2.2.7 Adding PRBoundary into a cellview

ACTION 1: Start Virtuoso. In the UNIX command line, type:

ACTION 2: If Library Manager is not opened, LMB Tools inside CIW to invoke Library Manager.

Open up the cellview: zambezi45 pll_fbdiv layout.

ACTION 3: When the Open File GUI form appears, select Layout XL and LMB the OK button.

The canvas will show the layout of the pll_fbdiv cellview.

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ACTION 5: Use the left mouse key to draw a PRBoundary object (click, hold, draw a box and release the

mouse button) that covers all the placed and routed objects. At this point, do not worry about the coordinates of the corners or the size of the PRBoundary. The size will be fine-tuned later.

ACTION 6: On the left side of the layout canvas, check if the Objects window appears. Expand

Boundaries to view P&R Boundary, and check if the corresponding V (viewable) and S (selectable)

buttons are clicked. If not, LMB the button to enable it.

ACTION 7: Use the left mouse key to select the PR Boundary object and click q (to query). Edit the

Points field to match the following:

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ACTION 8: Save and close the cellview. If prompted to save the changes made, LMB Yes.

Virtuoso.

ACTION 10: Load the cellview again in Innovus. In the UNIX command line, type:

% innovus –init scripts/pll_fbdiv_init.tcl

> win

With the PR Boundary object existing, you are able to view and analyze the layout now. Exit Innovus. In the Innovus command line, type:

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2.3 Running STA on an AOT design in Innovus using the flat approach

In this module, you will learn:

1) How to run assembleDesign to physically flatten a block within an AOT design so that the instances and wires inside the block are brought to the top level.

2) How does assembleDesign affect the physical hierarchy of the cellview that gets flattened. 3) How does assembleDesign affect the logical hierarchy of the cellview that gets flattened. 4) What are the commands run to analyze the timing of a low power design with multiple power

domains after assembleDesign.

5) How to use Global Timing Debug to debug timing and perform cross-probing between the layout and timing report.

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2.3.1 Examining the design

% cd AOT_STA/_flat_sta % source scripts/pcell.cshrc % make setup

ACTION 2: Start Innovus. In the UNIX command line, type:

% innovus –init scripts/flat.tcl

You might want to view the content of flat.tcl in the scripts directory. The first few lines in this file are:

source scripts/LP_pll.globals setOaxMode -allowAnalysisOnly true init_design

The content of LP_pll.globals in the scripts directory is:

set init_design_netlisttype {OA} set init_oa_design_lib {zambezi45} set init_oa_design_cell {LP_pll} set init_oa_design_view {layout} set init_oa_ref_lib {gsclib045}

set init_mmmc_file {scripts/LP_pll.viewDefinition.tcl} set init_pwr_net {dvdd avddlf avddhf avdd_h VDDsw} set init_gnd_net {dgnd agndlf agndhf agnd_h}

In this .globals file, you specify the design library, and cell and view names through three variables (init_oa_design_lib, init_oa_design_cell and init_oa_design_view). The standard cell library,

gsclib045, is specified through the init_oa_ref_lib variable so that Innovus reads all the abstract

cellviews in this library for the standard cells.

Note that you have a variable init_mmmc_file that points to LP_pll.viewDefinition.tcl for the LP_pll block. This viewDefinition.tcl file contains the multi-mode, multi-corner specification for the LP_pll block. The specification includes the timing libraries for the logic standard cells for each power domains and QRC technology files to do RC extraction. The specification also lists the timing constraint file (LP_pll.sdc), which resides in the scripts directory.

Note: After the init_design command is run, you will see Innovus issue some warning and error messages

(for example, TCLCMD-513, TCLCMD-1170, TCLCMD-917, TCLCMD1109) in the log file when it reads the timing constraint file. This is expected because, at this stage, the design does not have the specified instances at the top level. These specified instances are at a lower physical level and not seen by Innovus. In the subsequent steps, you will run some actions to understand why Innovus does not see these instances, and issues these messages.

The setOaxMode –allowAnalyaisOnly true statement is for later use when running the assembleDesign command to flatten blocks.

sta_aot_v07

Static Timing Analysis on

Schematic-based Mixed-Signal

Design: Workshop User Guide

Contents

1

Workshop Overview

1.1 Objective of the Workshop

1.2 Overview of the Modules

1.3 Design and process node

1.3.1 Blocks of interest

1.3.2 Timing paths of interest

1.4 Database structure

1.5 Workshop setup

2

Workshop Modules

2.1 Running OADBChecker

2.1.1 Finding the location of oaDBChecker SKILL script

2.1.2 Loading oaDBChecker SKILL script into CIW

2.1.3 Running oaDBChecker on LP_pll_dig_combo block

2.1.4 Running oaDBChecker on pll_fbdiv block

2.1.5 Running oaDBChecker on LP_pll block

2.2 Setting up the design for analysis in Innovus

2.2.1 Loading an AOT design with PCell into Innovus using GUI

2.2.2 Setting the Pcell environment variables and generating an

ExpressPcell cache

2.2.3 Importing an AOT design into Innovus using the TCL command

2.2.4 Generating a Verilog stub netlist and adding net connection to

wire

2.2.5 Running verilogAnnotate

2.2.6 Opening a cellview with no PRBoundary

2.2.7 Adding PRBoundary into a cellview

2.3 Running STA on an AOT design in Innovus using the flat approach

2.3.1 Examining the design