ACTION 1: In the UNIX command line, type:
% innovus
ACTION 2: In the Innovus command line, type:
> source scripts/LP_pll.globals
> init_design
Source the global file and run the init_design command to load the libraries and design.
Note: You can cut and paste from ftm_sta.tcl in the scripts directory.
ACTION 3: In the Innovus command line, type:
> setDesignMode -process 45
> setExtractRCMode -engine postRoute -effortLevel high -lefTechFileMap scripts/QRC_LEF.layermap_10lm.new
ACTION 4: In the Innovus command line, type:
> specifyIlm -cell LP_pll_dig_combo -dir LP_pll_dig_combo_FTM
> specifyIlm -cell pll_fbdiv -dir pll_fbdiv_FTM
> flattenIlm
The specifyIlm command is to instruct Innovus where to find the Verilog netlist and SPEF file for the corresponding block. The flattenIlm command switches Innovus from the default blackbox mode into ILM mode in which the netlist and SPEF of the FTM are read by Innovus. Under this mode, Innovus sees the instances and nets inside the FTM blocks. Thus, the timer of Innovus is able to see the logical
connection from the instance inside the LP_pll_dig_wSPI block to another instance, pll_fbdiv block (through the additional Verilog netlist provided by the FTM block). The RC parasitic information in the FTM blocks is back-annotated by the timer of Innovus for timing delay calculation.
ACTION 5: In the Innovus command line, type:
> loadCPF scripts/LP_pll.cpf
> commitCPF -keepRows
ACTION 6: In the Innovus command line, type:
> setObjFPlanBox group PD_cal 8.4 384.73 91.6 442.92
> setObjFPlanBox group pd_avddlf_agndlf 189.455 377.31 212 398 This is for the floorplan shape for the power domains.
ACTION 7: Display the layout window. In the Innovus command line, type:
> win
ACTION 8: On the top menu of Innovus, LMB Tools and select Design Browser…. Type in I1/*pll* in the Find Instance field of Design Browser and press the Enter key. *
This step is to show that Innovus has the netlist information of the digital block (LP_pll_dig_wSPI) in its database. The hierarchical module for this is I1/u_pll_dig_wSPI. You might want to do the same for the pll_fbdiv block by entering *fbdiv* in the Find Instance field of Design Browser.
ACTION 9: Dump out the Verilog netlist of the LP_pll block including the FTM netlist of the pll_fbdiv and LP_pll_dig_combo FTM blocks. In the Innovus command line, type:
ilmView 1> saveNetlist –ilm LP_pll_ilm.v
Note that the –ilm option can only be run in the ILM mode (after flattenILM). This command can be used to debug if the FTM netlist is being read into Innovus database properly.
ACTION 10: In the Innovus command line, type:
ilmView 2> update_constraint_mode -name PM_cal -ilm_sdc_files {scripts/LP_pll.sdc}
Once flattenIlm is run, Innovus enters into the ILM mode. In this mode, Innovus sees more instances and nets due to the addition of netlist from the LP_pll_dig_combo and pll_fbdiv FTM blocks. Thus, you have to specify the SDC file for the ILM mode, which is different from the default mode. Without doing this step, when you report_timing later, Innovus will return:
No constrained timing paths found.
ACTION 11: In the Innovus command line, type:
ilmView 3> set_global report_timing_format {instance arc cell delay arrival required annotation voltage}
ACTION 12: In the Innovus command line, type:
ilmView 4> report_timing -to |u_fbdiv/u_1_0/D Innovus will show the timing report in the log file:
From the timing report, it can be seen that the instances in the lower-level hierarchy of the pure digital block LP_pll_dig_wSPI (instance is I1/|u_pll_dig_wSPI) and custom digital block pll_fbdiv (the instance name is |u_fbdiv) are visible from the timing perspective.
ACTION 13: In the Innovus command line, type:
ilmView 5> report_timing -from |u_fbdiv/u_divclk/CK Innovus will show the timing report in the log file:
Path 1: MET Setup Check with Pin |u_fbdiv/u_0_0/CK
Endpoint: |u_fbdiv/u_0_0/D (^) checked with leading edge of 'clk_in' Beginpoint: |u_fbdiv/u_divclk/QN (v) triggered by leading edge of 'clk_in' Path Groups: {clk_in}
Note: In the FTM approach, both the LP_pll_dig_combo and pll_fbdiv blocks are not physically flattened (Innovus sees the timing perspective only through the Verilog netlist and SPEF). Thus, in the layout window, you do not see the instances and wires of both the blocks appearing at the top level. This is one of the main differences between the flat and FTM approaches.
The following table shows a comparison between the FTM and flat approaches.
FTM Flat
No assembleDesign on top level Runs one or more assembleDesign till the instances are seen on top level
How the block is represented
The block is represented by a Verilog netlist and SPEF file(s) for the RC parasitic that makes it portable.
Does not require to write out the logical connectivity in the Verilog netlist and RC parasitic in the form of SPEF Usability and
Debugging
Useful only when the Verilog netlist and SPEF file of a block (IP) are available (no layout view is given) Instances and timing path inside FTM block are not visible in layout window specifyILM and flattenILM commands are to be run prior to running report_timing.
Requires layout view of the block
Able to see instances on the layout window
Does not require to create the FTM
ACTION 14: In the Innovus command line, type:
ilmView 6> unflattenIlm
This step is to return to the blackbox mode in which Innovus does not see the instances inside the FTM block. You will expect to see some ERROR messages. (For example, ENCMSMV 1521 and ENCDB-1212). These error messages are expected because, after unflattening, the instances inside the FTM blocks are not visible. Hence, certain content of the CPF is not valid in the current blackbox mode.
ACTION 15: Exit Innovus. In the Innovus command line, type:
> exit