ACTION 17: In the Innovus command line, type:
> assembleDesign –block {zambezi45 LP_pll_dig_wSPI layout} -keepPinGeometry ACTION 18: In the Innovus command line, type:
> zoomBox -4 350 237 536
After one more round of assembleDesign, you see the standard cells inside the LP_pll_dig_wSPI block appear in the Innovus window.
ACTION 19: Quit the Design Browser by LMB the x button and reopen it. LMB the + sign of PowerDomains to expand it.
In the Design Browser, it shows only one power domain (PD_cal). This is not right.
ACTION 20: In the Innovus command line, enter the following two commands:
> loadCPF scripts/LP_pll.cpf
> commitCPF -keepRows
You have to load and commit the CPF (Common Power Format) file because CPF provides information about the power domain an instance belongs to. It is possible that an instance placed in one power domain and another instance placed in another power domain are of the same cell type (same physical design).
However, when these are placed in different power domains with connections to different power signals (one is dvdd and the other is VDDsw), a CPF is necessary to let Innovus know which timing library set it should use for these two instances. In this design, the digital block (LP_pll_dig_wSPI) and custom digital block (pll_fbdiv) are driven with different supply voltages. Based on the CPF file, Innovus knows which library sets to pick (0.9V and 1.1V timing libraries for the digital block and 1.08V and 1.32V timing libraries for the custom digital block) to do multi-corner timing analysis.
The main purpose of specifying the –keepRows option is to instruct Innovus to keep the rows of the digital block (LP_pll_dig_wSPI). It is recommended to use this option for commitCPF in the hierarchical flow (after assembleDesign is used). Without this option, the default behavior of
commitCPF will remove and recreate the existing rows. If rows of the assembled block is not aligned with the rows on the top, the newly create row will get misaligned with the instances:
Top edges not aligned
The following table shows the main definition of the CPF macromodel for each hard block:
pll_cdsmiso 1.0 V dvdd dgnd pd_dvdd_dgnd @1.0V
pll_cp 1.2V, 2.5V
pll_reg 2.5V vdd_h agnd_h pd_avdd_h_agnd_h @2.5V
The following table shows a quick overview of the nominal voltage and power mode definition at the top level:
The following table shows the power domains and corresponding instances that you are interested in this timing analysis exercise:
Power Domains Instances Description
PD_def Default Default power domain
PD_cal I1/|u_pll_dig_wSPI/u_pll_dig/u_rcal, I1/|u_pll_dig_wSPI/u_pll_dig/u_vcocal
Shut off power domain for modules inside pure digital block
pd_avddlf_agndlf |u_fbdiv, |u_pfd, I1/|u_ls_rst, I1/|u_ls_ndiv[0], I1/|u_ls_ndiv[1],
ACTION 21: In the Innovus command line, enter the following three commands:
> setObjFPlanBox group pd_avddlf_gndlf 189.455 377.31 212 398
> modifyPowerDomainAttr pd_avddlf_agndlf –addBlockBox {|u_pfd}
> modifyPowerDomainAttr pd_avddlf_agndlf –addBlockBox {{ I1/|u_ls_rst I1/|u_ls_ndiv(0)
I1/|u_ls_ndiv(1) I1/|u_ls_ndiv(2) I1/|u_ls_ndiv(3) I1/|u_ls_ndiv(4) I1/|u_ls_ndiv(5) I1/|u_ls_ndiv(6) }}
Note: In the CPF file, these instances (for example, |u_fbdiv) are specified as instances belonging to the pd_avddlf_agndlf power domain. These instances are placed in Virtuoso. Innovus is not going to replace these because this workshop is a timing analysis exercise that involves no place and route operation. It is recommended to specify the floorplan shape for this power domain using the command such as
setObjFPlanBox or modifyPowerDomainAttr. It does not matter whether the blocks are fully placed inside the power domain shape. However, you should at least specify a physical location or boundary for Innovus to understand where this power domain should be placed physically.
ACTION 22: Quit Design Browser and reopen it. LMB the + sign of PowerDomains to expand it. Now, the Design Browser shows multiple power domains.
ACTION 23: LMB the All Colors button in the layer control section. The Color Preferences form will appear. LMB the Custom tab. Turn off the Psub layer by LMB the S button followed by V buttons next to it. LMB the Close button at the bottom of this form to close the Color Preferences form.
ACTION 24: Zoom to the pll_fbdiv block:
> zoomBox 184 373 214 402
You see the pll_fbdiv module has a different power domain: pd_avddlf_agndlf.
Psub Layer
ACTION 25: In the Design Browser, expand the + sign next to pd_avddlf_agndlf. Further expand
|u_fbdiv and its StdCells. You will see the names of all the cells of the |u_fbdiv block, which belongs to the pd_avddlf_agndlf power domain.
ACTION 26: Generate Verilog netlist. In the Innovus command line, type:
> saveNetlist LP_pll_asm2.v
The netlist now has more levels of module hierarchy.
For example, you can view how each module is defined and instantiated under the following logical hierarchy order:
LP_pll (top level)
=> LP_pll_dig_combo => LP_pll_dig_wSPI => LP_pll_dig => pll_dig_dsm => ls_ndiv_reg[0]
The key content of the netlist is:
module LP_pll_dig_wSPI (…
LP_pll_dig u_pll_dig (.FE_OFN37_scan_en(FE_OFN37_scan_en),
…));
endmodule
module LP_pll_dig (…
pll_dig_dsm u_dsm (…
…));
…
module pll_dig_dsm (…
SDFFRHQX1 \ls_ndiv_reg[0] (.SI(ls_ndiv[1]), …));
… endmodule
module pll_fbdiv (…
…
endmodule
module LP_pll_dig_combo (…
LP_pll_dig_wSPI \|u_pll_dig_wSPI (.pmc(pmc),
…));
endmodule
module LP_pll (…
pll_fbdiv \|u_fbdiv (.rst_n(rst_fn), …);
LP_pll_dig_combo I1 (vcocalen, …);
… endmodule
You can expand the Design Browser to view the module hierarchy (Tip: minimize PowerDomains and keep expanding Modules).
Here is a summary of what assembleDesign does to the design:
1) It physically flattens the selected block and brings up all the instances and wires inside the block to the top.
2) In the logical connectivity, it increases the level of logical (or modular) hierarchy. In this example, before assembleDesign, Innovus sees only one module. After assembly, the digital block
LP_pll_dig_wSPI that has embedded modular hierarchy is preserved and becomes visible to Innovus.
3) It flattens one physical level of hierarchy for each specified block.
ACTION 27: Turn on the two NET buttons under the layer control section. Expand NET and disable Special Net under the Net section.
ACTION 28: Zoom to the timing path between the LP_pll_dig_wSPI and pll_fbdiv blocks. In the Innovus command line, type:
> zoomBox 81 355 231 535
> source scripts/selectnet.tcl
The content of the file, selectnet.tcl, is:
selectNet ndiv[1]
selectNet |u_fbdiv/i_ndiv[1]
selectNet |u_fbdiv/i_cnt[1]
selectNet I1/ls_ndiv[1]
This script is to highlight all the nets of one timing path.
ACTION 29: You can LMB View on the top menu and select Dim Background. It improves the visibility with the selected wires highlighted while the display of the rest dimed. You will get the following left screen by doing the Dim once. Do Dim once more to get the right screen as shown in the following screen:
You can see that the design is ready for extraction now. All the instances and wires are visible and extractable by Innovus.
ACTION 30: Do Dim Background once to revert to the original display (no dimming).