Multiplexer based High Speed Double Precision Floating Point Multiplication
1
K V Gowreesrinivas,
2P Samundiswary
1
Research Scholar,
2Assistant Professor,
1,2
Dept. of Electronics Engg.
Pondicherry University, Puducherry, India
ABSTRACT
In this paper, double precision floating point multiplication is designed and analyzed using two algorithms such as karatsuba algorithm and vedic algorithm. Different modified 2x1 multiplexer techniques are incorporated in both Karatsuba and vedic algorithms to improve the speed. Further, the comparative analysis is made for both algorithms in terms of speed and area. From the results, it is inferred that double precision floating point multiplication with karatsuba algorithm using modified 2x1 multiplexer model V offers improved performance with high speed along with improvised in area utilization. than that of existing techniques. All the blocks involved for floating point multiplication are coded with Verilog and synthesized using Xilinx Vivado Tool.
Keywords— Vedic multiplier, Karatsuba Algorithm, 2x1 Multiplexer,Verilog
I. INTRODUCTION
In present scenario, lots of work is going on miniaturization with the cost of speed and power dissipation. In general, any digital based real time electronic system has many computations in its logic implementation. For example, in case of any Digital Signal Processing application, requires the computations in the form of additions and multiplications. Usually, multiplication takes more resources and also time. In this aspect, different algorithms are developed to improve the performance of multiplication block alone. In this regard, algorithms like karatsuba and vedic are developed. These algorithms are used in double precision floating point multiplication to improve the performance metrics such as area and speed[1-4].
IEEE double precision floating point format is a computing format that occupies 8-bytes (64- bits) in computer memory. In IEEE 754-2008 standard 64-bit binary format is also named as binary 64[5-6]]. In this paper, standard cell based optimization is tailed which place the main part in performance improvement for high level abstraction. Different 2x1 multiplexer based modified logics are used in place of full adder design to improve the performance. For this, previously different methods such as ripple carry adder based addition and 4x1 multiplexer based additions are performed [7] in conventional multiplier architectures
This article described as follows, Section 2 illustrates the existing work on double precision floating point multiplication and section 3 presents modified models of 2x1 multiplexer, section 4 explains about simulation results followed by conclusion which is described in section 5.
II. Existing Work
Mantissa multiplication is the main block in floating point multiplication, which influence the overall performance. For the double precision floating point number, 53-bits length mantissa multiplication is required and it decides the performance[8]. In literature, different algorithms are introduced in multipliers to improve the speed and area [8-10].In this work, multiplexer based techniques are replaced in the place of full adder are incorporated in double precision floating point multiplication. The multiplication using proposed multiplexer based methods gives better results in
compared with existing vedic multiplier results. The implementation is done by using Xilinx Vivado tool.
Figure 1: Floating Point number representation
III. PROPOSED WORK
In this work, double precision floating point multiplication is designed and analyzed by using different models of full adder using 2x1 multiplexer logic, which is used in both Karatsuba and Vedic multipliers. Finally, the performance comparison is made between Vedic and Karatsuba based double precision floating point multiplication for existing and proposed techniques in respect of speed and area.
3.1 Proposed 2x1 multiplexer based full adder designs:
Full adder is designed using the combination of logic gates and 2x1 multiplexer. From figure 2 to 9, represents full adder designs which are used in multiplication algorithms such as vedic and Karatsuba.
Figure 2: Double Precision Floating Point multiplication diagram
Figure 3: Full adder using 2x1 Mux Model I Figure 4: Full adder using 2x1 Mux Model II
Figure 5: Full adder using 2x1 Mux Model III Figure 6: Full adder using 2x1 Mux Model IV
Figure 7: Full adder using 2x1 Mux Model V Figure 8: Full adder using 2x1 Mux Model VI
Figure 9: Full adder using 2x1 Mux Model VII Figure 10: Full adder using 2x1 Mux Model VIII
From the figure 3, in Model I, Full Adder (FA) is designed using 2- 2x1 multiplexers and 4-basic logic gates. Sum output is derived using one 2x1 multiplexer, NOT and XOR gates, carry output is derived using one 2x1 multiplexer, AND and OR logic gates. Similarly, figure 4 illustrated that, full adder is implemented with two 2x1 multiplexers and two logic gates. Sum output is realized using one 2x1 multiplexer and one XOR gate, carry output is realized using one 2x1 multiplexer and AND logic gates. In terms of transistor count, this design utilizes 10T to get sum and carry outputs.
From the figure 5, in Model 3, FA is developed by retaining 2-stages of XOR gates for the sum output and one XOR and one Multiplexer is involved in getting carry output, which is shown in figure 5. Similarly, figure 6 illustrated that, full adder is implemented with five 2x1 multiplexers and two inverters. Sum output is realized using two 2x1 multiplexers and two inverter gates, carry output is realized using three 2x1 multiplexers.
From figures 7, in Model 5, FA is designed by using 2-XNOR gates and one 2:1 Multiplexer.
Sum output is derived using 2-XNOR gates, carry output is realized using one 2x1 multiplexer and 1- XNOR logic gate. In terms of transistor count, this design utilizes 06T to get sum and carry outputs.
From figures 8, full adder is realized using one XOR and XNOR gate and two 2:1 Multiplexers. Sum output is realized using one XOR and one XNOR gate and one 2x1 Mux, carry output is realized using one 2x1 multiplexer and one XOR logic gate. In terms of transistor count, this design utilizes 08T to get sum and carry outputs.
From figures 9, in Model 7, full adder is employed with one XNOR gate and two 2:1 MUX. Sum
using one 2x1 multiplexer and one XOR logic gate. In terms of transistor count, this design utilizes 10T to get sum and carry outputs. From figures 10, full adder is implemented with one XNOR and two AND gates and one 2:1 Multiplexer and one OR gate. Sum output is realized using one XOR and one 2x1 Mux, carry output is realized using two AND logic gates one OR gate and one Inverter. In terms of transistor count, this design utilizes 14T to get sum and carry outputs.
IV. SIMULATION RESULTS
The double precision floating point multiplication developed and analyzed using Verilog HDL programming language and further the synthesis of the different multipliers are performed by using Vivado tool. The performance constraints such as speed and area are compared. Functionality verification of Vedic multiplication using multiplexer and compressors are performed and results are summarized
Figure 11: Karatsuba algorithm RTL Diagram Figure 12: Full Adder using Model I RTL Diagram
4.1 Comparison Analysis
From the comparison table 1, it is noticed that floating point multiplication with 2x1 multiplexer of model-V provides reduced delay but optimized performance in area. From the comparison table-4, it is noticed that floating point multiplication with 4:2 compressor using XNOR- XOR-MUX combination achieves reduction in area and power but optimized delay. In this paper, Vedic multiplier using 4:2 compressor with XNOR-XOR-MUX logic provides better improvement in area and 2x1 Mux model 5 provides better in delay improvement.
Table 1: Multiplexer based DPFPM using Vedic multiplier
Double Precision Floating Point Multiplication using Vedic multiplier
Number of 4-input
LUTs
Number of Slices
Delay (ns)
Vedic multiplier using Modified 2x1 Multiplexer Models
4x1 Mux
(Existing) 1560 912 53.24
2x1 Mux
model 1 1446 887 51.09
2x1 Mux
model 2 1314 834 50.18
2x1 Mux model 3
1301 820 48.41
2x1 Mux model 4
1284 782 49.13
2x1 Mux model 5
1108 713 43.71
2x1 Mux model 6
1178 761 46.13
2x1 Mux model 7
1212 793 45.71
2x1 Mux model 8
1192 772 44.21
2x1 Mux model 9
1261 841 45.27
Table 2: Multiplexer based DPFPM using Karatsuba Algorithm Double Precision Floating Point
Multiplication using Karatsuba Algorithm
Number of 4- input LUTs
Number of Slices
Delay (ns)
Karatsuba Algorithm using Modified 2x1
Multiplexer Models
4x1 Mux
(Existing) 1823 1501 47.24
2x1 Mux
model 1 1773 1452 46.09
2x1 Mux
model 2 1717 1432 45.18
2x1 Mux model 3
1687 1412 43.41
2x1 Mux model 4
1618 1393 44.13
2x1 Mux model 5
1568 1297 39.71
2x1 Mux model 6
1669 1492 42.13
2x1 Mux model 7
1753 1532 41.71
2x1 Mux model 8
1718 1521 40.94
2x1 Mux model 9
1851 1598 41.57
V. CONCLUSION
In this paper, double precision floating point multiplication using vedic multiplier and Karatsuba algorithm with different modified 2x1 multiplexer based full adders with respect to area and speed.
From the results it is resolved that Double Precision floating point multiplication using Karatsuba algorithm with 2x1 multiplexer model V achieves better performance in terms of speed and optimized area. Further, Karatsuba and vedic algorithms based Double Precision floating point multiplication is analyzed and compared in terms of speed and area. From the comparison analysis, Karatsuba algorithm using 2x1 Multiplexer model V achieves 10% improvement in speed with respect to Vedic multiplier. Similarly, vedic multiplier achieves better results in view of area , it gives 41%
improvement with respect to area.
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