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Interconnection Structures

Interconnection Structures

 A computer consists of a set A computer consists of a set of componentsof components

(CPU,memory

(CPU,memory,I/O) that ,I/O) that communicate withcommunicate with each other.

each other.

  The collection of paths connecting the The collection of paths connecting the

various modules is call the

various modules is call the interconnectioninterconnection

structure

structure..

  The design of this structure will depend on The design of this structure will depend on

the exchange that must be made between the exchange that must be made between modules

(2)

Input/Output for each module

Input/Output for each module

Memory Memory N Word N Word 0 0 .. .. .. N-1 N-1 Read Read Write Write Address Address Data Data Data Data CPU CPU Interrupt Signal Interrupt Signal Data Data Data Data Instructions Instructions Control Control Signal Signal I/O Module I/O Module M Ports M Ports Read Read Write Write Address Address Internal Internal Data Data External External Data Data Internal Internal Data Data External External Data Data Interrupt Interrupt Signal Signal

(3)

 Type of transfers

 Type of transfers

Memory to CPU

Memory to CPU

CPU to Memory

CPU to Memory

I/O to CPU

I/O to CPU

CPU to I/O

CPU to I/O

(4)

Bus Interconnection

Bus Interconnection

 A bus is a communication pathwayA bus is a communication pathway

connecting two or more device. connecting two or more device.

 A key characteristic of a bus is that A key characteristic of a bus is that it is ait is a

shared transmission medium. shared transmission medium.

 A bus consists of multiple pathways or lines.A bus consists of multiple pathways or lines. 

 Each line is capable of transmitting signalEach line is capable of transmitting signal

representing binary digit (1 or 0) representing binary digit (1 or 0)

(5)

Bus Interconnection

Bus Interconnection

 A sequence of bits can be transmit across aA sequence of bits can be transmit across a

single line. single line.

 Several lines can be used to transmit bitsSeveral lines can be used to transmit bits

simultaneously (in parallel). simultaneously (in parallel).

 A bus that connects major componentsA bus that connects major components

(CPU,Memory,I/O) is called

(CPU,Memory,I/O) is called System BusSystem Bus..

  The most common computer interconnection The most common computer interconnection

structures are based on the use

structures are based on the use of one orof one or more system buses.

(6)

Bus Structure

Bus Structure

 A system bus consists of 50-100 lines.A system bus consists of 50-100 lines.

 Each line is assigned a Each line is assigned a particular meaning or function.particular meaning or function.

 On any bus the lines can be classified into 3 groupsOn any bus the lines can be classified into 3 groups

 Data linesData lines

 Address linesAddress lines

(7)

Data Lines

Data Lines

 Provide a path for moving data between systemProvide a path for moving data between system

modules. modules. 

  These lines, collectively, are called the These lines, collectively, are called the data busdata bus

  The data bus typically consists of 8,16 or 32 The data bus typically consists of 8,16 or 32

separate lines, the numbers of lines being separate lines, the numbers of lines being transferred to as the

transferred to as the widthwidth of the data bus.of the data bus. 

 Each line carry only 1 bit at a time, the number of Each line carry only 1 bit at a time, the number of 

lines determines how many bits can transferred at lines determines how many bits can transferred at a time - overall system performance.

(8)

 The Address Lines

 The Address Lines

 Used to designate the source orUsed to designate the source or

destination of the data on the data bus destination of the data on the data bus

  The width of the address bus The width of the address bus

determines the maximum possible determines the maximum possible memory capacity of the system.

(9)

 The Control Lines

 The Control Lines

 Used to control the access to and the useUsed to control the access to and the use

of the data and address lines. of the data and address lines.

 Typical control lines include Typical control lines include

 Memory writeMemory write 

 Memory readMemory read 

 I/O writeI/O write 

 I/O readI/O read 

 ClockClock 

 ResetReset

 Bus requestBus request

 Bus grantBus grant

 Interrupt requestInterrupt request

 Interrupt ACK Interrupt ACK 

(10)

 The operation of the bus

 The operation of the bus

If one module wishes to send data If one module wishes to send data

 obtain the use of the busobtain the use of the bus 

 transfer data via the bustransfer data via the bus

If one module wishes to request data If one module wishes to request data

 obtain the use of the busobtain the use of the bus 

 transfer request to the other module over thetransfer request to the other module over the

control and address lines, then wait for

control and address lines, then wait for thatthat second module to send the data.

(11)

Physical Bus Architecture

Physical Bus Architecture

 System bus is a number of System bus is a number of 

parallel electrical conductors. parallel electrical conductors.

  The conductors are metal The conductors are metal

lines etched in a card or lines etched in a card or printed circuit board.

printed circuit board.

  The bus extends across all of  The bus extends across all of 

the components tat taps into the components tat taps into the bus lines.

(12)

Multiple-Bus Hierarchies

Multiple-Bus Hierarchies

 More devices attached to bus, More devices attached to bus, propagationpropagation

delays affect performance delays affect performance

 How to arbitration arbitration?How to arbitration arbitration?

 Bottleneck as the aggregate dataBottleneck as the aggregate data

transfer demand approaches capacity of  transfer demand approaches capacity of 

bus. bus. (e.g

(e.g graphics graphics & & video video controller)controller)

(13)

 Traditional Bus Architecture

 Traditional Bus Architecture

Local bus

Local bus

 CPU - CacheCPU - Cache

System bus

System bus

 Main memory - CacheMain memory - Cache

Expansion bus

Expansion bus

(14)

High-Performance Architecture

High-Performance Architecture

Local bus

Local bus

 CPU - Cache/bridgeCPU - Cache/bridge

System bus

System bus

 Cache/bridge - memoryCache/bridge - memory

High-speed bus

High-speed bus

 High-speed I/O module - Cache/bridgeHigh-speed I/O module - Cache/bridge

Expansion bus

Expansion bus

(15)

Bus Design

Bus Design

 

 Type

 Type

  DedicatedDedicated   MultiplexedMultiplexed 

Bus Width

Bus Width

  AddressAddress   DataData  

 Timing

 Timing

  SynchronousSynchronous   AsynchronousAsynchronous 

Method of Arbitration

Method of Arbitration

 CentralizedCentralized

 DistributedDistributed

Data Transfer Type

Data Transfer Type

  ReadRead   WriteWrite   Read-modify-writeRead-modify-write   Read-after-writeRead-after-write   BlockBlock

(16)

 Type

 Type

Dedicated

Dedicated

permanent assigned bus either

permanent assigned bus either

to one function or to a physical

to one function or to a physical

subset of computer components

subset of computer components

Multiplexed

Multiplexed

use

use

in

in

the

the

same

same

bus

bus

for

for

multiple purpose

(17)

Bus Width

Bus Width

Address

Address

the

the

wider

wider

of

of

address

address

bus

bus

has an impact on range of 

has an impact on range of 

locations that can be referenced

locations that can be referenced

Data

Data

the wider of data bus

the wider of data bus

has an impact on the number

has an impact on the number

of bits transferred at one time

of bits transferred at one time

(18)

 Timing

 Timing

  SynchronousSynchronous occurrence occurrence of

of events events on on the the busbus

is determined by a

is determined by a

clock (

clock (Clock Cycle orClock Cycle or

Bus Cycle

Bus Cycle) which) which

includes line upon

includes line upon

  AsynchronousAsynchronous occurrence occurrence of one event of one event follows and follows and depends on the depends on the previous event. previous event.

(19)

Method of Arbitration

Method of Arbitration

  CentralizedCentralized bus controller bus controller (

(ArbiterArbiter), hardware), hardware

device,is responsible

device,is responsible

for allocating time

for allocating time

on the bus (daisy

on the bus (daisy

chain) chain)   DistributedDistributed access control access control

logic in each module

logic in each module

act together to share

act together to share

bus

(20)

Data Transfer Type

Data Transfer Type

Read

Read

Multiplexed

Multiplexed

bus is used to

bus is used to

specifying address and then for

specifying address and then for

transferri

transferri

ng

ng

data

data

after

after

a

a

wait

wait

while

while

data is being fetched

data is being fetched

Read

Read

Dedicated

Dedicated

address is put

address is put

on

on

bus

bus

and

and

remain

remain

there

there

while

while

data

data

are put on the data bus

(21)

Data Transfer Type

Data Transfer Type

 WriteWrite MultiplexedMultiplexed

bus is used to

bus is used to specifying addressspecifying address

and

and then then transferring transferring data data ((same assame as

read operation

read operation))

 WriteWrite DedicatedDedicated

data put on data bus as soon

data put on data bus as soon

as the address has stabilized

(22)

 Read-modify-writeRead-modify-write

address is broadcast once at beginning a

address is broadcast once at beginning a

simply read is followed immediately by a

simply read is followed immediately by a write towrite to

the same address

the same address

 Read-after-writeRead-after-write

a write followed immediately by a read

a write followed immediately by a read

from the same address,performed for checking

from the same address,performed for checking

purposes

purposes

Data Transfer Type

Data Transfer Type

(23)

Data Transfer Type

Data Transfer Type

Block

Block

one address cycle is

one address cycle is

followed by

followed by

n

n

data cycles.

data cycles.

 The first data item is transferred to

 The first data item is transferred to

or from the specified address;

or from the specified address;

remainder

remainder

data

data

items

items

are

are

transferred

transferred

to

to

or

or

from

from

subsequent

subsequent

addresses

(24)

Data Transfer Type

Data Transfer Type

no

no

(25)

Samples of Bus

Samples of Bus

 ISA (Industry Standard Architecture)ISA (Industry Standard Architecture)

 MCA (Micro Channel Architecture)MCA (Micro Channel Architecture)

 EISA (Extended ISA)EISA (Extended ISA)

 VL Bus (VESA Local Bus)VL Bus (VESA Local Bus)

 PCI Bus (Peripheral ConnectionPCI Bus (Peripheral Connection

Interface) Interface)

(26)

Industry Standard Architecture

Industry Standard Architecture

 ISA is a standard busISA is a standard bus (computer(computer interconnection)

interconnection) architecture that isarchitecture that is

associated with the IBM AT motherboard. associated with the IBM AT motherboard.

 It allows 16 bits at a tiIt allows 16 bits at a time to flowme to flow

between the motherboard circuitry and between the motherboard circuitry and an expansion slot card and its associated an expansion slot card and its associated device(s).

device(s).

no

no

(27)

Industry Standard Architecture

(28)

A

A

"local bus" 

"local bus" 

is a physical

is a physical

path on which data flows at

path on which data flows at

almost the speed of the

almost the speed of the

microprocessor, increasing

microprocessor, increasing

total system performance.

(29)

Micro Channel Architecture

Micro Channel Architecture

 Developed by IBM for its line of PS/2 desktopDeveloped by IBM for its line of PS/2 desktop

computers, MCA is an interface between a computers, MCA is an interface between a computer (or multiple computers) and its computer (or multiple computers) and its

expansion cards and their associated devices. expansion cards and their associated devices. 

 MCA was a distinct break from previous busMCA was a distinct break from previous bus

architectures such as ISA. architectures such as ISA. 

  The pin connections in MCA are smaller than other The pin connections in MCA are smaller than other

bus interfaces. For this and other reasons, MCA bus interfaces. For this and other reasons, MCA does not support other bus architectures.

does not support other bus architectures.

no

no

(30)

Micro Channel Architecture

Micro Channel Architecture

(cont.)

(cont.)

 Although MCA offers a number of Although MCA offers a number of 

improvements over other bus improvements over other bus architectures, its proprietary, architectures, its proprietary,

nonstandard aspects did not encourage nonstandard aspects did not encourage other manufacturers to adopt it.

other manufacturers to adopt it.

 It has influenced other bus designs andIt has influenced other bus designs and

it is still in use in PS/2s and in some it is still in use in PS/2s and in some minicomputer systems.

minicomputer systems.

no

no

(31)

Extended Industry Standard

Extended Industry Standard

Architecture

Architecture

 EISA is a standard bus EISA is a standard bus architecture thatarchitecture that

extends the ISA standard to a

extends the ISA standard to a 32-bit32-bit interface. It was developed in part as

interface. It was developed in part as anan open alternative to the proprietary

open alternative to the proprietary

Micro Channel Architecture (MCA) that Micro Channel Architecture (MCA) that IBM introduced in its PS/2 computers. IBM introduced in its PS/2 computers.

 EISA data transfer can reach a peak of EISA data transfer can reach a peak of 

33 megabytes per second 33 megabytes per second

no

no

(32)

VESA Local Bus

VESA Local Bus

 VESA VL bus is a standard interfaceVESA VL bus is a standard interface

between your computer and its e

between your computer and its expansionxpansion slot that provides faster data

slot that provides faster data flow betweenflow between the devices controlled by the expansion

the devices controlled by the expansion

cards and your computer's microprocessor. cards and your computer's microprocessor.

 AA "local bus""local bus" is a physical path on whichis a physical path on which

data flows at almost the speed of the data flows at almost the speed of the

microprocessor, increasing total system microprocessor, increasing total system performance.

performance.

no

no

(33)

VESA Local Bus (cont.)

VESA Local Bus (cont.)

 VESA Local Bus is VESA Local Bus is particularly effective inparticularly effective in

systems with advanced video cards and systems with advanced video cards and supports 32-bit data flow at 50 MHz

supports 32-bit data flow at 50 MHz

 A VESA Local Bus is implemented by addingA VESA Local Bus is implemented by adding

a supplemental slot and card that aligns a supplemental slot and card that aligns with and augments an ISA expansion card. with and augments an ISA expansion card. (ISA is the most common expansion slot in (ISA is the most common expansion slot in today's computers.)

today's computers.)

no

no

(34)

Peripheral Component

Peripheral Component

Interconnect

Interconnect

 PCI is an interconnection systemPCI is an interconnection system

between a microprocessor and attached between a microprocessor and attached devices in which expansion slot are

devices in which expansion slot are

spaced closely for high speed operation. spaced closely for high speed operation.

 Using PCI, a computer can support bothUsing PCI, a computer can support both

new PCI cards while continuing to new PCI cards while continuing to

support ISA expansion cards, currently support ISA expansion cards, currently the most common kind of expansion the most common kind of expansion card.

(35)

Peripheral Component Interconnect

Peripheral Component Interconnect

(cont.)

(cont.)

 Designed by Intel, the original PCI was similar to theDesigned by Intel, the original PCI was similar to the

VESA Local Bus. VESA Local Bus.

 PCI2.0 is no longer a local bus and is designed to bePCI2.0 is no longer a local bus and is designed to be

independent of microprocessor design. independent of microprocessor design.

 PCI is designed to be synchronized with the clockPCI is designed to be synchronized with the clock

speed of the microprocessor, in the range of 33 to speed of the microprocessor, in the range of 33 to 66 MHz.

66 MHz.

 Standard : Up to 64 data-lines at 66 MHz. RawStandard : Up to 64 data-lines at 66 MHz. Raw

transfer

(36)

Peripheral Component Interconnect

Peripheral Component Interconnect

(cont.)

(cont.)

 PCI is now installed on most newPCI is now installed on most new

desktop computers, not only those desktop computers, not only those

based on Intel's Pentium processor but based on Intel's Pentium processor but also those based on the PowerPC.

also those based on the PowerPC.

 PCI transmits 32 bits at a time in PCI transmits 32 bits at a time in a 124-a

124-pin connection (the extra 124-pins are for pin connection (the extra pins are for power supply and grounding) and 64 power supply and grounding) and 64 bits in a 188-pin connection in an

bits in a 188-pin connection in an expanded implementation.

(37)

Peripheral Component Interconnect

Peripheral Component Interconnect

(cont.)

(cont.)

 PCI uses all active paths to transmitPCI uses all active paths to transmit

both address and data signals, sending both address and data signals, sending the address on one clock cycle and data the address on one clock cycle and data on the next.

on the next.

 PCI deliver better system performancePCI deliver better system performance

for high-speed I/O subsystems for high-speed I/O subsystems e.g.

e.g. graphic display adaptersgraphic display adapters,, networknetwork

interface controllers

(38)

PCI

PCI

Single-processo

Single-processor r SystemSystem

A Multiprocessor System A Multiprocessor System

(39)

Interface

Interface

Port Port   SerialSerial   ParallelParallel   PS/2PS/2   PCMCIAPCMCIA   USBUSB (Universal Serial (Universal Serial Bus) Bus) No port No port   InfraredInfrared   BluetoothBluetooth

(40)

Universal Serial Bus

Universal Serial Bus

 Standard bus which is invented by a group of companies :Standard bus which is invented by a group of companies :

Compaq, DEC, IBM, Intel, Microsoft, NEC, Northern Compaq, DEC, IBM, Intel, Microsoft, NEC, Northern  Telecom, etc.

 Telecom, etc. 

 Not change switch, jumper on board or other devicesNot change switch, jumper on board or other devices

 Can use the same cableCan use the same cable

 Device that use USB can use power supply from PC.Device that use USB can use power supply from PC.

 Up to 127 devices connected off single portUp to 127 devices connected off single port

 Support real-time systemSupport real-time system

 Hot Plug-inHot Plug-in

 Low costLow cost

no

no

(41)

Multi-System Buses

(42)

Accelerated Graphics Port

Accelerated Graphics Port

 AGP is an interface specification that enables 3-DAGP is an interface specification that enables 3-D

graphics to display quickly on ordinary PC. graphics to display quickly on ordinary PC. 

 AGP is an interface designed to convey 3-D imagesAGP is an interface designed to convey 3-D images

(ex:-from Web sites or CD-ROMs) much more quickly (ex:-from Web sites or CD-ROMs) much more quickly and smoothly than is possible today on any computer and smoothly than is possible today on any computer other than an expensive graphics workstation.

other than an expensive graphics workstation. 

  The interface uses your computer's main storage The interface uses your computer's main storage

(RAM) for refreshing the monitor image and to support (RAM) for refreshing the monitor image and to support the

the texture mappingtexture mapping,, z-buffering z-buffering,, andand alpha blendingalpha blending required for 3-D image display.

required for 3-D image display.

no

no

(43)

Accelerated Graphics Port (cont.)

Accelerated Graphics Port (cont.)

  The AGP main memory use is dynamic, meaning that when not The AGP main memory use is dynamic, meaning that when not being used for accelerated graphics, main

being used for accelerated graphics, main memory is restoredmemory is restored for use by the operating system or other applications.

for use by the operating system or other applications.

 Intel, which has taken the lead in developing its specifications,Intel, which has taken the lead in developing its specifications, introduced AGP into a chipset for its Pentium microprocessor. introduced AGP into a chipset for its Pentium microprocessor.

  The newer, faster microchips in  The newer, faster microchips in Pentium line are designed toPentium line are designed to work with the AGP chipset. Intel says the advanced floating work with the AGP chipset. Intel says the advanced floating point unit and faster cache algorithm of the more advanced point unit and faster cache algorithm of the more advanced Pentiums are better adapted for 3-dimensional applications. Pentiums are better adapted for 3-dimensional applications.

no

no

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