Universidade de Lisboa

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de Lisboa

Curriculum Vitae of Professor

Leonel Augusto Pires Seabra de Sousa

Electrical and Computer Engineering Department, IST

INESC-ID, Rua Alves Redol, 9, 1000-029 Lisboa, Portugal

email: las@inesc-id.pt

web page: http://sips.inesc-id.pt/las

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Experience

Current Activities

Current position Full Professor in the Electrical and Computer Engineering (ECE) Department at Instituto Superior T´ecnico(IST), Universidade de Lisboa (UL), in Portugal, since December 2010. Teaching Lecturer of basic and advanced courses on embedded systems, computer architectures, and

parallel systems, included in the ECE M.Sc. and Ph.D. programs at IST.

Research Head a of a research group atInstituto de Engenharia de Sistemas e Computadores, Inves-tiga¸c˜ao e Desenvolvimento(INESC-ID), currently supervising 6 PhD students (supervised 12 PhD students that already finished), member of the EU FP7 Network of Excellence HiPEAC3, member of the management committee and Working Group Leader of the EU COST action Network for Sustainable Ultrascale Computing (NESUS), and Principal Investigator of the project Stretching the Limits of Parallel Processing on Heterogenous Computing Systems funded by the Portuguese Foundation for Science and Technology.

Conselor One of the 14 members of the Scientific Council for Exact Sciences and Engineering of the Portuguese Foundation for Science and Technology (FCT), with the mission of providing the FCT Board with strategic advice and recommendations on developing, implementing and modifying science and technology in Portugal; Vice-Head of the Scientific Board of IST, a board composed by 20 elected members that plays a major role in the governance of IST.

Evaluator Coordinator of the National Panel for the final scientific evaluation of all projects in the area of Electrical Engineering funded by the FCT (2014-2016); evaluator of research project proposals of the H2020 program sponsored by the European Commission; reviewer and opponent on several these PhD defenses on international universities.

Speaker Invited or keynote speaker on several conferences, universities and companies.

Professional service Editor-in-Chief of the Springer EURASIP Journal of Embedded Systems, and Associate Editor of the IEEETransactions on Multimedia, IEEETransactions on Circuits and Sys-tems for Video Technology, IEEE Access, and SpringerJournal of Real Time Image Pro-cessing; involved in the organization of several international conferences (e.g. in 2014 in ICCD, SAMOS, Computing Frontiers, IPDPS, ICPP, Europar, EUSIPCO, SBAC-PAD); member of several international technical committees.

Previous Recent Activities

Positions Chair of INESC-ID, a not for profit, privately owned institution of public interest, dedica-ted to advanced research and development in the domains of electronics, telecommunicati-ons and information technologies, with more than 100 PhD researchers and owned by IST (2009-2013); Coordinator of the M.Sc. and B.Sc. programs in ECE at IST, which totalize more than 1500 students (2008-2012); Visiting Professor in the Computer Engineering Lab at the Faculty of Electrical Engineering, Mathematics and Computer Science of TU Delft (”2002/03 spring semester).

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Academic Degrees

• Habilitation (Agrega¸c˜ao in Portugal) in Electrical and Computer Engineering, at IST, in 2004. Thesis title: Architectures and Algorithms for Signal Processing in Real Time.

• Ph.D. degree in Electrical and Computer Engineering, at IST, in 1996. Thesis title: Parallel Image Processors with Orthogonal Access to Shared Memory.

• M.Sc. in Electrical and Computer Engineering, at IST, in 1989. Thesis title: Algorithms and Architecture for the Digital Signal Processing System APICE.

• Licenciatura in Electronics and Telecommunications at University of Aveiro, in 1984.

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Teaching

My teaching experience comprises: the development of new advanced postgraduate courses in the area of Computer Engineering; the coordination, for five years, of the MSc and BSc programs in Electrical and Computer Engineering (ECE) at IST, with a total of more than 1500 students; and the teaching of courses in this area. I have developed pedagogical material to the courses that I taught, which has been used through the years.

Teaching I have taught courses on Computer Organization, Computer Architecture, Embedded Systems, and Parallel Computing Architectures over the past 15 years. Notwithstanding I have intro-duced several courses in the M.Sc. and Ph.D. ECE programs, I have also taught courses on Embedded Systems, namely theComputer Electronicscourse and theBasic Electronicscourses.

New courses I have designed and introduced the following new courses in the IST MS.C and Ph.D. Programs in ECE:Advanced Computer Architectures, started in 2003/2004 and has been running in the M.Sc. program all spring semesters; Specialized Digital Processors, launched as an elective course in 1997/98 and offered in the program till 2002/2003; and High Performance Com-puting Architectures, a course that is running in the PhD program since 2006/2007. I have developed advanced lab tutorials for courses in computer architecture and embedded systems, an example can be found inA Lab Project on the Design and Implementation of Programmable and Configurable Embedded Systems, one of the most popular articles of theIEEE Transactions on Education.

Curriculum Design I was also involved in curriculum design, 2006/2007, on adapting the ECE integrated M.Sc. Program according to the Bologna declaration. Being in charge of coordinating the M.Sc. and the B.Sc. ECE programs in IST since 2009, in 2011/2012 I redesigned the ECE M.Sc. Program, namely the organization of the specialization areas and the courses offered in each one of those areas.

Textbooks I am co-author of the textbook Bioelectronic Vision Retina Models, Evaluation Metrics, and System Design, series on Bioengineering and Biomedical Engineering, vol. 3, World Scientific, a textbook for advanced undergraduate and graduate students in biomedical engineering, and electrical and computer engineering. This book provides a technical perspective of the func-tional and structural retina models, and provides insight about the models used on hardware implementations.

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4. Research Focus and Achievements 3

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Research Focus and Achievements

The focus of my research has been on computer architecture and high performance computing, namely the design of highly efficient architectures, algorithms and circuits for current and emergent applications. My research work has evolved by taking a holistic system perspective that addresses the interaction between applications, algorithms, software and hardware platforms, and how it impacts the performance and tradeoffs across different hardware and software solutions. Among others, there are two key topics in which I have made cutting-edge research contributions: Hardware Accelerators, and Parallel Heterogeneous Systems.

• Hardware Accelerators

– Theoretical formulation of computational redundancy in predictive video coding approaches [J.62]: served as the basis for further investigation and practical application to exploit redundancy in all current video encoding standards Discrete Cosine Transform (DCT) based or integer DCT-based transforms;

– Design of specific programmable and dedicated accelerators, mostly for signal processing and cryp-tography: encompasses groundwork for what is today known as General-Purpose Computing on Graphics Processing Units (GPGPU), as well as for fully exploiting spatial parallelism also at arith-metic level, by investigating Residue Number Systems (RNS);

∗ Pioneer work on programming models and tools for stream-based computing, when in early 2000’s, GPU programming and execution models were proposed for the first time (as the fore-runners to nowadays common concepts), e.g. flow-modelfor stream computing and the program-ming tool and run-time system Caravela [J.48], with its extension to GPU-based distributed computing [C.64]. This work opened gates to the use of GPUs beyond their graphics purposes, e.g., for solving regular and irregular Low-Density Parity-Check (LDPC) [J.35, J.29, J.19];

∗ RNS for deeply exploit parallelism, at the level of RNS arithmetic units and converters for large moduli sets [J.1] [J.10]; this investigation paved the way for innovative RNS-based public-key parallel cryptographic accelerators - an advantageous new approach, both in hardware and software, to achieve high performance computing [J.24, J.17] and energy-efficiency in embedded systems [C.36, C.1].

• Parallel Heterogeneous Systems

– Communication-aware static task scheduling algorithms for multicore and distributed systems: in a ground work, it was shown the impact of communication for task scheduling in cluster systems [J.54], and new system model and scheduling algorithms were proposed [J.51]. These contributions have a significant impact in static task scheduling and they represent an unavoidable research basis for current scientific studies in parallel and distributed systems (more than 250 citations in the Scholar).

– On-the-fly performance modeling and dynamic load balancing for heterogeneous systems: these con-tributions also led to development of several on-the-fly performance modeling and scheduling algo-rithms for heterogeneous multi-core systems, namely for parallel CPU+GPU systems and highly heterogeneous multi-cluster environments; these algorithms have been applied for a plethora of dif-ferent applications, such as video encoding, data-base applications, linear algebra and digital signal processing [J.9, C.13].

– Insightful performance modeling of multi-core architectures: this recent contribution tackles the important topic of roofline modeling for multi-cores (very much used, more than 100 citations just

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in 2014). To overcome serious limitations of the original model, the Cache-Aware Roofline Model (CARM) [J.7] explicitly considers a complete memory hierarchy when describing the performance of multi-core architectures.

5

Publications

More than 140 publications in DBLP, more than 1050 citations registered in Scopus (h-index 17), and 2400 in the Google Scholar (h-index 25), the most relevant are listed below.

5.1

Textbook

[B.1] J. Martins and L. Sousa,Bioelectronic Vision: Retina Models, Evaluation Metrics, and System Design, volume 3 ofSeries on Bioengineering & Biomedical Engineering, World Scientific, London, March 2009.

5.2

Journal papers

[J.1] L. Sousa, “2nRNS scalers for extended 4-moduli sets,”IEEE Transactions on Computers, 2015, accepted for publication.

[J.2] R. Chaves P. Matutino and L. Sousa, “An efficient scalable RNS architecture for large dynamic ranges,”

Journal of Signal Processing Systems, volume 77, no. 1-2, pp. 191–205, 2014.

[J.3] H. Pettenghi, F. Pratas and L. Sousa, “Method for designing efficient mixed radix multipliers,”Circuits, Systems & Signal Processing, volume 33, no. 10, pp. 3165–3193, 2014.

[J.4] S. Ant˜ao and L. Sousa, “A flexible architecture for modular arithmetic hardware accelerators based on RNS,”Journal of Signal Processing Systems, volume 76, no. 3, pp. 249–259, 2014.

[J.5] L. Sousa and P. Martins, “Efficient sign identification engines for integers represented in the RNS extended 3-moduli set {2n−1,2n+k,2n+ 1},”IET Electronics Letters, volume 50, no. 16, pp. 1138– 1139, 2014.

[J.6] T. Dias, N. Roma and L. Sousa, “Unified transform architecture for AVC, AVS, VC-1 and HEVC high-performance codecs,”EURASIP Journal on Advances in Signal Processing, , no. 1, July 2014.

[J.7] A. Ilic, F. Pratas and L. Sousa, “Cache-aware roofline model: Upgrading the loft,” IEEE Computer Architecture Letters, volume 13, no. 1, pp. 21–24, 2014.

[J.8] H. Pettenghi, S. Cotofana and L. Sousa, “Efficient method for designing modulo{2n±k}multipliers,”

Journal of Circuits, Systems, and Computers, volume 23, no. 1, 2014.

[J.9] Nuno Roma S. Momcilovic, A. Ilic and L. Sousa, “Dynamic load balancing for real-time video encoding on heterogeneous cpu+gpu systems,”IEEE Transactions on Multimedia, volume 16, no. 1, pp. 108–121, 2014.

[J.10] H. Pettenghi, R. Chaves and L. Sousa, “Method to design general RNS reverse converters for extended moduli sets,”IEEE Transactions on Circuits and Systems II, volume 60, no. 12, pp. 877–881, 2013.

[J.11] S. Sanchez, R. Ramalho, L. Sousa and A. Plaza, “Real-time implementation of remotely sensed hy-perspectral image unmixing on GPUs,” Journal of Real-Time Image Processing, 2013, accepted for publication.

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5.2 Journal papers 5

[J.12] D. Jayasinghe J. Ambrose, H. Pettenghi and L. Sousa, “A randomized multi-modulo RNS architecture for double-and-add to prevent power analysis side channel attacks,”IET Circuits, Devices & Systems, volume 7, no. 5, pp. 283–293, 2013.

[J.13] L. Sousa, S. Ant˜ao and J. Germano, “A lab project on the design and implementation of programmable and configurable embedded systems,”IEEE Transactions on Education, volume 56, no. 3, pp. 322–328, 2013.

[J.14] L. Sousa, S. Ant˜ao and R. Chaves, “On the design of RNS reverse converters for the four-moduli set

{2n+ 1,2n1,2n,2n+1+ 1},”IEEE Transactions on Very Large Scale Integration (TVLSI) Systems,

volume 21, no. 10, pp. 1945–1949, 2013.

[J.15] H. Pettenghi, R. Chaves and L. Sousa, “RNS reverse converters for moduli sets with dynamic ranges up to (8n+1)-bit,”IEEE Transactions on Circuits and Systems I, volume 60-I, no. 6, pp. 1487–1500, 2013.

[J.16] T. Dias, S. Lopez, N. Roma and L. Sousa, “Scalable unified transform architecture for advanced video coding embedded systems,” International Journal of Parallel Programming (IJPP), volume 41, no. 2, pp. 236–260, 2013.

[J.17] S. Ant˜ao and L. Sousa, “The CRNS framework and its application to programmable and reconfigurable cryptography,”ACM Transactions on Architecture and Code Optimization, volume 9, no. 4, p. 33, 2013.

[J.18] R. Ferreira, E. Paz, P. Freitas, J. Ribeiro, J. Germano and L. Sousa, “2-axis magnetometers based on full Wheatstone bridges incorporating magnetic tunnel junctions connected in series,”IEEE Transactions on Magnetics, volume 48, no. 11, pp. 4107–4110, November 2012.

[J.19] G. Falc˜ao, V. Silva, L. Sousa and J. Andrade, “Portable LDPC decoding on multicores using OpenCL,”

IEEE Signal Processing Magazine, volume 29, no. 4, pp. 81–109, July 2012.

[J.20] F. Pratas, P. Trancoso, L. Sousa, A. Stamatakis, G. Shi and V. Kindratenko, “Fine-grain parallelism using multi-core, Cell/B.E., and GPU systems,” Journal of Parallel Computing (ParCo), volume 38, no. 8, pp. 365—-390, August 2012.

[J.21] F. Pratas, L. Sousa, J. Dieterich and R. Mata, “Computation of induced dipoles in molecular mechanics simulations using graphics processors,”Journal of Chemical Information and Modeling, volume 52, no. 5, pp. 1159—-1166, April 2012.

[J.22] L. Sousa and S. Ant˜ao, “MRC-based RNS reverse converters for the four-moduli sets {2n+ 1,2n 1,2n,22n+1)−1} and{2n+ 1,2n1,22n),22n+11},” IEEE Transactions on Circuits and Systema II

(TCAS II), volume 59, no. 4, pp. 244–248, April 2012.

[J.23] G. Falc˜ao, M. Gomes, V. Silva, L. Sousa and J. Cacheira, “Configurable m-factor VLSI DVB-S2 LDPC decoder architecture with optimized memory tiling design,”EURASIP Journal on Wireless Communi-cations and Networking, , no. 98, March 2012.

[J.24] S. Ant˜ao, J-C Bajard and L. Sousa, “RNS based elliptic curve point multiplication for massive parallel architectures,”Computer Journal, volume 55, no. 5, pp. 629–647, May 2012.

[J.25] N. Roma and L. Sousa, “A tutorial overview on the properties of the discrete cosine transform for encoded image and video processing,” Signal Processing, volume 91, no. 11, pp. 2443–2464, November 2011.

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[J.26] S. L´opez T. Dias, N. Roma and L. Sousa, “A flexible architecture for the computation of direct and in-verse transforms in H.264/AVC video codecs,”IEEE Transactions on Consumer Electronics, volume 57, no. 2, pp. 936–944, May 2011.

[J.27] G. Falc˜ao, J. Andrade, V. Silva and L. Sousa, “GPU-based DVB-S2 LDPC decoder with high throughput and fast error floor detection,”Elecronics Letters, volume 47, no. 9, pp. 542–543, April 2011.

[J.28] S. Momcilovic and L. Sousa, “Modeling and evaluating non-shared memory Cell/B.E. type multi-core ar-chitectures for local image and video processing,”The Journal of Signal Processing Systems, volume 62, no. 3, March 2011.

[J.29] G. Falc˜ao, L. Sousa and V. Silva, “Massively LDPC decoding on multicore architectures,”IEEE Tran-sactions on Parallel and Distributed Systems (TPDS), volume 22, no. 2, pp. 309—-322, February 2011.

[J.30] P. Tom´as and L. Sousa, “A quantitative analysis of firing rate estimators: unveiling bias sources,”

Neurocomputing, volume 73, no. 16-18, October 2010.

[J.31] V. Martins, J. Germano, F. Cardoso, J. Loureiro, S. Cardoso, L. Sousa, M. Piedade, L. Fonseca and P. Freitas, “Challenges and trends in the development of a magnetoresistive biochip portable platform,”

Journal of Magnetism and Magnetic Materials, volume 322, no. 9-12, p. 1655–1663, May 2010.

[J.32] P. Lopes, J. Germano, T. Almeida, L. Sousa, M. Piedade, F. Cardoso, H. Ferreira and P. Freitas, “Measuring and extraction of biological information on new handheld biochip-based microsystem,”IEEE Transactions on Instrumentation and Measurement, volume 59, no. 1, pp. 56–62, January 2010.

[J.33] T. Almeida, M. Piedade, L. Sousa, J. Germano, P. Lopes, F. Cardoso and P. Freitas, “On the model-ling of new tunnel junction magnetoresisitive biosensors,”IEEE Transactions on Instrumentation and Measurement, volume 59, no. 1, pp. 92–100, January 2010.

[J.34] P. Tom´as and L. Sousa, “A feature selection algorithm for the regularization of neuron models,” IEEE Transactions on Instrumentation and Measurement, volume 58, no. 11, pp. 3824–3830, November 2009.

[J.35] G. Falc˜ao, S. Yamagiwa, V. Silva and L. Sousa, “Parallel LDPC decoding on GPUs using a stream-based computing approach,” Journal of Computer Science and Technology, volume 24, no. 5, pp. 913–924, 2009.

[J.36] J. Germano, V. Martins, F. Cardoso, T. Almeida, L. Sousa, P. Freitas and M. Piedade, “A portable and autonomous magnetic detection platform for biosensing,”Sensors, volume 9, no. 6, pp. 4119–4137, June 2009.

[J.37] J. Martins, P. Toma´s and L. Sousa, “Neural code metrics: Analysis and application to the assessment of neural models,”Neurocomputing, volume 72, no. 10-12, pp. 2337–2350, June 2009.

[J.38] V. Martins, F. Cardoso, J. Germano, S. Cardoso, L. Sousa, M. Piedade, P. Freitas and L. Fonseca, “Fem-tomolar limit of detection with a magnetoresistive biochip,”Biosensors and Bioelectronics, volume 24, no. 8, pp. 2690–2695, February 2009.

[J.39] G. Falc˜ao, V. Silva, L. Sousa and J. Marinho, “High coded data rate and multicodeword WiMAX LDPC decoding on the CELL/B.E.”Electronics Letters, volume 44, no. 24, pp. 1415–1416, November 2008.

[J.40] R. Chaves, G. Kuzmanov, L. Sousa and S. Vassiliadis, “Cost-efficient SHA hardware accelerators,”IEEE Transactions on Very Large Scale Integration Systems (TVLSI), volume 16, no. 8, pp. 999–1008, August 2008.

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5.2 Journal papers 7

[J.41] P. Tom´as and L. Sousa, “Statistical analysis of a spike train distance in Poisson models,” IEEE Signal Processing Letters, volume 15, pp. 357–360, 2008.

[J.42] F. Cardoso, J. Germano, R. Ferreira, S. Cardoso, V. Martins, P. Freitas, M.Piedade and L. Sousa, “Detection of 130 nm magnetic particles by a portable electronic platform using spin valve and magnetic tunnel junction sensors,”Journal of Applied Physics, volume 103, p. 07A310, February 2008.

[J.43] T. Dias, N. Roma, L. Sousa and M. Ribeiro, “Reconfigurable architectures and processors for real-time video motion estimation,”Journal of Real-Time Image Processing, volume 2, no. 4, pp. 191–205, December 2007.

[J.44] N. Roma and L. Sousa, “Efficient hybrid dct-domain algorithm for any arbitrary integer re-size video downscaling,”EURASIP Journal on Advances in Signal Processing - Special issue on Video Adaptation for Heterogeneous Environments, , no. Article ID 57291, pp. 1–16, September 2007.

[J.45] R. Chaves and L. Sousa, “Improving residue number system multiplication with more balanced moduli sets and enhanced modular arithmetic structures,”Journal Computers & Digital Techniques, volume 1, no. 5, pp. 472–480, September 2007.

[J.46] F. Cardoso, R. Ferreira, S. Cardoso, J. Conde, V. Chu, P. Freitas, J. Germano, T. Almeida, L. Sousa and M. Piedade, “Noise characteristics and particle detection limits in diode+MTJ matrix elements for biochip applications,”IEEE Transactions on Magnetics, volume 43, no. 6, pp. 2403–2405, June 2007.

[J.47] T. Dias, S. Momcilovic, N. Roma and L. Sousa, “Adaptive motion estimation processor for autonomous video devices,”EURASIP Journal on Embedded Systems, , no. 57234, May 2007.

[J.48] S. Yamagiwa and L. Sousa, “Caravela: A novel environment for stream-based distributed computing,”

IEEE Computer Magazine, volume 40, pp. 70–77, May 2007.

[J.49] M. Piedade, L. Sousa, T. Almeida, J. Germano, B. Costa, J. Lemos, P. Freitas, H. Ferreira and F. Car-doso, “A new hand-held microsystem architecture for biological analysis,”IEEE Transactions on Circuits and Systems-I: Regular Papers, volume 53, pp. 2384–2395, November 2006.

[J.50] F. Cardoso, H. Ferreira, J. Conde, P. Freitas, D. Vidal, J. Germano, L. Sousa, M. Piedade, B. Costa and J. Lemos, “Diode/magnetic tunnel junction cell for fully scalable matrix-based biochip,”Journal of Applied Physics, volume 99, p. 08B307, April 2006.

[J.51] O. Sinnen, L. Sousa and F. Sandnes, “Towards a realistic task scheduling model,” IEEE Transactions on Parallel and Distributed Systems, volume 17, no. 3, pp. 263–275, March 2006.

[J.52] M. Piedade, J. Gerald, L. Sousa, G. Tavares and P. Tom´as, “Visual neuroprosthesis: A non invasive system for stimulating the cortex,” IEEE Transactions on Circuits and Systems-I: Regular Papers, volume 52, no. 12, pp. 2648–2662, December 2005.

[J.53] L. Sousa and R. Chaves, “A universal architecture for designing efficient modulo 2n+ 1 multipliers,”

IEEE Transactions on Circuits and Systems-I: Regular Papers, volume 52, no. 6, pp. 1166–1178, June 2005.

[J.54] O. Sinnen and L. Sousa, “Communication contention in task scheduling,”IEEE Transactions on Parallel and Distributed Systems, volume 16, no. 6, pp. 503–515, June 2005.

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[J.55] O. Sinnen and L. Sousa, “On task scheduling accuracy: Evaluation methodology and results,” The Journal of Supercomputing, volume 27, no. 2, pp. 177–194, February 2004.

[J.56] O. Sinnen and L. Sousa, “List scheduling: Extension for contention awareness and evaluation of node priorities for heterogeneous cluster architectures,” Parallel Computing, volume 30, no. 1, pp. 81–101, January 2004.

[J.57] N. Roma and L. Sousa, “Fast transcoding architectures for insertion of non-regular shaped objects in the compressed DCT-domain,”Signal Processing: Image Communication, volume 18, no. 8, pp. 659–683, September 2003.

[J.58] O. Sinnen and L. Sousa, “Experimental evaluation of task scheduling accuracy: Implications for the scheduling model,”IEICE Transactions on Information and Systems, volume E86-D, no. 9, pp. 1620– 1627, September 2003.

[J.59] N. Roma and L. Sousa, “Automatic synthesis of motion estimation processors based on a new class of hardware architectures,” Journal of VLSI Signal Processing-Systems for Signal, Image, and Video Technology, volume 34, no. 3, pp. 277–290, July 2003.

[J.60] L. Sousa, “Algorithm for modulo (2n+ 1) multiplication,” IEE Electronics Letters, volume 39, no. 9, pp. 752–754, May 2003.

[J.61] N. Roma and L. Sousa, “Efficient and configurable full search block matching processors,”IEEE Tran-sactions on Circuits and Systems for Video Technology, volume 12, no. 12, pp. 1160–1167, December 2002.

[J.62] L. Sousa, “A general method for eliminating redundant computations in video coding,”IEE Electronics Letters, volume 36, no. 4, pp. 306–307, February 2000.

5.3

Conference papers (refereed)

[C.1] P. Martins and L. Sousa, “Stretching the limits of programmable embedded devices for public-key cryp-tography,” inSecond Workshop on Cryptography and Security in Computing Systems (CS2), September 2015.

[C.2] A. Ilic, S. Momcilovic, N. Roma and L. Sousa, “FEVES: Framework for efficient parallel video encoding on heterogeneous systems,” in43rd International Conference on Parallel Processing (ICPP), September 2014.

[C.3] J. Andrade, F. Pratas, G. Falc ao, V. Silva and L. Sousa, “Combining flexibility with low power: Dataflow and widepipeline LDPC decoding engines in the Gbit/s era,” in25th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2014.

[C.4] H. Pettenghi, R. Chaves, L. Sousa and J. Ambrose, “Method for designing multi-channel RNS architec-tures to prevent power analysis SCAs,” inInternational Symposium on Circuits and Systems (ISCAS), 2014.

[C.5] D. Souza, N. Roma and L. Sousa, “Cooperative CPU+GPU deblocking filter parallelization for high performance HEVC video codecs,” in39th International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 2014, pp. 5026–5030.

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5.3 Conference papers (refereed) 9

[C.6] P. Matutino, R. Chaves and L. Sousa, “A compact and scalable RNS architecture,” in 24th IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), 2013, pp. 125–132.

[C.7] S. Ant˜ao and L. Sousa, “An RNS-based architecture targeting hardware accelerators for modular arith-metic,” in 38th International Conference on Acoustics, Speech, and Signal Processing (ICASSP), May 2013.

[C.8] F. Pratas, D. Oriato, O. Pell, R. Mata and L. Sousa, “Accelerating the computation of induced dipo-les for molecular mechanics with dataflow engines,” in 21st IEEE International Symposium on Field-Programmable Custom Computing Machines (FCCM), May 2013, pp. 177–180.

[C.9] J. Ambrose, H. Pettenghi and L. Sousa, “DARNS: A randomized multi-modulo rns architecture for double-and-add in ECC to prevent power analysis side channel attacks,” inASP-DAC, January 2013, pp. 620–625.

[C.10] T. Dias, L. Ros´ario, N. Roma and L. Sousa, “High performance unified architecture for forward and inverse quantization in H.264/AVC,” in15th Euromicro Conference on Digital System Design (DSD), September 2012.

[C.11] P. Matutino, H. Pettenghi, R. Chaves and L. Sousa, “RNS arithmetic units for modulo {2n±k},” in

15th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools (DSD), July 2012.

[C.12] F. Pratas, P. Tom´as, P. Trancoso and L. Sousa, “Energy efficient stream-based configurable architecture for embedded platforms,” inInternational Conference on Embedded Computer Systems: Architectures, Modeling and Simulation, July 2012.

[C.13] D. Clarke, A. Ilic, A. Lastovetsky and L. Sousa, “Hierarchical partitioning algorithm for scientific com-puting on highly heterogeneous CPU + GPU clusters,” inEuro-Par, May 2012, pp. 489–501.

[C.14] H. Pettenghi, L. Sousa and J. Ambrose, “Efficient implementation of multi-moduli architectures for binary-to-RNS conversion,” inThe 17th Asia and South Pacific Design Automation Conference (ASP-DAC), February 2012, pp. 819–824.

[C.15] A. Ilic and L. Sousa, “On realistic divisible load scheduling in highly heterogeneous distributed systems,” inPDP, Special Session on GPU Computing and Hybrid Computing, February 2012, pp. 426–433.

[C.16] P. Matutino, R. Chaves and L. Sousa, “Binary-to-RNS conversion units for moduli 2n ±3,” in 14th

EUROMICRO Conference on Digital System Design (DSD), IEEE, September 2011, pp. 460–467.

[C.17] T. Dias, S. Lopez, N. Roma and L. Sousa, “High throughput and scalable architecture for unified trans-form coding in embedded H.264/AVC video coding systems,” inInternational Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (SAMOS), July 2011, pp. 225–232.

[C.18] G. Falc˜ao, J. Andrade, V. Silva and L. Sousa, “Real-Time DVB-S2 LDPC decoding on many-core GPU accelerators,” in36th International Conference on Acoustics, Speech and Signal Processing (ICASSP), IEEE, July 2011, pp. 1685–1688.

[C.19] S. Ant˜ao and L. Sousa, “Exploiting SIMD extensions for linear image processing with OpenCL,” in

Proceedings of the 28th International Conference on Computer Design (ICCD), IEEE, October 2010, pp. 425–430.

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[C.20] T. Dias, N. Roma and L. Sousa, “Hardware/software co-design of H.264/AVC encoders for multi-core embedded systems,” inProceedings of the Conference on Design and Architectures for Signal and Image Processing (DASIP), October 2010.

[C.21] H. Pettenchi, R. Chaves, L. Sousa and M. Avedillo, “An improved RNS generator 2n±k based on threshold logic,” inProceedings of the 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), September 2010, pp. 119–124.

[C.22] T. Dias, N. Roma and L. Sousa, “H.264/AVC framework for multi-core embedded video encoders,” in

Proceedings of the International Symposium on System-on-Chip (SoC), September 2010.

[C.23] B. Francisco, F. Pratas and L. Sousa, “Unifying stream based and reconfigurable computing to design application accelerators,” inProceedings of the 18th IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), September 2010, pp. 408–413.

[C.24] P. Matutino, R. Chaves and L. Sousa, “Arithmetic units for RNS moduli 2n3 and 2n+3,” inProceedings

of the 13th Euromicro Conference On Digital System Design (DSD), September 2010.

[C.25] G. Falc˜ao, L. Sousa and V. Silva, “Embedded multicore architectures for LDPC decoding,” in Proce-edings of the International Conference on Embedded Computer Systems: Architectures, Modeling and Simulation (IC-SAMOS), IEEE, July 2010, pp. 349–356.

[C.26] S. Ant˜ao, J. Bajard and L. Sousa, “Elliptic curve point multiplication on GPUs,” in Proceedings of the 21st IEEE International Conference on Application-specific Systems, Architectures and Processors (ASAP), July 2010.

[C.27] K. Gbolagade, R. Chaves, L. Sousa and S. Cotofana, “An improved reverse converter for the {22n+1

1,2n,2n1}moduli set,” inProceedings of the IEEE International Symposium on Circuits and Systems

(ISCAS), May 2010, pp. 2103–2106.

[C.28] S. Momcilovic and L. Sousa, “Programming Cell/B.E. and GPU based systems for real-time video encoding,” inProceedings of Proceedings of SPIE, Real-Time Image and Video Processing Conference, Bruxelas, B´elgica, April 2010, volume 7724.

[C.29] S. Ant˜ao, R. Chaves and L. Sousa, “AES and ECC cryptography processor with runtime configuration,” inProceedings of the Seventeenth International Conference on Advanced Computing and Communicati-ons, IEEE, December 2009.

[C.30] K. Glolagade, R. Chaves, S. Cotofana and L. Sousa, “Residue-to-binary converter for the moduli set

{22n+1,22n,2n1},” inProceedings of the 2nd International Conference on Adaptive Science &

Tech-nology, IEEE, December 2009, pp. 26–33.

[C.31] F. Pratas, P. Trancoso, A. Stamatakis and L. Sousa, “Fine-grain parallelism using multi-core, Cell/B.E., and GPU systems: Accelerating the phylogenetic likelihood function,” inProceedings of the International Conference on Parallel Processing (ICPP), IEEE, September 2009, pp. 9–17.

[C.32] G. Passos, N. Roma, B. Costa, L. Sousa and J. Lemos, “Distributed software platform for automation and control of general anaesthesia,” inProceedings of the 8th International Symposium on Parallel and Distributed Computing (ISPDC), IEEE Computer Society Press, July 2009, pp. 135–142.

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5.3 Conference papers (refereed) 11

[C.33] S. Yamagiwa and L. Sousa, “CaravelaMPI: Message passing interface for parallel gpu-based appli-cations,” in Proceedings of the 8th International Symposium on Parallel and Distributed Computing (ISPDC), IEEE Computer Society Press, July 2009, pp. 161–168.

[C.34] G. Falc˜ao, V. Silva and L. Sousa, “How GPUs can outperform ASICs for fast LDPC decoding,” in

Proceedings of the 23rd International Conference on Supercomputing (ICS), ACM, June 2009, pp. 390– 399.

[C.35] L. Sousa, S. Momcilovic, V. Silva and G. Falc˜ao, “Multi-core platforms for signal processing: Source and channel coding,” inProceedings of the IEEE International Conference on Multimedia and Expo, June 2009, pp. 1809–1812.

[C.36] S. Ant˜ao, R. Chaves and L. Sousa, “Compact and flexible microcoded elliptic curve processor for recon-figurable devices,” in Proceedings of the 17th IEEE Symposium on Field-Programmable Custom Com-puting Machines (FCCM), IEEE Computer Society, April 2009, pp. 193–200.

[C.37] J. Germano, R. Ramalho and L. Sousa, “On the design of distributed autonomous embedded systems for biomedical applications,” in Proceedings of the 3rd International Conference on Pervasive Computing Technologies for Healthcare (Pervasive Health), IEEE, April 2009, pp. 1–8.

[C.38] G. Falc˜ao, L. Sousa, V. Silva and J. Marinho, “Parallel LDPC decoding on the cell/b.e. processor,” in

Proceedings of the 4th International Conference on High Performance and Embedded Architectures and Compilers (HiPEAC), Springer, January 2009, Lecture notes in Computer Science, pp. 389–403.

[C.39] S. Ant˜ao, R. Chaves and L. Sousa, “Fpga elliptic curve cryptographic processor over GF(2m),” in

Pro-ceedings of the International Conference on Field-Programmable Technology (ICFPT), IEEE, December 2008, pp. 357–360.

[C.40] N. Sebasti˜ao, T. Dias, N. Roma, P. Flores and L. Sousa, “Application specific programmable ip core for motion estimation: technology comparison targeting efficient embedded co-processing units,” in

Proceedings of the 11th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools (DSD), IEEE Computer Society, September 2008, pp. 181–188.

[C.41] P. Matutino and L. Sousa, “An RNS based specific processor for computing the minimum,” inProceedings of the 11th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools (DSD), IEEE Computer Society Press, September 2008, pp. 768–775.

[C.42] R. Chaves, G. Kuzmanov and L. Sousa, “On-the-fly attestation of reconfigurable hardware,” in Pro-ceedings of the International Conference on Field Programmable Logic and Applications (FPL), IEEE, September 2008, pp. 71–76.

[C.43] A. Ilic, F. Pratas and L. Sousa, “Distributed web-based platform for computer architecture simulation,” in Proceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC), IEEE CS, July 2008, pp. 317–324.

[C.44] S. Yamagiwa, K. Wada and L. Sousa, “Heuristic optimization methods for improving performance of recursive general purpose applications on gpus,” inProceedings of the 7th International Symposium on Parallel and Distributed Computing (ISPDC), IEEE CS, July 2008, pp. 325–332.

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[C.45] V. Martins, F. Cardoso, J. Loureiro, M. Mercier, J. Germano, S. Cardoso, R. Ferreira, L. Fonseca, L. Sousa, M. Piedade and P. Freitas, “Integrated spintronic platforms for biomolecular recognition detec-tion,” inProceedings of the Conference on Biomagnetism and Magnetic Biosystems based on Molecular Recognition Processes, AIP, June 2008, volume 1025, pp. 150–175.

[C.46] F. Pratas, B. Mladen, G. Gaydadjiev, L. Sousa and S. Kaxiras, “Low power microarchitecture with instruction reuse,” inProceedings of the ACM International Conference on Computing Frontiers, May 2008, pp. 149–157.

[C.47] R. Chaves, G. Kuzmanov, L. Sousa and S. Vassiliadis, “Merged computation for whirlpool hashing,” in Proceedings of the Design, Automation and Test in Europe (DATE), IEEE/ACM, March 2008, pp. 272–275.

[C.48] S. Yamagiwa, D. Ant˜ao and L. Sousa, “Design and implementation of a graphical user interface for stream-based distributed computing,” inProceedings of the IASTED International Conference on Pa-rallel and Distributed Computing and Networks (PDCN), February 2008.

[C.49] G. Falc˜ao, V. Silva, M. Gomes and L. Sousa, “Edge stream oriented LDPC decoding,” in Proceedings of the 16th Euromicro International Conference on Parallel, Distributed and network-based Processing (PDP), IEEE, February 2008, pp. 237–244.

[C.50] G. Falc˜ao, L. Sousa and V. Silva, “Massive parallel LDPC decoding on GPU,” in Proceedings of the 13th Symposium on Principles and Practice of Parallel Programming (PPoPP), ACM, February 2008, pp. 83–90.

[C.51] R. Chaves, B. Donchev, G. Kuzmanov, L. Sousa and S. Vassiliadis, “BRAM-LUT tradeoff on a poly-morphic DES design,” inProceedings of the International Conference on High Performance Embedded Architectures & Compilers (HiPEAC), Springer Verlag, January 2008, volume 4917 of Lecture notes on Computer Science, pp. 55–65.

[C.52] P. Tom´as, J. Martins and L. Sousa, “Towards a unified model for the retina: Static vs dynamic integrate and fire models,” in Proceedings of the International Conference on Bio-Inspired Systems and Signal Processing (BIOSIGNALS), January 2008.

[C.53] N. Roma and L. Sousa, “Fully compressed domain transcoder for PIP/PAP video composition,” in

Proceedings of the 26th Picture Coding Symposium (PCS), EURASIP, November 2007.

[C.54] T. Teod´osio and L. Sousa, “QCA-LG: A tool for the automatic layout generation of QCA combinational circuits,” inProceedings of the 25th Norchip Conference, IEEE, November 2007.

[C.55] P. Tom´as and L. Sousa, “Feature selection for the stochastic integrate and fire model,” in Proceedings of the International Symposium on Intelligent Signal Processing (WISP), IEEE, October 2007.

[C.56] S. Martins, L. Sousa and J. Martins, “Additive logistic regression applied to retina modelling,” in Pro-ceedings of the IEEE International Conference on Image Processing (ICIP), September 2007, volume 3, pp. 309–312.

[C.57] S. Capela, P. Tom´as and L. Sousa, “Stochastic integrate-and-fire model for the retina,” in Proceedings of the 15th European Signal Processing Conference (EUSIPCO), September 2007, pp. 2514–2518.

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5.3 Conference papers (refereed) 13

[C.58] M. Ribeiro and L. Sousa, “A run-time reconfigurable processor for video motion estimation,” in Procee-dings of the 17th International Conference on Field Programmable Logic and Applications (FPL), IEEE, August 2007, pp. 726–729.

[C.59] S. Momcilovic, N. Roma and L. Sousa, “Adaptive motion estimation algorithm for H.264/AVC,” in

Proceedings of the 15th International Conference on Digital Signal Processing (DSP), IEEE, July 2007, pp. 519–522.

[C.60] P. Tom´as and L. Sousa, “An efficient expectation-maximisation algorithm for spike classification,” in

Proceedings of the 15th International Conference on Digital Signal Processing (DSP), IEEE, July 2007, pp. 203–206.

[C.61] S. Yamagiwa, L. Sousa and T. Brand˜ao, “Meta-pipeline: A new execution mechanism for distributed pipeline processing,” in Proceedings of the 6th International Symposium on Parallel and Distributed Computing (ISPDC), IEEE CS, July 2007.

[C.62] L. Sousa, “Efficient method for magnitude comparison in RNS based on two pairs of conjugate moduli,” inProceedings of the IEEE International Symposium on Computer Arithmetic (ARITH18), June 2007, pp. 240–247.

[C.63] P.Lopes, J. Germano, T. Almeida, L. Sousa, M. Piedade, F. Cardoso, H. Ferreira and P. Freitas, “A new handheld biochip-based microsystem,” inProceedings of the IEEE International Symposium on Circuits and Systems (ISCAS), May 2007, pp. 2379–2382.

[C.64] S. Yamagiwa and L. Sousa, “Design and implementation of a stream-based distributed computing plat-form using graphics processing units,” inProceedings of the ACM International Conference on Compu-ting Frontiers, May 2007, pp. 197–204.

[C.65] L. Sousa, F. Alegria and J. Germano, “Developing and integrating lab projects as important learning components in an embedded systems course,” inProceedings of the International Conference on Micro-electronic Systems Education (MSE), IEEE, June 2007.

[C.66] S. Yamagiwa, L. Sousa and D. Ant˜ao, “Data buffering optimization methods toward a uniform pro-gramming interface for GPU-based applications,” inProceedings of the ACM International Conference on Computing Frontiers, May 2007, pp. 205–212.

[C.67] L. Sousa, M. Piedade, J. Germano, T. Almeida, P. Lopes, F. Cardoso and P. Freitas, “Generic ar-chitecture designed for biomedical embedded systems,” in Proceedings of the International Embedded Systems Symposium (IESS), Springer, April 2007, volume 61 of IFIP Advances in Information and Communication Technology, pp. 353–362.

[C.68] P. Lopes, T. Almeida, L. Sousa, M. Piedade, F. Cardoso, H. Ferreira and P. Freitas, “Determination of biological expression signals on a new hand held biochip-based microsystem,” inProceedings of the Biomedical Circuits and Systems Conference (BIOCAS), IEEE, November 2006, pp. 57–60.

[C.69] T. Almeida, M. Piedade, J. Germano, P. Lopes, L. Sousa, F. Cardoso, H. Ferreira and P. Freitas, “Measurements and modelling of a magnetoresistive biosensor,” inProceedings of the Biomedical Circuits and Systems Conference (BIOCAS), IEEE, November 2006, pp. 41–44.

[C.70] J. Germano, M. Piedade, L. Sousa, T. Almeida, P. Lopes, F. Cardoso, H. Ferreira and P. Freitas, “Microsystem for biological analysis based on magnetoresistive sensing,” in Proceedings of the XVIII IMEKO World Congress, September 2006.

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[C.71] T. Almeida, M. Piedade, P. Lopes, L. Sousa, J. Germano, F. Cardoso, H. Ferreira and P. Freitas, “Mag-netoresistive biosensor modelling for biomolecular recognition,” in Proceedings of the XVIII IMEKO World Congress, September 2006.

[C.72] S. Momcilovic, T. Dias, N. Roma and L. Sousa, “Application specific instruction set processor for adap-tive video motion estimation,” inProceedings of the 9th EUROMICRO Conference on Digital System Design: Architectures, Methods and Tools (DSD), IEEE Computer Society, August 2006, pp. 160–167.

[C.73] N. Roma and L. Sousa, “Least squares motion estimation algorithm in the compressed DCT domain for H.26x/MPEG-x video sequences,” inProceedings of IEEE International Conference on Advanced Video and Signal-Based Surveillance (AVSS), Como, It´alia, September 2005, pp. 576–581.

[C.74] T. Dias, N. Roma and L. Sousa, “Efficient VLSI architecture for real-time motion estimation in advan-ced video coding,” inProceedings of IEEE International SOC Conference (SOCC), Washington, EUA, September 2005, pp. 91–92.

[C.75] J. Martins and L. Sousa, “Performance comparison of computational retina models,” in Proceedings of the 5th IASTED International Conference on Visualization, Imaging and Image Processing (VIIP), Benidorm, Espanha, September 2005, pp. 156–161.

[C.76] S. Vassiliadis, L. Sousa and G. Gaydadjiev, “The midlifekicker microarchitecture evaluation metric,” in

Proceedings of the IEEE International Conference on Application-Specific Systems, Architectures and Processors (ASAP), Samos, Gr´ecia, July 2005, pp. 92–97.

[C.77] R. Guapo, S. Yamagiwa and L. Sousa, “On the implementation and evaluation of Berkeley sockets on Maestro2 cluster computing environment,” inProceedings of the 3rd IEEE International Symposium on Parallel and Distributed Computing (ISPDC), Lille, Fran¸ca, July 2005, pp. 317–324.

[C.78] M. Leong, P. Vasconcelos, J. Fernandes and L. Sousa, “A programmable cellular neural network circuit,” inProceedings of the 17th Symposium on Integrated Circuits and System Design (SBCCI), ACM, Brasil, September 2004, pp. 186–191.

[C.79] R. Chaves and L. Sousa, “{2n+ 1,2n+k,2n−1}: A new RNS moduli set extension,” in Proceedings of

the IEEE Euromicro Symposium On Digital System Design: Architectures, Methods and Tools (DSD), Rennes, Fran¸ca, September 2004, pp. 210–217.

[C.80] K. Ferreira, S. Yamagiwa, L. Sousa, K. Aoki, K. Wada and L. Campos, “Distributed shared memory system based on the Maestro2 high performance cluster network,” in Proceedings of the 3rd IEEE International Symposium on Parallel and Distributed Computing (ISPDC), Cork, Irlanda, July 2004, pp. 91–96.

[C.81] S. Yamagiwa, K. Ferreira, L. Campos, K. Aoki, M. Ono, K. Wada, M. Fukuda and L. Sousa, “On the performance of Maestro2 high performance network equipment, using new improvement techniques,” in

Proceedings of the 23rd IEEE International Performance Computing and Communications Conference (IPCCC), Arizona, EUA, April 2004, pp. 103–110.

[C.82] R. Chaves and L. Sousa, “RDSP: A RISC DSP based on residue number system,” in Proceedings of the IEEE Euromicro Symposium On Digital System Design: Architectures, Methods and Tools (DSD), Antalya, Turquia, September 2003, pp. 128–135.

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5.3 Conference papers (refereed) 15

[C.83] L. Sousa, P. Tomas, F. Pelayo, A. Martinez, C. Morillas and S. Romero, “A FPL bioinspired visual encoding system to stimulate cortical neurons in real-time,” in Proceedings of the International Con-ference on Field Programmable Logic and Applications (FPL), Springer, Lisboa, Portugal, September 2003, volume 2778 ofLecture Notes in Computer Science, pp. 691–700.

[C.84] F. Pelayo, A. Martinez, C. Morillas, S. Romero, L. Sousa and P. Tomas, “Retina-like processing and coding platform for cortical neuro-stimulation,” in Proceedings of the 25th International Conference Engineering in Medicine and Biology Society, IEEE, Cancun, Mexico, September 2003, pp. 2023–2026.

[C.85] N. Roma, T. Dias and L. Sousa, “Customisable core-based architectures for real-time motion estimation on FPGAs,” inProceedings of the International Conference on Field Programmable Logic and Applica-tions (FPL), Springer, Lisboa, Portugal, September 2003, volume 2778 ofLecture notes in Computer Science, pp. 745–754.

[C.86] O. Sinnen and L. Sousa, “Experimental evaluation of task scheduling accuracy,” in Proceedings of 3rd International Conference on Parallel and Distributed Computing, Applications and Technologies (PD-CAT), Kanazawa, Jap˜ao, September 2002, pp. 378–383.

[C.87] J. Salvado and L. Sousa, “Video coding by using the 3D zero-tree approach in the wavelet transform domain,” inProceedings of the 14th International Conference on Digital Signal Processing (DSP’2002), IEEE, Santorini, Gr´ecia, July 2002, volume 2, pp. 683–687.

[C.88] N. Roma and L. Sousa, “Insertion of irregular-shaped logos in the compressed DCT domain,” in Proce-edings of the 14th International Conference on Digital Signal Processing (DSP’2002), IEEE, Santorini, Gr´ecia, July 2002, volume 1, pp. 125–128.

[C.89] N. Roma and L. Sousa, “A new VLSI architecture for full search block matching,” in Proceedings of the IFIP International Conference on Very Large Scale Integration (VLSI-SoC), Montpellier, Fran¸ca, December 2001, pp. 213–218.

[C.90] O. Sinnen and L. Sousa, “Exploiting unused time slots in list-scheduling considering communication contention,” in Proceedings of the Euro-Par 2001 Parallel Processing, Springer, Manchester, Reino Unido, August 2001, volume 2150 ofLecture notes in Computer Science, pp. 166–170.

[C.91] O. Sinnen and L. Sousa, “Scheduling task graphs on arbitrary processor architectures considering con-tention,” in Proceedings of the High Performance Computing and Networking, Springer, Amesterd˜ao, Holanda, June 2001, volume 2110 ofLecture notes in Computer Science, pp. 373–382.

[C.92] O. Sinnen and L. Sousa, “A platform independent parallelising tool based on graph theoretic models,” in Vector and Parallel Processing - VECPAR 2000 selected papers, Springer, Porto, Portugal, 2001, volume 1981 ofLecture notes in Computer Science, pp. 154–167.

[C.93] O. Sinnen and L. Sousa, “A comparative analysis of graph models to develop parallelising tools,” in Pro-ceedings of the International Conference on Applied Informatics, IASTED, Innsbruck, ´Austria, February 2000, pp. 832–838.

[C.94] L. Sousa, “Applying conditional processing to design low-power array processors for motion estimation,” inProceedings of the International Conference on Image Processing, IEEE, Kobe, Jap˜ao, October 1999, volume 2, pp. 769–773.

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[C.95] J. Isidro, L. Coelho, K. Ferreira and L. Sousa, “On the development of a video CODEC for low bitrate communication in general purpose computers,” inProceedings of the International Conference on Applied Informatics, IASTED, Innsbruck, ´Austria, February 1999, pp. 285–288.

[C.96] L. Sousa, “Bidirectional systolic arrays for digital recursive filters,” in Proceedings of the IEEE Inter-national Conference on Electronic Circuits and Systems, IEEE, Lisboa, Portugal, September 1998, pp. 499–502.

[C.97] L. Sousa and M. Piedade, “A new orthogonal multiprocessor and its application to image processing,” in

Proceedings of the International Conference on High Performance Computing, IEEE/ACM, Bangalore, India, December 1997, pp. 511–516.

[C.98] L. Sousa and M. Piedade, “Simulation of SIMD and MIMD shared memory architectures on UNIX based systems,” in Proceedings of the International Symposium on Circuits and Systems, IEEE, Calif´ornia, EUA, May 1992, volume 2, pp. 637–640.

[C.99] L. Sousa, J. B´arrios, A. Costa and M. Piedade, “Parallel image processing for transputer based sys-tems,” inProceedings of the International Conference on Image Processing and its Applications, IEE, Maastricht, Holanda, April 1992, pp. 33–36.

[C.100] L. Sousa, J. Caeiro and M. Piedade, “An advanced architecture for image processing and analysis,” in

Proceedings of the International Symposium on Circuits and Systems (ISCAS), IEEE, Singapura, May 1991, volume 1, pp. 77–80.

[C.101] L. Sousa, M. Piedade and J. Caeiro, “A high performance image processing system,” inProceedings of the International Symposium on Circuits and Systems (ISCAS), IEEE, Nova Orle˜aes, EUA, May 1990, volume 1, pp. 751–754.

5.4

Workshop papers (refereed)

[W.1] S. Momcilovic, N. Roma and L. Sousa, “Multi-level parallelization of advanced video coding on hy-brid CPU+GPU platforms,” inInternational Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar), August 2012.

[W.2] A. Ilic and L. Sousa, “Simultaneous multi-level divisible load balancing for heterogeneous desktop sys-tems,” in ISPA 2012, International Workshop on Heterogeneus Architectures and Computing, March 2012, pp. 683–690.

[W.3] A. Ilic and L. Sousa, “Scheduling divisible loads on heterogeneous desktop systems with limited memory,” in Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar), July 2011.

[W.4] P. Petrides, F. Pratas, L. Sousa and P. Trancoso, “Virtualization for morphable multi-cores,” in

Workshop on Parallel Programming and Run-time Management Techniques for Many-core Architec-tures, January 2011.

[W.5] R. Ramalho, P. Tom´as and L. Sousa, “Efficient independent component analysis on a GPU,” in Proce-edings of the International Workshop on Frontier of GPU Computing (FGC), IEEE Computer Society Press, July 2010.

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5.4 Workshop papers (refereed) 17

[W.6] A. Rodrigues, N. Roma and L. Sousa, “p264: Open platform for designing parallel H.264/AVC video encoders on multi-core systems,” inProceedings of the International Workshop on Network and Operating Systems Support for Digital Audio and Video (NOSSDAV), ACM, June 2010, pp. 81–86.

[W.7] A. Ilic and L. Sousa, “Collaborative execution environment for heterogeneous parallel systems,” in

Proceedings of the 12th Workshop on Advances in Parallel and Distributed Computational Models (APDCM/IPDPS 2010), May 2010.

[W.8] F. Pratas, R. Mata and L. Sousa, “Iterative induced dipoles computation for molecular mechanics on GPUs,” in Proceedings of the 3rd Workshop on General Purpose Processing on Graphics Processing Units (co-located with ASPLOS), ACM, February 2010, pp. 111–120.

[W.9] S. Momcilovic and L. Sousa, “Development and evaluation of scalable video motion estimators on GPU,” inProceedings of the Workshop on Signal Processing Systems (SiPS), IEEE, October 2009, pp. 291–296.

[W.10] F. Pratas and L. Sousa, “Applying the stream-based computing model to design hardware accelerators: A case study,” inProceedings of the International Workshop on Systems, Architectures, Modeling, and Simulation, Springer, July 2009, LNCS, pp. 237–246.

[W.11] T. Tulabandhula, S. Ant˜ao and L. Sousa, “A class of software-hardware processors for fingerprint mat-ching on the fourier domain,” inProceedings of the 3rd HiPEAC Workshop on Reconfigurable Computing, January 2009.

[W.12] S. Yamagiwa and L. Sousa, “Design and implementation of a tool for modeling and programming deadlock free meta-pipeline applications,” inProceedings of the 10th Workshop on Advances on Parallel and Distributed Processing Symposium (APDCM/IPDPS), IEEE, April 2008.

[W.13] S. Momcilovic and L. Sousa, “A parallel algorithm for advanced video motion estimation on multi-core architectures,” in Proceedings of the International Workshop on Multi-Core Computing Systems (MuCoCoS), IEEE, March 2008, pp. 831–836.

[W.14] G. Fernandes, S. Yamagiwa, V. Silva and L. Sousa, “Stream-based LDPC decoding on GPUs,” in Proce-edings of the First Workshop on General Purpose Processing on Graphics Processing Units, September 2007.

[W.15] S. Momcilovic, N. Roma and L. Sousa, “An ASIP approach for adaptive motion estimation on AVC,” in

Proceedings of the IEEE 3rd Conference on PhD Research in Microelectronics and Electronics (PRIME), July 2007, pp. 165–168.

[W.16] R. Chaves, G. Kuzmanov, L. Sousa and S. Vassiliadis, “Improving SHA-2 hardware implementations,” inProceedings of the Workshop on Cryptographic Hardware and Embedded Systems (CHES), Springer, October 2006, LNCS, pp. 298–310.

[W.17] T. Dias, N. Roma and L. Sousa, “Low power distance measurement unit for real-time hardware motion estimators,” inProceedings of the International Workshop on Power and Timing Modeling, Optimization and Simulation (PATMOS), Springer, September 2006, volume 4148 of Lecture notes in Computer Science, pp. 247–255.

[W.18] R. Chaves, G. Kuzmanov, L. Sousa and S. Vassiliadis, “Rescheduling for optimized SHA-1 calculation,” inProceedings of the SAMOS Workshop on Computer Systems Architectures Modelling and Simulation, Springer, July 2006, volume 4017 ofLNCS, pp. 425–434.

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[W.19] R. Chaves, G. Kuzmanov, S. Vassiliadis and L. Sousa, “Reconfigurable memory based AES co-processor,” in Proceedings of IEEE 20th International Parallel & Distributed Processing Symposium, 13th Reconfigurable Architectures Workshop, IEEE Computer, April 2006.

[W.20] R. Piedade and L. Sousa, “Configurable embedded core for controlling electro-mechanical systems,” in

Proceedings of the Applied Reconfigurable Computing Workshop (ARC), Springer Verlag, February 2006, volume 3985 ofLecture notes on Computer Science, pp. 18–23.

[W.21] T. Dias, N. Roma and L. Sousa, “Efficient motion vector refinement architecture for sub-pixel motion estimation systems,” inProceedings of IEEE Workshop on Signal Processing Systems (SiPS), Atenas, Gr´ecia, November 2005, pp. 313–318.

[W.22] O. Sinnen and L. Sousa, “Task scheduling: Considering the processor involvement in communication,” inProceedings of the IEEE International Workshop on Algorithms, Models and Tools for Parallel Com-puting on Heterogeneous Networks (HeteroPar), Cork, Irlanda, July 2004, pp. 328–335.

[W.23] O. Sinnen and L. Sousa, “Comparison of contention aware list scheduling heuristics for cluster compu-ting,” inProceedings of the Workshop on Scheduling and Resource Management for Cluster Computing (ICPP), IEEE Computer Society Press, Valˆencia, Espanha, September 2001, pp. 382–387.

[W.24] N. Roma and L. Sousa, “Parameterizable hardware architectures for automatic synthesis of motion esti-mation processors,” inProceedings of IEEE Workshop on Signal Processing Systems (SiPS), Antu´erpia, B´elgica, September 2001, pp. 428–439.

[W.25] N. Roma and L. Sousa, “On the development and evaluation of specialized processors for computing high-order 2-D image moments in real-time,” inProceedings of the International Workshop on Computer Architectures for Machine Perception, IEEE, Padova, It´alia, September 2000, pp. 170–179.

[W.26] J. Brito and L. Sousa, “A video codec based on the TMS320C6X DSP,” inProceedings of the European DSP Education and Research Conference, Texas Instruments, Paris, Fran¸ca, September 2000.

[W.27] L. Sousa and N. Roma, “On the design of low-power array architectures for motion estimation,” in Proce-edings of the IEEE 3rd Workshop on Multimedia Signal Processing, Copenhaga, Dinamarca, September 1999, pp. 679–684.

[W.28] A. Abreu, N. Roma, J. Gerald and L. Sousa, “Digital video transmission through the electrical power lines,” in Proceedings of the European DSP Education and Research Conference, Texas Instruments, Paris, Fran¸ca, September 1998, pp. 16–21.

[W.29] A. Costa, J. B´arrios, L. Sousa and M. Piedade, “Low and intermediate parallel image processing for transputer base systems,” inProceedings of the European Workshops on Parallel Computing, Barcelona, Espanha, March 1992, pp. 393–396.

[W.30] O. Mealha, J. Delgado and L. Sousa et al, “PARSEC-parallel computing in signal processing and en-vironments for concurrent systems,” inProceedings of the Second Workshop of the Parallel Computing Action, Directorate General XXIII, Commission of the European Communities, December 1990, pp. 378–395.

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5.5 Book Chapters 19

5.5

Book Chapters

[BC.1] J. Andrade, G. Falc˜ao, V. Silva, S. Yamagiwa and L. Sousa,Encyclopedia of Computer Science and Te-chnology, Taylor and Francis Group, chapter Accelerating Conventional Processing Using GPU Clusters: LDPC Decoders, 2015.

[BC.2] L. Kuan, P. Tom´as and L. Sousa, Numerical Computations with GPUs, Springer, chapter Finite-Difference in Time-Domain scalable implementations on CUDA and OpenCL, July 2014.

[BC.3] A. Ilic and L. Sousa,High-Performance Computing on Complex Environments, Wiley, chapter 14: Effi-cient Multilevel Load Balancing on Heterogeneous CPU + GPU Systems, pp. 261–279, June 2014. [BC.4] D. Clarke, A. Ilic, A. Lastovetsky, V. Rychkov, L. Sousa and Z. Zhong, High-Performance Computing

on Complex Environments, Wiley, chapter 13: Design and Optimization of Scientific Applications for Highly Heterogeneous and Hierarchical HPC Platforms Using Functional Computation Performance Models, pp. 237–257, June 2014.

[BC.5] S. Ant ao, R. Chaves and L. Sousa, Embedded Systems: Hardware, Design and Implementation, John Wiley & Sons, chapter 14: Reconfigurable Architecture for Cryptography over Binary Finite Fields, pp. 319–362, January 2013.

[BC.6] A. Ilic, F. Pratas, P. Trancoso and L. Sousa, High Performance Computing: From Grids and Clouds to Exascale, IOS Press, chapter High-Performance Computing on Heterogeneous Systems: Database Queries on CPU and GPU, pp. 202–222, September 2011.

[BC.7] P. Tom´as, A. Ilic and L. Sousa, Biomedical Diagnostics and Clinical Technologies: Applying High-Performance Cluster and Grid Computing, IGI Global, chapter 9: Massive Data Classification of Neural Responses, February 2010.

[BC.8] G. Falc˜ao, V. Silva and L. Sousa, GPU Computing Gems, Morgan Kaufmann, chapter 39: Parallel LDPC Decoding, December 2010.

[BC.9] Gabriel Falc˜ao, Vitor Silva, Jos´e Marinho and Leonel Sousa, WIMAX New Developments, IN-TECH, chapter 6: LDPC Decoders for the WiMAX (IEEE 802.16e) based on Multicore Architectures, pp. 133–150, December 2009.

[BC.10] M. Piedade, J. Gerald, L. Sousa and G. Tavares, VLSI Circuits for Biomedical Applications, Artech House, chapter 2: Visual Cortical Neuroprosthesis: A System Approach, pp. 25–43, April 2008. [BC.11] S. Yamagiwa and L. Sousa, Concurrent & Parallel Computing: Theory, Implementation and

Appli-cations, Nova Science Publishers, chapter 1. Caravela: A High Performance Stream-based Concurrent Computing Platform, pp. 1–37, 2008.

[BC.12] N. Roma, T. Dias and L. Sousa, New Algorithms, Architectures and Applications for Reconfigurable Computing, Lysaght P. e Rosenstiel W. (Eds.), Springer-Verlag, chapter 5. Customisable and Reduced Hardware Motion Estimation Processors, pp. 55–66, 2005.

[BC.13] L. Sousa, P. Tom´as, F. Pelayo, A. Martinez, C. Morillas and S. Romero,New Algorithms, Architectures and Applications for Reconfigurable Computing, Lysaght P. e Rosenstiel W. (Eds.), Springer-Verlag, chapter 22. Bioinspired Stimulus Encoder for Cortical Visual Neuroprostheses, pp. 279–290, 2005.

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[BC.14] L. Sousa and N. Roma,SOC Design Methodologies, Kluwer Academic Publishers, volume 218 of IFIP International Federation for Information Processing, chapter A New VLSI Architecture for Full Search Block Matching Motion Estimation, pp. 253–264, 2002.

[BC.15] L. Sousa and M. Piedade, Parallel Algorithms for Digital Image Processing, Computer Vision and Neural Networks, Ioannis Pitas (Ed.), John Wiley & Sons, Nova Iorque, chapter Low Level Parallel Image Processing, pp. 25–52, 1993.

5.6

Edited Books, Proceedings, and Special Issues

[E.1] Farhana Sheikh and Leonel Sousa (eds.), Circuits and Systems for Security and Privacy, CRC Press, 2015.

[E.2] H. Lin, M. Alexander, M. Forsell, A. Kn¨upfer, R. Prodan, L. Sousa and A. Streit (eds.),Euro-Par 2009 - Parallel Processing Workshops, volume 6043 of Lecture Notes in Computer Science, Springer, June 2010.

[E.3] L. Sousa and Yves Robert (eds.),Proceedings of the Eighth International Symposium on Parallel and Distributed Computing, IEEE Computer Society, July 2009, ISBN 978-0-7695-3680-4.

[E.4] L. Sousa, N. O’Connor, M. Mattavelli and A. Nunez (eds.),EURASIP Journal of Embedded Systems, Editor respons´avel pelo n´umero especial emEmbedded Systems for Portable and Mobile Video Platforms, February 2007.

6

Supervision Ph. D. and (before Bologna) Master Theses

6.1

PhD Theses

2014 Aleksandar Ilic, ”Heterogeneous Systems: Load Balancing and Performance Modeling”, Electrical and Computer Engineering Department (DEEC), IST. First Employment: Pos-DOc at INESC-ID. 2013 Samuel Ant˜ao, ”High-performance and Embedded Systems for Cryptography”, Electrical and

Com-puter Engineering Department (DEEC), IST. First Employment: IBM Thomas J. Watson Research Center, NY, USA.

2013 Jo˜ao Martins, ”Computational Models, Neuronal Metrics and System Identification in Bioelectronic Vision”, (main advisor, co-advisor Prof. Jos´e Caeiro) Electrical and Computer Engineering Depart-ment (DEEC), IST. First EmployDepart-ment: Instituto Polit´ecnico de Beja, Portugal.

2012 Frederico Pratas, ”Stream-based Computing and Fine-grained Parallelism: from Algorithms to Re-configurable Hardware”, (main advisor, co-advisor Prof. Pedro Trancoso) Electrical and Computer Engineering Department (DEEC), IST. First Employment: Intel Labs Barcelona (ILBA), Spain. 2011 Jos´e Germano, ”A Hand-held Microsystem for Biological Analysis: Electronics, Signal Acquisition and

Processing for Information Extraction”, Electrical and Computer Engineering Department (DEEC), IST. First Employment: Post-Doc at INESC-ID, Portugal.

2011 Jos´e Sarmento, ”Optimized Digital Clock and Data Recovery Architectures”, DEEC, IST. First Em-ployment: Synopsis Portugal.

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6.2 Master Theses (before-Bologna, half-way between MSc. and Ph. D.) 21

2011 Svetislav Momcilovic, ”Parallel Video Coding on Multicore Platforms”, DEEC, IST. First Employ-ment: Post-Doc at INESC-ID, Portugal.

2010 Gabriel Fernandes, ”Parallel Algorithms and Architectures for LDPC Decoding”(main advisor, co-advisor Prof. Vitor Silva), Electrical and Computer Engineering Department, Universidade de Coim-bra. First Employment: Assistant Professor at Universidade de CoimCoim-bra.

2009 Pedro Tom´as, ”Neural Code: Tunning and Assessment of Retina Models”, DEEC, IST. First Em-ployment: Assistant Professor at DEEC, IST.

2008 Nuno Roma, ”Transform domain video transcoding systems for static and dynamic video composi-tion”, DEEC, IST. First Employment: Assistant Professor at the Informatics and Computer Engine-ering Department (DEIC), IST.

2007 Ricardo Chaves, ”Secure Computing on Reconfigurable Systems”(co-advisor), Faculty Electrical En-gineering, Mathematics and Computer Science, Technical University of Delft. First Employment: Assistant Professor at the Informatics and Computer Engineering Department (DEIC), IST.

2003 Oliver Sinnen, ”Accurate Task Scheduling for Parallel Systems”, DEEC, IST. First Employment: Lecturer at the Department of Electrical and Computer Engineering (ECE), University of Auckland, New Zealand.

6.2

Master Theses (before-Bologna, half-way between MSc. and Ph. D.)

2007 S´ergio Martins, ”Non-Linear Functionals for Retina Models”, Master in Electrical and Computer Engineering, IST.

2007 S´ergio Capela, ”Stochastic Integrate-and-Fire Retina Model”, Master in Electrical and Computer Engineering, IST.

2007 Miguel Nuno Ribeiro, ”A Configurable Processing Platform and its Application to Video Coding”, Master in Electrical and Computer Engineering, IST.

2006 Jo˜ao Martins, ”Computational Retina Models for Bioelectronic Vision”, Master in Electrical and Computer Engineering, IST.

2006 Gustavo Rocha, ”Graph Generation from Software Descriptions”, Master in Electrical and Computer Engineering, IST.

2005 Jos´e Germano , ”Portable System for DNA Analysis based on a Biochip”(co-supervised with Prof. Mois´s Piedade), Master in Electrical and Computer Engineering, IST.

2005 Pedro Tom´as, ”Algorithms and Tools for Automatic Generation of DSP Hardware Structures”, Master in Electrical and Computer Engineering, IST.

2004 Ricardo Guapo, ”Programming and Evaluation of the Berkeley Socket Interface on the Maestro2 Communication System”, Master in Electrical and Computer Engineering, IST.

2003 Tiago Dias, ”High Performance VLSI Motion Estimation Processors: Data Reuse and Sub-Pixel Accuracy”, Master in Electrical and Computer Engineering, IST.

2002 Ricardo Chaves, ”RDSP: Processador Digital de Sinal com Suporte para Aritm´etica por Res´ıduos”(thesis written in portuguese), Master in Electrical and Computer Engineering, IST.

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2002 Jos´e Salvado, ”Codifica¸c˜ao de V´ıdeo por Decomposi¸c˜ao 3D baseada na Transformada de ˆOndulas”(thesis written in portuguese), Master in Electrical and Computer Engineering, IST.

2001 Oliver Sinnen, ”Experimental Evaluation of Task Scheduling Accuracy”, Master in Electrical and Computer Engineering, IST.

2000 Nuno Roma, ”Processadores Dedicados para Estima¸c˜ao de Movimento em Sequˆencias de V´ıdeo”(thesis written in portuguese), Master in Electrical and Computer Engineering, IST.

7

Professional Services

In 2006, I was involved in the preparation of the document of the Thematic Group 7 ”Tera-Device Computing and Beyond”, which provides the European Commission with the vision, and also the major challenges of computer engineering in Europe.

7.1

Editorial Services

2014- Editor-in-Chief of the EURASIP Journal on Embedded Systems (JES), SpringerOpen Journal. 2014- Associate Editor and Member of the Editorial Board of the IEEE Transactions on Multimedia (TMM). 2014- Associate Editor and Member of the Editorial Board of the IEEE Transactions on Circuits and

Systems for Video Technology (TCSVT). 2014- Associate Editor of the IEEEAccess.

2013- Associate Editor of the Journal of Real-Time Image Processing, Springer.

2005-2013 Associate Editor of the EURASIP Journal on Embedded Systems (JES), SpringerOpen Journal. 2011 Guest editor for ”Follow-on of ISPDC’2009 and HeteroPar’2009”, volume 37, number 8 of theParallel

Computingjournal, Elsevier, together with Y. Robert and Denis Trystram.

2010 Editor for ”Euro-Par 2009 - Parallel Processing Workshops”, Lecture Notes in Computer Science, volume 6043, Springer, together with H. Lin, M. Alexander, M. Forsell, A. Kn¨upfer, R. Prodan and A. Streit.

2009 Editor of the ”Proceedings of the Eighth International Symposium on Parallel and Distributed Com-puting”, IEEE Computer Society, with Yves Robert.

2007 Guest editor for ”Embedded Systems for Portable and Mobile Video Platforms”, special issue of the EURASIP Journal on Embedded Systems, together with N. O’Connor, M. Mattavelli and A. Nunez.

7.2

Chairmanship, and Steering Committee Appointments

2015 Program co-chair of the IEEE International Symposium on Multimedia, Miami, Florida, USA. 2015 Co-Chair of the Special Session of ISCAS’15 on ”Special Session on ”Efficient Circuits and Systems

for HEVC and its 3D Encoding Extension”, Lisboa, Portugal.

2014 General Chair of 22th European Signal Processing Conference (EUSIPCO), EURASIP, Lisboa, Por-tugal.

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7.3 Program Committee Membership 23

2014 Track Chair of the the 25th International Symposium on Computer Architecture and High Perfor-mance Computing, Paris, France.

2013 Program Co-Chair of The Workshop on Power and Energy Aspects of Computation, co-located with the 10th International Conference on Parallel Processing and Applied Mathematics (PPAM), Warsaw, Poland.

2011 General Chair of Topic 3,Scheduling and Load Balancing, Euro-Par, Bordeaux, France.

2010 Co-Chair of The Applications, Systems, Architectures, and Processors Track, of the International Symposium on Systems, Architectures, MOdeling and Simulation, (IC-SAMOS), IEEE, Samos, Gre-ece.

2010 General Co-Chair of the 4th HiPEAC Workshop on Reconfigurable Computing (WRC), co-located with the International Conference on High Performance Embedded Architectures & Compilers, Pisa, Italy.

2009 General Chair of the 8th International Symposium on Parallel and Distributed Computing (ISPDC), Lisboa, Portugal.

2009 Program Chair of the International Workshop on Algorithms, Models and Tools for Parallel Compu-ting on Heterogeneous Networks (HeteroPar), co-located with Euro-Par, Delft, Netherlands.

2009 Program Co-Chair of the 3rd HiPEAC Workshop on Reconfigurable Computing, co-located with the International Conference on High Performance Embedded Architectures & Compilers, Paphos, Cyprus.

2011- Member of the Advisory Board of the EuroPar.

2010- Member of Steering Committee of the International Workshop on Algorithms, Models and Tools for Parallel Computing on Heterogeneous Platforms (HeteroPar).

2008-2011 Member of Steering Committee of the International Symposium on Parallel and Distributed Com-puting (ISPDC).

2008 International Liaison Co-Chair of the 5th International Conference on Ubiquitous Intelligence and Computing, Oslo, Norway.

7.3

Program Committee Membership

I have served on more than 60 Program and Technical Committees of Conferences and Workshops, some of the most relevant are listed below.

• IEEE IPDPS (International Parallel and Distributed Processing Symposium): 2014, 2013, 2012, 2010, 2007, 2003.

• IEEE International Conference on Computer Design (ICCD): 2014, 2013, 2012, 2011, 2010.

• IEEE/ACM International Conference on High Performance Computing (HiPC): 2014, 2012, 2011, 2010.

• ACM International Conference on Computing Frontiers: 2015, 2014, 2011

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