A reordered first fit algorithm based novel storage scheme for parallel turbo decoder

Digital Object Identifier(DOI): 10.1007/s 11741-007-0412-2

A reordered first fit algorithm based novel storage scheme for parallel turbo decoder

ZHANG Le (  ), HE Xiang ( ), XU You-yun (), LUO Han-wen () Department of Electronic Engineering, Shanghai Jiaotong University, Shanghai 200240, P. R. China

Abstract In this paper we discuss a novel storage scheme for simultaneous memory access in parallel turbo decoder. The new scheme employs vertex coloring in graph theory. Compared to a similar method that also uses unnatural order in storage, our scheme requires 25 more memory blocks but allows a simpler configuration for variable sizes of code lengths that can be implemented on-chip. Experiment shows that for a moderate to high decoding throughput (40∼100 Mbps), the hardware cost is still affordable for 3GPP’s (3rd generation partnership project) interleaver.

Keywords turbo codes, parallel turbo decoding, interleaver, vertex coloring, reordered first fit algorithm (RFFA), field programmable gate array (FPGA).

1 Introduction

During field programmable gate array (FPGA) im- plementation of turbo decoder, a substantial amount of memory is assigned to store channel information and ex- trinsic information. A decoder using parallel maximum a priori (MAP) algorithm contains multiple soft-input- soft-output (SISO) modules

, so parallel access to these storages is required. When translated into hardware de- sign, it means that data required by different SISOs at the same time must not be stored in the same RAM block. Fig.1(a) and Fig.1(b) illustrate memory access during one iteration in turbo decoding, which is concep- tually divided into 2 phases: (1) decoding against the 1st component code, and (2) decoding against the 2nd com- ponent code. During each phase, the trellis of the com- ponent code is divided into three segments, each taken care of by one SISO module. Suppose we avoid mem- ory access contention in the 1st phase by storing SISOs’

output physically in 3 different RAM blocks. However, during the 2nd phase, previously separate writing of ad- dresses from SISOs are translated by the interleaver Π.

Potentially they can end up on the same RAM, and memory access contention still exists.

Designing the interleaving pattern wisely can pre- vent such collision

and empirical results show that these contention-free interleavers can yield similar per- formance as conventional interleavers designed for serial implementation

. However, we notice that they are all constructed in a semi-random way so that at least

SISO

SISO

SISO

RAM

RAM

RAM

SISO

SISO

Collision SISO

RAM

RAM

RAM

∏

(a) Decoding the first component code

(b) Decoding the second component code Fig.1 Memory access in parallel Turbo decoder

one part of the interleaver pattern must be stored ex- plicitly, which can be inconvenient when support for dif- ferent code length is required. A solution is provided in [4], but it still requires explicit storage of the inter- leaver of the longest size. Interleavers of other lengths are then obtained by pruning this longest interleaver pattern. Other works try to solve this problem without redesigning interleaver pattern, partly because in some applications, interleaving pattern is predefined as part of the standard

. Also many excellent variable length real-time addressable interleavers exist, but they are not contention free

. In [7], an architecture was proposed which buffers memory access requests when they point to the same address. But it requires a special hard- ware structure unavailable in today’s FPGA. The idea Received Oct.25, 2005; Revised Feb.22, 2006

Project supported by the National High-Technology Research and Development Program of China (Grant No.2003AA123310), and the National Natural Science Foundation of China (Grant Nos.60332030, 60572157)

Corresponding author ZHANG Le, PhD Candidate, E-mail: [email protected]

of resolving memory access contention by storing data in an unnatural order is first introduced in [8], which proves that, in this way, P RAM blocks are adequate to support P concurrent memory access. It provides the bottom line of the memory requirement and an ‘an- neal procedure’ which computes memory storage order offline.

In this paper we follow the idea of unnatural order in storage proposed in [8] but try to make the calcula- tion of storage order simple enough so as to implement on-chip. The new storage order calculation borrows its idea from graph theory and is in essence a serial vertex coloring algorithm using greedy heuristics

. Simula- tion with 3GPP’s interleaver pattern shows the solution given by this method requires a few more memory blocks than [8], but the storage order calculation module can be implemented with simple logic, which reconfigures the decoder at the time of code length change within O(10L) clock cycles, where L is the length of informa- tion bits. We also find the major bottleneck of this un- natural order storage scheme is interconnection, in that the number of required tri-state buffers increases signifi- cantly for high throughput. However, we verify that for moderate decoding throughput (40 ∼50 Mbps), the re- quired amount of tri-state buffers is still affordable for 5 iterations and 80 ∼100 MHz system clock. For applica- tion in WCDMA system, the peak throughput can even reach 100 Mbps.

The rest of the paper is organized as follows. Section 2 models concurrent memory access as vertex coloring problem. Section 3 explains the resultant architecture of turbo decoder. Section 4 discusses the design of ver- tex coloring algorithm in the light of interconnection bottleneck. We also show how to implement this algo- rithm with hardware. Finally, to test the viability of our scheme, we implement it on a Xilinx Virtex II Pro xc2vp70 FPGA.

2 Memory access as a vertex-coloring problem

Graph coloring is first used to solve a register alloca- tion problem in compiler design

. The same principle can be borrowed to solve memory access problem in Sec- tion 1. It may be described as follows.

(1) Every stage of the trellis of the component code is modeled as a vertex. Any two vertexes are connected with an (undirected) edge if and only if data related to these two stages are accessed simultaneously by differ- ent SISO processors

in ‘parallel turbo decoding algo- rithm’.

(2) Let each color represent an RAM block. As long as any two adjacent vertexes are labeled with different colors, memory access will be collision free. This is ex- actly the ‘vertex coloring’ problem in graph theory.

(3) To use as few RAM blocks as possible, the num- ber of colors in use should be minimized.

Principles (2) and (3) should be obvious. The graph construction of principle (1) is demonstrated with an ex- ample in Fig.2, where there are 2 SISO processors, and the trellis length is 8. Assume the interleaving pattern π(x) is 5, 3, 7, 8, 1, 4, 6, 2 for x=1, 2,· · · , 8. During the 1st phase of one iteration, trellis stages requiring simul- taneous access are paired as {1, 5}, {2, 6}, {3, 7}, {4, 8 } according to Fig.2(a). During the 2nd phase, they are paired as {5,1}, {8,7}, {2,3}, {6,4}. In the following context, we call edges resulting from the 1st phase, thus drawn below the numbers, ‘low edges’, and edges from 2nd phase, thus drawn above the numbers, ‘high edges’.

1 2 3 4 5 6 7

7 6 5 4 3 2

1 8

8

SISO

(a) Before interleaving

(c) The graph

(b) After interleaving

SISO

SISO

SISO

5 8 2 6 1 7 3 4

Fig.2 Construction of the graph from interleaving pattern when 2 SISO processors are used and trellis has 8 stages

3 Hardware design

For explanation purpose, channel and extrinsic infor- mation of one trellis stage are simply called an ‘element’.

Let the number of stages in the trellis be M, the num- ber of SISO processors be P , the graph is colored with χ colors. Then access collision can be avoided by stor- ing the M elements in χ memory blocks, each with the capacity of L/P  elements, as follows:

Stage i’s data element (i = 0, · · · , M − 1) is stored in the cth RAM at position (i mod L/P ) where c is the stage’s color.

Fig.3 shows the turbo decoder’s overall architecture.

Only information bits’ extrinsic values are stored with the new scheme, while channel values of parity check bits are still stored orderly in ordinary way. Informa- tion bits’ channel values, which remain unchanged over the decoding period, are replicated twice and stored in natural and interleaved orders respectively (see Fig.8 in [3]). ‘x’ indicates the part of RAM which is occu- pied by a data element. The P tables store the c value of data elements used by the SISO. Since every SISO must support two kinds of input order, every table has a size 2 log

χ2

, which is 2 K when χ=10 and L/P =256. During the ‘learning period’

, each SISO consults their neighbor’s table, so the connections between SISO processors and tables may switch to the

‘dash-dot’ line in the figure.

SISO

Table

SISO

RAM

RAM

RAM

RAM

Config

Table

SISO

Table

SISO

Table

RAM blocks of channel values

Selection network RAM stack for information bits’

extrinsic values

x x x

x x

x x

x

x x x

x x x

x x x x

x

x

RAM blocks

[

here

Fig.3 Turbo decoder architecture ( P =4, χ=6, L=20)

Data exchange between SISO processors and RAM stack is done via a ‘selection network’, whose internals are shown in Fig.4. The switches are implemented with tri-state buffers. We define χ

as the number of output ports of the pth switch. Input is copied to the port in- dicated by control signal (drawn in dots), and all other ports are left in high-impedance state. The port width of switch

(for read) is log

L/P . The port width of switch

(for write) is log

L/P  + w, where w is word length of data. Thus the overall number of tri- state buffers can be calculated with 

p=1

(2 log

L/P +

w)χ

.

Table

Delay

Selector

RAM

, q=1,..., χ

Switch

Switch

Delay

Delay

p p

Data from

RAM blocks

To χ

RAM blocks

Read data (

Read address (p)

...

... ... ...

...

Counter Inter/

deinter

Counter Inter/

deinter

From switches

Write address (

Write data (p)

Fig.4 Selection network with concurrent read and write support

In practice we find the number of tri-state buffers can be overwhelming, which equals 1600 when L=2048, P =8, w=9, χ

≡ P . It is about 10% of all available tri-state buffers on a Xilinx xc2vp70 FPGA with 7 mil- lion gates. We also notice if the decoder’s latency is fixed, which means 2 log

L/P +w remains constant, the number of tri-state buffers increases at the speed of O(P

). This rapid increase in hardware consumption is mainly due to the ‘time varying’ nature of switches and is called ‘interconnection bottleneck’

.

Designing the coloring scheme properly can alleviate this problem. We do this by restricting the whole num- ber of colors seen by an SISO processor when it decodes

the two component codes. If χ

can be restricted, the total tri-state buffer consumption will decrease. The resultant ‘reordered first fit’ algorithm is described as follows.

Let n = L/P , and π(x) be the interleaved index of x. For simplicity, we assume P divides L. Let A

be the index of elements processed by an SISO processor, which is defined as follows:

A

= {pn + m, m = 0, 1, · · · , n − 1} ∪ {π

( pn + m), m = 0, 1, · · · , n − 1}.

For p = 0, 1, · · · , P −1, color vertices in set A

as follows.

Look at the vertex’s every adjacent vertex and record all colors (if any) already used by them. Let the smallest color not used by adjacent nodes be the vertex’s color.

The difference of our algorithm from a canonical first fit algorithm

, which may also be used here, is that the latter colors vertices orderly from index 0 to L−1. Here we color vertices in set A

first, and then color vertices in set A

, and so on. Every vertex is colored twice. This, in theory, will not increase coloring latency significantly if some additional complexity is introduced to jump over colored vertices.

Reordered first fit algorithm and its canonical version are compared in the sense of number of tri-state buffers and χ in Fig.5, in which L/P is kept constant at 256 and P is increased from 4 to 16. The number of tri-state buffers is calculated as 

p=1

(2 log

L/P  + w)χ

with w=9, L/P =256. We also provide estimated number of tri-state buffers of [8] whose results imply χ

≡ P . According to Fig.5(a), the reordered first fit algorithm saves 12% ∼20% tri-state buffers compared to canonical first fit algorithm. It uses even fewer tri-state buffers than [8] for P =16. According to Fig.5(b), the coloring scheme uses 2 ∼5 more RAM blocks than [8]. In practice, this additional cost can be alleviated by implementing the last RAM block with slices as it usually hosts less than 16 elements.

Reordered first fit algorithm makes the connection network ‘irregular’, in that χ

is different from each other. When different code lengths are supported, we are concerned if connections saved under one code length are unlikely to reappear under another code length. This is ensured by the following 2 observations: (1) color in- dices are assigned to A

sequentially, that is, if color index i appears in A

, all colors with index smaller than i must appear in A

as well; (2) χ

generally increases monotonically with p because of the greedy nature of our algorithm. This is verified in Fig.6. Here the χ

for each p is its maximum value over the code length listed be- low. Calculation with 

p=1

(2 log

L/P  + w)χ

shows

that 15% of tri-state buffers are saved.

Canonical first fit

Reordered first fit Ref.[4]

Reordered first fit

Canonical first fit

Ref.[4]

4 6 8 10 12 14 16

P

4 6 8 10 12 14 16

P

22 20 18 16 14 12 10 8 6 4

χ

8000 7000 6000 5000 4000 3000 2000 1000 0

Number of tri-state buf fers

(a) Tri-state buffers consumption

(b) RAM block consumption when different vertex coloring scheme is used (L/P = 256)

Fig.5 Tri-state buffers and RAM block simulation

1 2 3 4 5 6 7 8

p χ

12

11

10

9

8

7

6

5

Canonical first fit

Reordered first fit

Fig.6 Comparison of χ

of different coloring scheme when supporting code length ( L=512, 1024, 2048, 4096, P =8)

The ‘config’ module in Fig.3 computes data for the P tables when code length changes. At this time, ports of the tables are switched to the connection shown in Fig.7. Assume the configuration of one table entry takes N clock cycles. The first two cycles are used to read col-

ors of neighboring vertices from tables, one for neighbors seen from ‘high edges’, the other for neighbors connected via ‘low edges’. The ‘read’ ports are then idle during the next ( N −2) cycles. This is because calculation for a new vertex can only start after the previous result has been written back into the tables. The ‘color calculator’ picks up the color for the vertex, which is written to the table indicated by the ‘write control’ module if necessary. For simplicity we just color every vertex twice, thus com- putation for all table entries takes O(2NL) clock cycles.

Address buses addr

and addr

are calculated as follows.

for p = 1, · · · , P for k ∈ A

for t = 0, · · · , N − 1

addr

=

( k mod L/P , t = 0,

π(k) mod L/P  + 2

, otherwise, addr

=

( k/L/P , t = 0, π(k)/L/P , otherwise, end for

end for end for

Delay Delay

P

tables

Delay Write

control

Table

Table

Color calculator

Flag Flag

Addr

Addr

. . .

. . .

The flag bit Color of current vertex

Colors of neighboring vertices

Fig.7 Configuration module

We notice for reordered the first fit algorithm, both π(x) and π

( x) are required to be real-time address- able, which can be inconvenient for some interleaver de- sign. If only π

( x) or π(x) are real-time addressable, canonical first fit algorithm can be used instead.

‘Color calculator’ is shown in Fig.8. An additional

bit is added to every table entry to indicate if it has

been initialized or not. The correct value of this bit for

initialized entry is indicated by ‘flag’ signal, which flips

after every configuration round. Read-in data from ta-

ble are first validated based on this bit (the flag bit) and

then translated by the subsequent decoder into color us-

age vector (1  x for input x) if it has been initialized

or 0 if it is not. These vectors are further combined via

OR logic to reflect color usage among neighbors. ‘Select color’ module outputs k if 0 ∼ (k−1)th bits in ‘color us- age vector’ are 1 and the kth bit is 0. This is exactly the smallest color not used by adjacent vertices if the cur- rent vertex has not been assigned any color. Otherwise, the output of color selector should not be used. This is achieved by buffering the flag bits from tables and feed them to ‘write control’ module as shown in Fig.7.

Validator

Validator

Decoder

Decoder

Sample Bit OR

Bit OR

Select color Vertex color

Color usage vector Colors of

neighboring vertices Flag

Fig.8 Color calculator

4 Implementation results

To test the viability of our storage scheme, we im- plement the selection network (see Fig.4) with on-chip reconfiguration (see Figs.7 and 8) capability on a Xilinx Virtex II pro FPGA (xc2vp70, 7 million gates). The cost summary after placement and routing for our method is shown in Table 1. Code lengths of 512, 1024, 1536, and 2048 are supported and P =8. The latency of the coloring scheme is 20 L clock cycles, which is 512 µs for 80 MHz system clock and L=2048. The decoding throughput at this clock and code length is 45 Mbps for 5 iterations and the total hardware consumption is 83%. If we increase P to 10 and decrease iteration num- ber to 3, which is still applicable to most applications in WCDMA system, the peak throughput reaches as high as 100 Mbps and the hardware consumption is about 78%, of which 26% is consumed by the storage scheme.

Table 1 Hardware cost of the storage scheme with recon- figuration capacity on XC2VP70 FPGA

Number of hardware Occupied of all Occupied resources resources percentage (%)

Number of RAMB16s 19 out of 328 5 Number of SLICEs 653 out of 33088 2 Number of TBUFs 1976 out of 16544 11

5 Conclusions

We conclude that the new storage scheme is suitable for a turbo decoder with moderate to high throughput

(40 ∼50 Mbps to as high as 100 Mbps) on a Xilinx Virtex II pro FPGA. As in [8], the scheme supports arbitrary interleaving pattern, which may not be realizable with a parallel interleaver

. However, our method offers a simpler configuration algorithm convenient for ‘on-chip’

configuration, which does not require iterative adjust- ments as annealing method in [8]. Both the proposed method and that described in [8] have interconnection bottleneck. However, for 40 ∼100 Mbps throughput the hardware cost is still affordable.

References

[1] Nimbalker A, Blankenship T K, Classon B, Fuja T E, Costello D J, Jr. Contention-free interleavers [C]//Proceedings International Sympusium on Infor- mation Theory, Chicago, USA. 2004: 54.

[2] Kwak J, Lee K. Design of dividable interleavers for parallel decoding in turbo codes [J]. IEE Electronics Letters, 2002, 38(22): 1362–1364.

[3] Dobkin R, Peleg M, Ginosar R. Parallel interleaver design and VLSI architecture for low-latency MAP turbo decoders [J]. IEEE Transactions on Very Large Scale Integration (VLSI) Systems, 2005, 13(4): 427–

438.

[4] Dinoi L, Benedetto S. Variable-size interleaver de- sign for parallel turbo decoder architectures [C]//IEEE Global Telecommunications Conference GLOBECOM, Dallas, USA. 2004, 5: 3108–3112.

[5] TSGR1#6(99)927. Updated text proposal for Turbo code internal interleaver [S]. NTT DoCoMo, Nortel Networks, SAMSUNG Electronics Co., 1999.

[6] Crozier S, Guinand P. High-performance low- memory interleaver banks for turbo-codes [C]//IEEE 54th Vehicular Technology Conference, Atlantic, USA.

2001, 4: 2394-2398.

[7] Thul M J, Gilbert F, Wehn N. Optimized Con- current Interleaving Architecture for High-Throughput Turbo Decoding [C]// 9th International Conference on Electronics, Circuits and Systems, Kaiserslautern, Ger- many. 2002, 3: 1099–1102.

[8] Tarable A, Montorsi G Benedetto S. Mapping of interleaving laws to parallel turbo decoder architectures [J]. IEEE Communications Letters, 2004, 8(3): 2002–

2009.

[9] Assefaw H G, Fredrik M. Scalable parallel graph coloring algorithms [EB/OL]. [2005.10.25] http://

www.ii.uib.no/ ∼assefaw/pub/thesis/paper1.pdf.

[10] Mueller F. Register allocation by graph color- ing: a review [EB/OL]. [2005.10.25] http://moss.csc.

ncsu.edu/ ∼mueller /ftp/pub/PART/ color.ps.Z.

(Editor HONG Ou)