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CHAPTER 1: INTRODUCTION CHAPTER 1: INTRODUCTION 1.1 FAST FOURIER TRANSFORM 1.1 FAST FOURIER TRANSFORM

A Fast Fourier Transform (FFT) is an efficient algorithm to compute the Discrete A Fast Fourier Transform (FFT) is an efficient algorithm to compute the Discrete Four

Fourier ier TrTransansforform m (D(DFT) FT) and and itits s invinverserse. e. TheThere re are are manmany y disdistintinct ct FFT FFT algalgoriorithmthmss involving a wide range of mathematics, from simple complex-numer arithmetic to group involving a wide range of mathematics, from simple complex-numer arithmetic to group theory and numer theory. The fast Fourier Transform is a highly efficient procedure for  theory and numer theory. The fast Fourier Transform is a highly efficient procedure for  computing the DFT of a finite series and re!uires less numer of computations than that computing the DFT of a finite series and re!uires less numer of computations than that of direct evaluation of DFT. "t reduces the computations y ta#ing advantage of the fact of direct evaluation of DFT. "t reduces the computations y ta#ing advantage of the fact that the calculation of the coefficients of the DFT can e carried out iteratively. Due to that the calculation of the coefficients of the DFT can e carried out iteratively. Due to this, FFT computation techni!ue is used in digital spectral analysis, filter simulation, this, FFT computation techni!ue is used in digital spectral analysis, filter simulation, autocorrelation and pattern recognition.

autocorrelation and pattern recognition.

The FFT is ased on decomposition and rea#ing the transform into smaller  The FFT is ased on decomposition and rea#ing the transform into smaller  transforms and comining them to get the total transform. FFT reduces the computation transforms and comining them to get the total transform. FFT reduces the computation time re!uired to compute a discrete Fourier transform and improves the performance y a time re!uired to compute a discrete Fourier transform and improves the performance y a factor of $%% or more ov

factor of $%% or more over direct evaluation of the DFT.er direct evaluation of the DFT. A

A DFDFT T dedecocompmpososes es a a sese!u!uenence ce of of vavalulues es ininto to cocompmpononenents ts of of didiffffererenentt fre!uencies. This operation is useful in many fields ut computing it directly from the fre!uencies. This operation is useful in many fields ut computing it directly from the definition is often too slow to e practical. An FFT is a way to compute the same result definition is often too slow to e practical. An FFT is a way to compute the same result more !uic#ly& computing a DFT of

more !uic#ly& computing a DFT of N  N  points in the ovious way, using the definition, points in the ovious way, using the definition, ta#es '( 

ta#es '(  ) arithmetical operations, while an FFT can compute the same result in only ) arithmetical operations, while an FFT can compute the same result in only '(

'( N  N  log log N  N ) operations.) operations.

The difference in speed can e sustantial, especially for long data sets where The difference in speed can e sustantial, especially for long data sets where N  N  may e in the thousands or millions*in practice, the computation time can e reduced y may e in the thousands or millions*in practice, the computation time can e reduced y severa

several l orderorders of s of magnimagnitude in tude in such cases, and such cases, and the improvemthe improvement is ent is roughlroughly y proporproportionationall to

to N N +log (+log ( N  N ). This huge ). This huge improvement made many improvement made many DFT-DFT-ased algorithms practical. FFTsased algorithms practical. FFTs are of

are of great importgreat importance to ance to a a wide variety of wide variety of appliapplicatiocations, from ns, from digitdigital signal processingal signal processing and

and solvisolving ng partipartial al diffdifferenterential e!uations to ial e!uations to algorialgorithms for thms for !uic# !uic# multmultipliciplication of ation of larglargee integers.

integers.

The most well #nown FFT algori

The most well #nown FFT algorithms depend upon the thms depend upon the factofactoriatriation ofion of N  N , ut, ut there are FFT with ' (

there are FFT with ' ( N  N   l  logog  N  N ) compl) complexiexity for allty for all  N  N , , even for even for priprimeme  N  N . any FFT. any FFT algorithms only

algorithms only depend on depend on the fact the fact that that is anis an N N th primitive root of unity, and thus can eth primitive root of unity, and thus can e app

applilied ed to to anaanalologougous s trtranansfsfororms ms ovover er any any fifininite te fifieleld, d, susuch ch as as nunummerer-t-theheororeteticic transforms.

transforms.

The Fast Fourier Transform algorithm exploit the two asic properties of the The Fast Fourier Transform algorithm exploit the two asic properties of the twi

twiddlddle e facfactor tor - - the the symsymmetmetry ry proproperperty ty and and perperiodiodiciicity ty proproperperty ty whiwhich ch redreduceuces s thethe numer of complex

numer of complex multiplications re!uired to perform DFT.multiplications re!uired to perform DFT. FFT

FFT algalgoriorithmthms s are are asased ed on on the the funfundamdamentental al priprincinciple ple of of decdecompomposiosing ng thethe computation of discrete Fourier Transform of a se!uence of length  into successively computation of discrete Fourier Transform of a se!uence of length  into successively smaller discrete Fourier transforms. There are asically

smaller discrete Fourier transforms. There are asically two classes of FFT algorithms.two classes of FFT algorithms. A) Decimation "n Time (D"T) algorithm

A) Decimation "n Time (D"T) algorithm

/) Decimation "n Fre!uency (D"F) algorithm. /) Decimation "n Fre!uency (D"F) algorithm.

"n decimation-in-time, the se!uence for which we need the DFT is successively "n decimation-in-time, the se!uence for which we need the DFT is successively divided into smaller se!uences and the DFTs of these suse!uences are comined in a divided into smaller se!uences and the DFTs of these suse!uences are comined in a certain pattern to otain the re!uired DFT of the entire se!uence. "n the certain pattern to otain the re!uired DFT of the entire se!uence. "n the

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decimation-in-fre!uency approach, the decimation-in-fre!uency samples of the DFT are decomposed into smaller and fre!uency approach, the fre!uency samples of the DFT are decomposed into smaller and smaller suse!uences in a

smaller suse!uences in a similar manner.similar manner.

The numer of complex multiplication and addition operations re!uired y the The numer of complex multiplication and addition operations re!uired y the simple forms oth the Discrete Fourier Transform (DFT) and "nverse Discrete Fourier  simple forms oth the Discrete Fourier Transform (DFT) and "nverse Discrete Fourier  Transform ("DFT) is of order

Transform ("DFT) is of order N  N  as there are as there are N N data points to calculate, each of whichdata points to calculate, each of which re!uires

re!uires N N complex arithmetic operations.complex arithmetic operations.

The discrete Fourier transform (DFT) is defined y the formula& The discrete Fourier transform (DFT) is defined y the formula&

00   $ $ % % )) (( )) (( N N  nK  nK    j   j  N   N  n n e e n n  x  x  K   K   X   X  Π Π − − ∑ ∑−− = = • • = = 1here 2 is an integer ranging

1here 2 is an integer ranging from % tofrom % to N  N  3 $. 3 $. The algorithmic complexity of DFT will '(

The algorithmic complexity of DFT will '( N  N ) and hence is not a very efficient) and hence is not a very efficient method. "f we can4t do any etter than this then the DFT will not e very useful for the method. "f we can4t do any etter than this then the DFT will not e very useful for the ma5ority of practical D67 application. 8owever, there are a numer of different 4Fast ma5ority of practical D67 application. 8owever, there are a numer of different 4Fast Fourier Transform4 (FFT) algorithms that enale the calculation the Fourier transform of  Fourier Transform4 (FFT) algorithms that enale the calculation the Fourier transform of  a signal much faster than a DFT. As the name suggests, FFTs are algorithms for !uic#  a signal much faster than a DFT. As the name suggests, FFTs are algorithms for !uic#  calculation of discrete Fourier transform of a data vector. The FFT is a DFT algorithm calculation of discrete Fourier transform of a data vector. The FFT is a DFT algorithm which reduces the numer of computations needed for

which reduces the numer of computations needed for N N points from  points from '('( N 2 N 2) to '() to '( N N loglog  N 

 N ) ) whwherere e lolog g is is ththe e aasese- - lologagaririththm. m. "f "f ththe e fufuncnctition on to to e e trtranansfsforormemed d is is nonott harmonically related to the sampling fre!uenc

harmonically related to the sampling fre!uency, the response of an FFT loo#s li#e a 9sincy, the response of an FFT loo#s li#e a 9sinc function (sin

function (sin x x) +) + x. x.

The :adix- D"T algorithm rearranges the DFT of the function

The :adix- D"T algorithm rearranges the DFT of the function x xnn into two parts& into two parts& a sum over the even-numered indices

a sum over the even-numered indices nn ;  ; mm and a sum over the odd-numered indices and a sum over the odd-numered indices n

n ;  ; mm < $& < $&

'n

'ne e cacan n fafactctor or a a cocommmmon on mumultltipiplilier er ouout t of of ththe e sesecocond nd susum m in in ththee e!uation. "t is the two sums are the DFT of the even-indexed part

e!uation. "t is the two sums are the DFT of the even-indexed part x xmm and the DFT of  and the DFT of  odd-indexed part

odd-indexed part x xmm < $ < $ of the function of the function x xnn. Denote the DFT of the. Denote the DFT of the E  E ven-indexed inputsven-indexed inputs

 x

 xmm y y E  E k k  and the DFT of the and the DFT of the OOdd-indexed inputsdd-indexed inputs x xmm < $ < $ y y OOk k  and we otain& and we otain&

8owever, these smaller DFTs have a length of

8owever, these smaller DFTs have a length of N  N +, so we need compute only+, so we need compute only N  N ++ outputs& than#s to the periodicity properties of the DFT, the outputs for + = # =  from outputs& than#s to the periodicity properties of the DFT, the outputs for + = # =  from a DFT of length

a DFT of length N  N + are identic+ are identical to the al to the outputoutputs for %= s for %= # = # = +. That is,+. That is, E  E k k  < < N  N  +  +  ; ;  E  E k  and

and OOk k  << N  N + +  ;; OOk k . The phase factor exp> 3 ?. The phase factor exp> 3 ?ik ik ++  N  N @ @ callecalled a twidd a twiddle fadle factor wctor whichhich oeys the relation& exp> 3 ?

oeys the relation& exp> 3 ?ii((k k  < < N  N  + ) + + ) + N  N @ ;@ ; ee 3 ?3 ?iiexp> 3 ?exp> 3 ?ik ik  + + N  N @ ; 3 exp> 3 ?@ ; 3 exp> 3 ?ik ik  + + N  N @,@, fli

flippipping the ng the sigsign n of theof the OOk k  <<  N  N  + +  terms. Thus, the whole DFT can e calculated as terms. Thus, the whole DFT can e calculated as follows&

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fre!uency approach, the fre!uency samples of the DFT are decomposed into smaller and fre!uency approach, the fre!uency samples of the DFT are decomposed into smaller and smaller suse!uences in a

smaller suse!uences in a similar manner.similar manner.

The numer of complex multiplication and addition operations re!uired y the The numer of complex multiplication and addition operations re!uired y the simple forms oth the Discrete Fourier Transform (DFT) and "nverse Discrete Fourier  simple forms oth the Discrete Fourier Transform (DFT) and "nverse Discrete Fourier  Transform ("DFT) is of order

Transform ("DFT) is of order N  N  as there are as there are N N data points to calculate, each of whichdata points to calculate, each of which re!uires

re!uires N N complex arithmetic operations.complex arithmetic operations.

The discrete Fourier transform (DFT) is defined y the formula& The discrete Fourier transform (DFT) is defined y the formula&

00   $ $ % % )) (( )) (( N N  nK  nK    j   j  N   N  n n e e n n  x  x  K   K   X   X  Π Π − − ∑ ∑−− = = • • = = 1here 2 is an integer ranging

1here 2 is an integer ranging from % tofrom % to N  N  3 $. 3 $. The algorithmic complexity of DFT will '(

The algorithmic complexity of DFT will '( N  N ) and hence is not a very efficient) and hence is not a very efficient method. "f we can4t do any etter than this then the DFT will not e very useful for the method. "f we can4t do any etter than this then the DFT will not e very useful for the ma5ority of practical D67 application. 8owever, there are a numer of different 4Fast ma5ority of practical D67 application. 8owever, there are a numer of different 4Fast Fourier Transform4 (FFT) algorithms that enale the calculation the Fourier transform of  Fourier Transform4 (FFT) algorithms that enale the calculation the Fourier transform of  a signal much faster than a DFT. As the name suggests, FFTs are algorithms for !uic#  a signal much faster than a DFT. As the name suggests, FFTs are algorithms for !uic#  calculation of discrete Fourier transform of a data vector. The FFT is a DFT algorithm calculation of discrete Fourier transform of a data vector. The FFT is a DFT algorithm which reduces the numer of computations needed for

which reduces the numer of computations needed for N N points from  points from '('( N 2 N 2) to '() to '( N N loglog  N 

 N ) ) whwherere e lolog g is is ththe e aasese- - lologagaririththm. m. "f "f ththe e fufuncnctition on to to e e trtranansfsforormemed d is is nonott harmonically related to the sampling fre!uenc

harmonically related to the sampling fre!uency, the response of an FFT loo#s li#e a 9sincy, the response of an FFT loo#s li#e a 9sinc function (sin

function (sin x x) +) + x. x.

The :adix- D"T algorithm rearranges the DFT of the function

The :adix- D"T algorithm rearranges the DFT of the function x xnn into two parts& into two parts& a sum over the even-numered indices

a sum over the even-numered indices nn ;  ; mm and a sum over the odd-numered indices and a sum over the odd-numered indices n

n ;  ; mm < $& < $&

'n

'ne e cacan n fafactctor or a a cocommmmon on mumultltipiplilier er ouout t of of ththe e sesecocond nd susum m in in ththee e!uation. "t is the two sums are the DFT of the even-indexed part

e!uation. "t is the two sums are the DFT of the even-indexed part x xmm and the DFT of  and the DFT of  odd-indexed part

odd-indexed part x xmm < $ < $ of the function of the function x xnn. Denote the DFT of the. Denote the DFT of the E  E ven-indexed inputsven-indexed inputs

 x

 xmm y y E  E k k  and the DFT of the and the DFT of the OOdd-indexed inputsdd-indexed inputs x xmm < $ < $ y y OOk k  and we otain& and we otain&

8owever, these smaller DFTs have a length of

8owever, these smaller DFTs have a length of N  N +, so we need compute only+, so we need compute only N  N ++ outputs& than#s to the periodicity properties of the DFT, the outputs for + = # =  from outputs& than#s to the periodicity properties of the DFT, the outputs for + = # =  from a DFT of length

a DFT of length N  N + are identic+ are identical to the al to the outputoutputs for %= s for %= # = # = +. That is,+. That is, E  E k k  < < N  N  +  +  ; ;  E  E k  and

and OOk k  << N  N + +  ;; OOk k . The phase factor exp> 3 ?. The phase factor exp> 3 ?ik ik ++  N  N @ @ callecalled a twidd a twiddle fadle factor wctor whichhich oeys the relation& exp> 3 ?

oeys the relation& exp> 3 ?ii((k k  < < N  N  + ) + + ) + N  N @ ;@ ; ee 3 ?3 ?iiexp> 3 ?exp> 3 ?ik ik  + + N  N @ ; 3 exp> 3 ?@ ; 3 exp> 3 ?ik ik  + + N  N @,@, fli

flippipping the ng the sigsign n of theof the OOk k  <<  N  N  + +  terms. Thus, the whole DFT can e calculated as terms. Thus, the whole DFT can e calculated as follows&

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This result

This result, , expresexpressing the sing the DFT of DFT of lengtlengthh N  N  recursively in terms of two DFTs of  recursively in terms of two DFTs of  sie

sie N  N +, is the core of the radix- D"T fast Fourier transform. The algorithm gains its+, is the core of the radix- D"T fast Fourier transform. The algorithm gains its speed y re-using the results of intermediate computations to compute multiple DFT speed y re-using the results of intermediate computations to compute multiple DFT outputs. ote that final outputs are otained y a <+3 comination of

outputs. ote that final outputs are otained y a <+3 comination of E  E k k   and  and OOk k exp( 3exp( 3 ?

?ik ik  + + N  N ), which is simply a sie- DFT0 when this is generalied to larger radices elow,), which is simply a sie- DFT0 when this is generalied to larger radices elow, the sie- DFT is replaced y a larger DFT (which itself can e evaluated with an FFT). the sie- DFT is replaced y a larger DFT (which itself can e evaluated with an FFT).

Thi

This s proprocescess s is is an an exaexamplmple e of of the generathe general l tectechnihni!ue !ue of of divdivide and ide and concon!uer!uerss alg

algoriorithmthms. s. "n "n manmany y trtradiaditiotional nal impimplemlemententatiationsons, , howehoweverver, , the the expexpliclicit it recrecursursion ion isis avoided, and instead one

avoided, and instead one traverses the computational tree in readth-first fashion.traverses the computational tree in readth-first fashion. Fig 1.1 Decimation In Time FFT

Fig 1.1 Decimation In Time FFT

"n the D"T algorithm, the twiddle multiplication is performed efore the utterfly "n the D"T algorithm, the twiddle multiplication is performed efore the utterfly stage whereas for the D"F algorithm, the twiddle multiplication comes after the /utterfly stage whereas for the D"F algorithm, the twiddle multiplication comes after the /utterfly stage.

stage.

Fig 1.2 : Decimation In Freqenc! FFT Fig 1.2 : Decimation In Freqenc! FFT The 4:adix 4 algori

The 4:adix 4 algorithms are useful ifthms are useful if N N is a regular power of  (is a regular power of  ( N  N ;; p p). "f we). "f we assume that algorithmic complexity provides a direct measure of execution time and that assume that algorithmic complexity provides a direct measure of execution time and that the relevant logarithm ase is  then as shown in tale $.$, ratio of execution times for  the relevant logarithm ase is  then as shown in tale $.$, ratio of execution times for  the (DFT) vs. (:adix  FFT) increases tremendously with increase in .

the (DFT) vs. (:adix  FFT) increases tremendously with increase in . Th

The e teterm rm 4F4FFTFT4 4 is is acactutualally ly slsligighthtly ly amamiiguguousous, , ececauause se ththerere e arare e seseververalal commonly used 4FFT4 algorithms. There are two different :adix  algorithms, the commonly used 4FFT4 algorithms. There are two different :adix  algorithms, the so-called 4Decimation in Time4 (D"T) and 4Decimation in Fre!uency4 (D"F) algorithms. /oth called 4Decimation in Time4 (D"T) and 4Decimation in Fre!uency4 (D"F) algorithms. /oth of these rely on the recursive decomposition of an

of these rely on the recursive decomposition of an N N  point  point transform transform into into   (( N  N +) point+) point transforms.

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 umer  of 7oints,   omplex ultiplications in Direct computations,   omplex ultiplication in FFT Algorithm, (+) log  6peed improvement Factor  B $C B B.%  CB $ E. $C EC  .%  $%B % $. CB B%GC $G $. $ $CB BB C.C

Ta"#e 1.1: Com$ari%on o& E'ection Time%( DFT ) Ra*i' + 2 FFT 1.2 ,UTTERF- STRUCTURES FOR FFT

/asically FFT algorithms are developed y means of divide and con!uer method, the is depending on the decomposition of an  point DFT in to smaller DFTs. "f  is factored as  ; r $,r ,r  ..r H where r $;r ;I;r H;r, then r H ;. where r is called as :adix of  FFFt algorithm.

"f r; , then if is called as radix- FFT algorithm,. The asic DFT is of sie of . The  point DFT is decimated into  point DFT y two ways such as Decimation "n Time (D"T) and Decimation "n Fre!uency (D"F) algorithm. /oth the algorithm ta#e the advantage of periodicity and symmetry property of the twiddle factor.

 N  nK    j e nK   N  W  Π − = )

The radix- decimation-in-fre!uency FFT is an important algorithm otained y the divide and con!uers approach. The Fig. $. elow shows the first stage of the -point D"F algorithm.

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The decimation, however, causes shuffling in data. The entire process involves v ; log  N stages of decimation, where each stage involves  N + utterflies of the type shown in the Fig. $..

Fig. 1.: ,tter&#! Sc0eme.

8ere e   j N  nk  n W  Π − = )

is the Twiddle factor.

onse!uently, the computation of -point DFT via this algorithm re!uires ( N +) log N complex multiplications. For illustrative purposes, the eight-point decimation-in fre!uency algorithm is shown in the Figure elow. 1e oserve, as previously stated, that the output se!uence occurs in it-reversed order with respect to the input. Furthermore, if  we aandon the re!uirement that the computations occur in place, it is also possile to have oth the input and output in normal order. The  point Decimation "n fre!uency algorithm is shown in Fig $.E.

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CHAPTER 2: HARD3ATE DESCRIPTION -AN4UA4E 2.1 INTRODUCTION

8ardware Description Hanguage (8DH) is a language that can descrie the  ehavior and structure of electronic system, ut it is particularly suited as a language to descrie the structure and the ehavior of the digital electronic hardware design, such as A6"s and F7JAs as well as conventional circuits. 8DH can e used to descrie electronic hardware at many different levels of astraction such as Algorithm, :egister  transfer level (:TH) and Jate level. Algorithm is un synthesiale, :TH is the input to the synthesis, and Jate Hevel is the input from the synthesis. "t is often reported that a large numer of A6" designs meet their specification first time, ut fail to wor# when plunged into a system. 8DH allows this issue to e addressed in two ways, a 8DH specification can e executed in order to achieve a high level of confidence in its correctness efore commencing design and may simulate one specification for a part in the wider system context(Kg&- 7rinted ircuited /oard 6imulation). This depends upon how accurately the specialiation handles aspects such as timing and initialiation.

2.2 AD5ANTA4ES OF

HD-A design methodology that uses 8DHs has several fundamental advantages over  traditional Jate Hevel Design ethodology. The following are some of the advantages&

• 'ne can verify functionality early in the design process and immediately simulate

the design written as a 8DH description. Design simulation at this high level,  efore implementation at the Jate Hevel allows testing architectural and

designing decisions.

• F7JA synthesis provides logic synthesis and optimiation, so one can

automatically convert a L8DH description to gate level implementation in a given technology.

• 8DH descriptions provide technology independent documentation of a design and

its functionality. A 8DH description is more easily read and understood than a net-list or schematic description.

• 8DHs typically support a mixed level description where structural or net-list

constructs can e mixed with ehavioral or algorithmic descriptions. 1ith this mixed level capailities one can descrie system architectures at a high level or  gate level implementation.

2.6

5HD-L8DH is a hardware description language. "t descries the ehavior of an electronic circuit or system, from which the physical circuit or system can then e attained.

L8DH stands for L86" 8ardware Description Hanguage. L86" is itself an areviation for Lery 8igh 6peed "ntegrated ircuits, an initiative funded y Mnited 6tates Department of Defense in the $G%s that led to creation of L8DH. "ts first version was L8DH N, later upgraded to the L8DH G. L8DH was the original and first hardware description language to e standardied y "nstitute of Klectrical and Klectronics Kngineers, through the "KKK $%NC standards. An additional standard, the "KKK $$CB, was later added to introduce a multi-valued logic system.

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L8DH is intended for circuit synthesis as well as circuit simulation. 8owever, though L8DH is fully simulatale, not all constructs are synthesiale. The two main immediate applications of L8DH are in the field of 7rogrammale Hogic Devices and in the field of A6"s (Application 6pecific "ntegrated ircuits). 'nce the L8DH code has  een written, it can e used either to implement the circuit in a programmale device or 

can e sumitted to a foundry for farication of an A6" chip.

L8DH is a fairly general-purpose language, and it doesn4t re!uire a simulator on which to run the code. There are many L8DH compilers, which uild executale  inaries. "t can read and write files on the host computer, so a L8DH program can e written that generates another L8DH program to e incorporated in the design eing developed. /ecause of this general-purpose nature, it is possile to use L8DH to write a test bench that verifies the functionality of the design using files on the host computer to define stimuli, interacts with the user, and compares results with those expected.

The #ey advantage of L8DH when used for systems design is that it allows the  ehavior of the re!uired system to e descried (modeled) and verified (simulated) efore

synthesis tools translate the design into real hardware (gates and wires). The L8DH statements are inherently concurrent and the statements placed in a 7:'K66, FMT"' or 7:'KDM:K are executed se!uentially.

2. EDA Too#%

There are several KDA (Klectronic Design Automation) tool availale for circuit synthesis, implementation and simulation using L8DH. 6ome tools are offered as part of  a vendors design suite such as Alteras Ouatus "" which allows the synthesis of L8DH code onto Alteras 7HD+F7JA chips, or Pilinxs "6K suite, for Pilinxs 7HD+F7JA chips.

"6KQ WebPACK™  design software is the industryRs only F:KK, fully featured front-to- ac# F7JA design solution for Hinux, 1indows P7, and 1indows Lista. "6K WebPACK 

is the ideal downloadale solution for F7JA and 7HD design offering 8DH synthesis and simulation, implementation, device fitting, and STAJ programming. "6K WebPACK  delivers a complete, front-to-ac# design flow providing instant access to the "6K features and functionality at no cost. Pilinx has created a solution that allows convenient  productivity y providing a design solution that is always up to date with error-free

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CHAPTER 6: DESI4N OF FFT

6.1 IMP-EMENTATION OF 178POINT FFT ,-OC9S

The FFT computation is accomplished in three stages. The x(%) until x($E) variales are denoted as the input values for FFT computation and P(%) until P($E) are denoted as the outputs. The pipeline architecture of the $C point FFT is shown in Fig B.$ consisting of utterfly schemes in it. There are two operations to complete the computation in each stage.

Fig 6.1: Arc0itectre o& 17 $oint FFT.

The upward arrow will execute addition operation while downward arrow will execute sutraction operation. The sutracted value is multiplied with twiddle factor  value efore eing processed into the next stage. This operation is done concurrently and is #nown as utterfly process.

The implementation of FFT flow graph in the L8DH re!uires three stages, final computation is done and the result is sent to the variale  (%) to  ($E). K!uation in each stage is used to construct scheduling diagram.

For stage one, computation is accomplished in three cloc# cycles denoted as 6% to 6.The operation is much simpler compared with FFT. This is ecause FFT processed  oth real and imaginary value. The result from FFT is represented in real and imaginary value ecause of the multiplication of twiddle factor. Twiddle factor is a constant defined  y the numer of point used in this transform. This scheduling diagram is derived from the e!uations otain in FFT signal flow graph. The rest of the scheduling diagrams can e s#etched in the same way as shown in figure B.. Thus each stage re!uires a cloc# cycle and totally three cloc# cycles are needed. 6cheduling diagrams are a part of ehavioral modeling and 6ynthesis steps to translate the algorithmic description into :TH (register  transfer level) in L8DH design.

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6.2 DESI4N OF A 4ENERA- RADI82 FFT USIN4

5HD-As we move to higher-point FFTs, the structure for computing the FFT ecomes more complex and the need for an efficient complex multiplier to e incorporated within the utterfly structure arises. 8ence we propose an algorithm for an efficient complex multiplier that overcomes the complication of using complex numers throughout the  process.

A radix- FFT can e efficiently implemented using a utterfly processor which includes, esides the utterfly itself, an additional complex multiplier for the twiddle factors.

A radix- utterfly processor consists of a complex adder, a complex sutraction, and a complex multiplier for the twiddle factors. The complex multiplication with the twiddle factor is often implemented with four real multiplications and  add + sutract operations.

Norma# Com$#e' O$eration:

(P<5) (< 56) ; P < 56P < 5 - 6 ; P U 6 < 5 (6P < ) :eal 7art : ; P U 6

"maginary 7art " ; 6P < 

Msing the twiddle factor multiplier that has een developed, it is possile to design a utterfly processor for a radix- ooley-Tu#ey FFT. 8ence this asic structure of radix- FFT can e used as a uilding loc# to construct higher -point FFTs. This structure has een developed as an extension to provide for the computation of higher  value index FFTs.

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CHAPTER : 5HD- IMP-EMENTATION .1 DESI4N SOFT3ARE

The implementations have een carried out using the software, Pilinx "6K G.i. The hardware language used is the Lery 8igh 6peed "ntegrated ircuit 8ardware Description Hanguage (L8DH). L8DH is a widely used language for register transfer  level description of hardware. "t is used for design entry, compile and simulation of  digital systems.

.2 INTERFACE

The architectural design consist of data inputs, control unit, cloc#s and the data output. The register may e of the array of four or eight variale in the type of real. The FFT implementation in L8DH consists of three states such as start, load and run.

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CHAPTER : RESU-TS

The simulation of this whole pro5ect has een done using the Pilinx "6K of  version G.i. Pilinx "6K is a simulation tool for programming VLH6"W VA6"Ws, VF7JAWs, V7HDWs, and V6oWs. "t provides a comprehensive simulation and deug environment for complex A6" and F7JA designs. 6upport is provided for multiple languages including Lerilog, 6ystemLerilog, L8DH and 6ystem.

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CHAPTER 7: CONC-USION AND FUTURE SCOPE 7.1. CONC-USION

This pro5ect descries the efficient use of L8DH code for the implementation of  radix  ased FFT architecture and the wave form result of the various stages has een otained successfully. The accuracy in otained results has een increased with the help of efficient coding in L8DH. The accuracy in results depends upon the e!uations otained from the utterfly diagram and then on the correct drawing of scheduling diagrams ased on these e!uations.

7.2. FUTURE SCOPE

The future scopes of this pro5ect are to implement the proposed FFT architecture using Field-7rogrammale Jate Arrays (F7JAs).

The FFT (Fast Fourier Transform) processor plays a critical part in speed and  power consumption of the 'rthogonal Fre!uency Division ultiplexing ('FD)

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CHAPTER ;: 5HD- CODE To$ rt# + %!nt0<main.=0* lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0 entity synthXmain is  port (

dataXio & in stdXlogicXvector($ downto %)0 finalXop & out stdXlogicXvector($ downto %) 0 cloc#Xmain,cloc#,enl,reset,init & in stdXlogic) 0 end synthXmain 0

architecture rtl of synthXmain is

signal shft , waves & stdXlogicXvector( downto %) 0 component sutractor

 port (

a & in stdXlogicXvector ($ downto %) 0  & in stdXlogicXvector ($ downto %) 0 cloc# , rstXsu , suXen & in stdXlogic 0

aXsmaller , finXsu , numXero & out stdXlogic 0 eroXdetect & out stdXlogicXvector($ downto %) 0 su & out stdXlogicXvector ( downto %)0

change & out stdXlogic ) 0 end component 0

component swap  port (

a & in stdXlogicXvector ($ downto %) 0  & in stdXlogicXvector ($ downto %) 0 cloc# & in stdXlogic 0

rstXswap , enXswap & in stdXlogic 0 finishXswap & out stdXlogic 0

d & out stdXlogicXvector ($ downto %) 0

largeXexp & out stdXlogicXvector (N downto %) 0 c & out stdXlogicXvector ( downto % ) ) 0 end component 0

component shift  port (

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cXin & in stdXlogicXvector ( downto %) 0 shiftXout & out stdXlogicXvector ($ downto %) 0 cloc# , shiftXen , rstXshift & in stdXlogic 0

finishXout & out stdXlogic ) 0 end component 0

component controlXmain  port (

aXsmall , signXa , signX & in stdXlogic 0

signXout , addXsu , resetXall & out stdXlogic 0

enXsu , enXswap , enXshift , addpulse , normalise & out stdXlogic 0 finXsu , finXswap , finishXshift , addXfinish , endXall & in stdXlogic 0 cloc#Xmain , cloc# , reset , enl , eroXnum , change & in stdXlogic ) 0 end component 0

component summer  port (

num$ , num & in stdXlogicXvector ($ downto %) 0 exp & in stdXlogicXvector (N downto %) 0

addpulseXin , addsu , rstXsum & in stdXlogic 0 addXfinish & out stdXlogic 0

sumout & out stdXlogicXvector (  downto %) ) 0 end component 0

component normalie  port (

a ,  & in stdXlogicXvector ($ downto %) 0 num & in stdXlogicXvector ( downto %) 0 exp & in stdXlogicXvector (N downto %) 0

signit , addsu , cloc# , enXnorm , rstXnorm & in stdXlogic 0 eroXdetect & in stdXlogicXvector($ downto %) 0

exitXn & out stdXlogic 0

normalXsum & out stdXlogicXvector ($ downto %) ) 0 end component 0

component utXgen  port (

addXincr , addXclear , stagedone & in stdXlogic 0 utXutterfly & out stdXlogicXvector( downto %) ) 0 end component 0

component stageXgen  port (

addXstaged , addXclear & in stdXlogic 0

stXstage & out stdXlogicXvector($ downto %) ) 0 end component 0

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component iodXstaged is  port (

utXfly & in stdXlogicXvector( downto %) 0 stageXno & in stdXlogicXvector($ downto %) 0 addXincr , ioXmode & in stdXlogic 0

addXiod , addXstaged , addXfftd & out stdXlogic 0  utterflyXiod & out stdXlogicXvector( downto %) ) 0 end component 0

component aseindex  port (

indXutterfly & in stdXlogicXvector( downto %) 0 indXstage & in stdXlogicXvector($ downto %) 0 addXfft & in stdXlogic 0

fftaddXrd & out stdXlogicXvector( downto %) 0 c% , c$ , c , c & in stdXlogic ) 0

end component 0 component ioaddXgen  port (

ioXutterfly & in stdXlogicXvector( downto %) 0 addXiomode , addXip , addXop & in stdXlogic 0 aseXioadd & out stdXlogicXvector( downto %) ) 0 end component 0

component muxXadd  port (

a ,  & in stdXlogicXvector( downto %) 0 sel & in stdXlogic 0

! & out stdXlogicXvector( downto %) ) 0 end component 0

component ramXshift  port (

dataXin & in stdXlogicXvector( downto %) 0 cloc#Xmain & in stdXlogic 0

dataXout & out stdXlogicXvector( downto %) ) 0 end component 0

component cycles  port (

cloc#Xmain , preset , c%Xen , cyclesXclear & in stdXlogic 0 waves & out stdXlogicXvector( downto %) ) 0

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component counter  port (

c & out stdXlogicXvector( downto %) 0 disale , cloc#Xmain , reset & in stdXlogic) 0 end component 0

component multXcloc#   port (

cloc#Xmain , mult$Xc% , mult$Xiomode , multXclear & in stdXlogic 0 mult$Xaddincr & out stdXlogic ) 0

end component 0 component contXgen  port (

conXstaged , conXiod , conXfftd , conXinit & in stdXlogic 0 conXip , conXop , conXiomode , conXfft & out stdXlogic 0

conXenw , conXenor , c%Xenale , conXpreset & out stdXlogic 0 conXclear , disale & out stdXlogic 0

c% , cloc#Xmain & in stdXlogic 0

enXrom , enXromgen , resetXcounter & out stdXlogic 0 conXcl#count & in stdXlogicXvector( downto %) ) 0 end component 0

component andXgates  port (

wavesXand & in stdXlogicXvector( downto %) 0 cloc#Xmain , c%Xen & in stdXlogic 0

c%,c$,c,c & out stdXlogic 0

c%Xc$,cXc,c%Xc,c$Xc & out stdXlogic ) 0 end component 0

component rXloc#   port (

data & in stdXlogicXvector($ downto %) 0 trigger & in stdXlogic 0

rXout & out stdXlogicXvector($ downto %) ) 0 end component 0

component lXloc#   port (

dataXl & in stdXlogicXvector($ downto %) 0 triggerXl & in stdXlogic 0

lXout & out stdXlogicXvector($ downto %) ) 0 end component 0

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component levelXedge  port (

dataXedge & in stdXlogicXvector($ downto %) 0 triggerXedge & in stdXlogic 0

edgeXout & out stdXlogicXvector($ downto %) ) 0 end component 0

component mux  port (

d% , d$ & in stdXlogicXvector($ downto %) 0 muxXout & out stdXlogicXvector($ downto %) 0 choose & in stdXlogic ) 0

end component 0 component negate  port (

negXin & in stdXlogicXvector($ downto %) 0 negXen , cloc#Xmain & in stdXlogic 0

negXout & out stdXlogicXvector($ downto %) ) 0 end component 0

component multiply  port(

numXmux , numXrom & in stdXlogicXvector($ downto %) 0 cloc# & in stdXlogic 0

multXout & out stdXlogicXvector($ downto %) ) 0 end component 0

component divide  port (

dataXin & in stdXlogicXvector($ downto %) 0 dataXout & out stdXlogicXvector($ downto %) ) 0 end component 0

component romaddXgen is  port (

ioXrom,c%,c$,c,c & in stdXlogic 0

stageXrom & in stdXlogicXvector($ downto %) 0 utterflyXrom & in stdXlogicXvector( downto %) 0 romadd & out stdXlogicXvector( downto %) 0 romgenXen & in stdXlogic )0

end component 0

component regXdpram is  port (

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! & out stdXlogicXvector ($ downto %)0 cloc# , ioXmode & in stdXlogic0

we , re & in stdXlogic0

waddress& in stdXlogicXvector ( downto %)0 raddress& in stdXlogicXvector ( downto %))0 end component 0

component rom is  port (

cloc# , enXrom & in stdXlogic 0

romadd & in stdXlogicXvector( downto %) 0

romXdata & out stdXlogicXvector($ downto %) ) 0 end component 0

'7'KT printXresult is 7':T(

cloc# & " stdXlogic0 op & " stdXlogic0

finXres & 'MT stdXlogicXvector($ downto %)0 result & " stdXlogicXvector($ downto %))0 end component 0

 egin

result& printXresult port map (cloc#Xmain, op,finalXop,ramXdata )0  ut & utXgen port map (incr , clear , staged ,utterflyXiod) 0

stg & stageXgen port map (staged , clear , stage) 0

iodXstgd & iodXstaged port map(utterflyXiod,stage,incr,ioXmode,iod,staged,fftd,utterfly) 0

 ase & aseindex port map (utterfly , stage , fftXen , fftaddXrd , c% , c$ , c , c) 0 ioadd & ioaddXgen port map (utterfly , ioXmode , ip , op , ioXadd) 0

ramXshift$ & ramXshift port map (fftaddXrd , cloc#Xmain , shift$) 0 ramXshift & ramXshift port map (shift$ , cloc#Xmain , shft) 0 ramXshift & ramXshift port map (shft , cloc#Xmain , shift) 0 ramXshiftB & ramXshift port map (shift , cloc#Xmain ,shiftB) 0 ramXshiftE & ramXshift port map (shiftB , cloc#Xmain , shiftE) 0 --ramXshiftC & ramXshift port map (shiftE , cloc#Xmain , shiftC) 0 multx$ & muxXadd port map (shiftE , ioXadd , ioXmode , ramXwr) 0 multx & muxXadd port map (fftaddXrd , ioXadd , ioXmode , ramXrd) 0 cyc & cycles port map (cloc#Xmain , preset , c%Xen , cycXclear , waves) 0 gates & andXgates port

map(waves,cloc#Xmain,c%Xen,c%,c$,c,c,c%Xc$,cXc,c%Xc,c$Xc) 0 cnt & counter port map (cl#Xcount , disale , cloc#Xmain , resetXcount) 0 muxXcloc# & multXcloc# port map (cloc#Xmain , c% , ioXmode , clear , incr) 0 control & contXgen port map (staged , iod , fftd , init , ip , op , ioXmode , fftXen ,

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enw , enor , c%Xen , preset , clear , disale , c% , cloc#Xmain ,romXen,romgenXen,resetXcount,cl#Xcount) 0

regXram & regXdpram port map

(outXdata,dataXio,ramXdata,cloc#Xmain,ioXmode,enw,enor,ramXwr,ramXrd) 0 f$ & rXloc# port map (ramXdata , c% , d) 0

f & lXloc# port map (ramXdata , c$ , d) 0 f & rXloc# port map (ramXdata , c , dB) 0 fB & rXloc# port map (ramXdata , c , dE) 0 fE & rXloc# port map (d , c$Xc , dG) 0 fC & lXloc# port map (d , c%Xc , d$%) 0 fN & lXloc# port map (d$ , c , d$) 0 f & lXloc# port map (d$ , c$ , d$B) 0

fG & rXloc# port map (d$N , cloc#Xmain , d$) 0

f$% & rXloc# port map (dataXrom , cloc#Xmain , romXff) 0 mux$ & mux port map (d , d , dC , cXc) 0

mux & mux port map (dB , dE , dN , c$Xc) 0 mux & mux port map (d$ , d$B , d$E , c$Xc) 0

neg$ & negate port map (d$% , c%Xc$ ,cloc#Xmain , d$$) 0 neg & negate port map (d$E , c%Xc$ ,cloc#Xmain , d$C) 0 mult$ & multiply port map (dC , romXff , cloc#Xmain , d) 0 div & divide port map (d$ , d$G) 0

f$$ & levelXedge port map (d$G,cloc#Xmain,outXdata) 0 romXadd$ & romaddXgen port map

(ioXmode,c%,c$,c,c,stage,utterfly,romXadd,romgenXen) 0 rom$ & rom port map (cloc# ,romXen,romXadd,dataXrom) 0

 $$ & sutractor port map ( d$C , dN , cloc# , rst , ensu , aXsmall , finsu , numero , erodetect , su , change) 0

  & swap port map ( a;Yd$C , ;YdN , cloc#;Ycloc# , rstXswap;Yrst ,

enXswap;Yenswap , finishXswap;Yfinswap , d;YswapXnum , largeXexp;Yexp , c;YswapXnum$ ) 0

 B & shift port map (suXcontrol;Ysu , cXin;YswapXnum$ , shiftXout;YshiftXout , cloc#;Ycloc# , shiftXen;Yenshift,

rstXshift;Yrst , finishXout;Yfinshift ) 0

 E & controlXmain port map ( aXsmall , d$C($) , dN($) , signit , addsu , rst , ensu ,

enswap , enshift , addpulse , normalise , finsu , finswap , finshift ,finishXsum , endXall ,

cloc#Xmain , cloc# , reset , enl , numero , change ) 0

 C & summer port map ( shiftXout , swapXnum , exp , addpulse , addsu , rst , finishXsum , sumXout ) 0

 N & normalie port map (d$C , dN , sumXout , exp , signit , addsu , cloc# , normalise , rst , erodetect , endXall , d$N) 0

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a$ & sutractor port map ( dG , d$$ , cloc# , rst , ensu , aXsmall , finsu , numero , erodetect , sua , changea) 0

a & swap port map (dG ,d$$ ,cloc# ,rst ,enswap , finswap ,swapXnum , exp , swapXnum$ ) 0

aB & shift port map (sua ,swapXnum$ ,shiftXouta ,cloc# , enshift , rst , finshift ) 0 aE & controlXmain port map ( aXsmall , dG($) , d$$($) , signit , addsu , rst , ensu , enswap , enshift , addpulse , normalise , finsu , finswap , finshift ,finishXsum , endXall , cloc#Xmain , cloc# , reset , enl , numero , changea ) 0

aC & summer port map ( shiftXouta , swapXnum , exp , addpulse , addsu , rst , finishXsum , sumXout ) 0

aN & normalie port map (dG , d$$ , sumXout , exp , signit , addsu , cloc# , normalise , rst , erodetect , endXall , d$) 0

end rtl 0

Te%t"enc0 &i#e + %!nt0<te%t.=0* lirary ieee0 use ieee.stdXlogicX$$CB.all0 use ieee.stdXlogicXarith.all0 use ieee.stdXlogicXunsigned.all0 lirary wor#0 use wor#.utterXli.all0 M6K "KKK.6TDXH'J"XTKPT"'.AHH0 M6K 6TD.TKPT"'.AHH0 KT"T t "6 KD t0 A:8"TKTM:K testenchXarch 'F t "6 F"HK :K6MHT6& TKPT '7K 1:"TKX'DK "6 Zresults.txtZ0 '7'KT synthXmain 7':T (

dataXio & "n stdXlogicXvector ($ DownTo %)0 finalXop & 'ut stdXlogicXvector ($ DownTo %)0 cloc#Xmain & "n stdXlogic0

cloc# & "n stdXlogic0 enl & "n stdXlogic0 reset & "n stdXlogic0 init & "n stdXlogic )0

KD '7'KT0

6"JAH dataXio & stdXlogicXvector ($ DownTo %) &; Z%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Z0

(22)

6"JAH finalXop & stdXlogicXvector ($ DownTo %) &; Z%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Z0

6"JAH cloc#Xmain & stdXlogic &; 4%40 6"JAH cloc# & stdXlogic &; 4%40

6"JAH enl & stdXlogic &; 4%40 6"JAH reset & stdXlogic &; 4%40 6"JAH init & stdXlogic &; 4%40

constant 7K:"'DXcloc# & time &; %% ns0 constant DMTXHKXcloc# & real &; %.E0 constant 'FF6KTXcloc# & time &; $%% ns0

constant 7K:"'DXcloc#Xmain & time &; %% ns0 constant DMTXHKXcloc#Xmain & real &; %.E0 constant 'FF6KTXcloc#Xmain & time &; % ns0   /KJ" MMT & synthXmain 7':T A7 ( dataXio ;Y dataXio, finalXop ;Y finalXop, cloc#Xmain ;Y cloc#Xmain, cloc# ;Y cloc#, enl ;Y enl, reset ;Y reset, init ;Y init )0   process

variale i & integer &; % 0  egin for i in $ to $%%% loop cloc# =; 4$4 0 wait for E ns 0 cloc# =; 4%4 0 wait for E ns 0 end loop 0 end process 0  process

variale 5 & integer &; % 0  egin for 5 in $ to $%%% loop cloc#Xmain =; 4$4 0 wait for %% ns 0 cloc#Xmain =; 4%4 0 wait for %% ns 0

(23)

end loop 0 end process 0  process

file vectorXfile & text open readXmode is ZJ&[PilinxGi[pro5ects[pro5XfftX""[romXram.vhdZ 0

variale l , l & line 0

variale ! , p & integer &; % 0 variale count & integer 0

variale tXa , tX & stdXlogicXvector ($ downto %) 0 variale space & character 0

 egin

while not endfile(vectorXfile) loop --for count in $ to $C loop

! &; $ 0

readline(vectorXfile , l) 0

for p in $ to  loop -- data from :A read(l , tX(!)) 0 ! &; ! - $ 0 end loop 0 ! &; $ 0 dataXio =; tX($ downto %) 0 wait for B%% ns 0 end loop 0 wait for  ms 0 --wait for CE% ns 0 end process0 -- process to reset  process  egin reset =; 4$4 0 enl =; 4$4 0 wait for $% ns 0 reset =; 4%4 0 wait 0 end process 0  process  egin init =; 4$4 0 wait for $E ns 0 init =; 4%4 0

(24)

wait 0

end process 0

(25)

%>a$.=0* %>a$.=0* -- 6 -- 61A1A7 M"T7 M"T lirary ieee 0 lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0 use ieee.stdXlogicXunsigned.all 0 entity swap is entity swap is  port (  port ( a

a & & in in stdXlogicXvector stdXlogicXvector ($ ($ downto downto %) %) 00 

 & & in in stdXlogicXvector stdXlogicXvector ($ ($ downto downto %) %) 00 cloc#

cloc# & & in in stdXlogic stdXlogic 00 rstXswap

rstXswap , , enXswap enXswap & & in in stdXlogic stdXlogic 00 finishXswap

finishXswap & & out out stdXlogic stdXlogic 00 d

d & & out out stdXlogicXvector stdXlogicXvector ($ ($ downto downto %) %) 00 largeXexp

largeXexp & & out out stdXlogicXvector stdXlogicXvector (N (N downto downto %) %) 00 c

c & & out out stdXlogicXvector stdXlogicXvector ( ( downto downto % % ) ) ) ) 00 end swap 0 end swap 0 architecture rtl of swap is architecture rtl of swap is  egin  egin

 process (a ,  , cloc# , rstXswap , enXswap)  process (a ,  , cloc# , rstXswap , enXswap)

variale x , y & stdXlogicXvector (N downto %) 0 variale x , y & stdXlogicXvector (N downto %) 0 variale p , ! & stdXlogicXvector ( downto %) 0 variale p , ! & stdXlogicXvector ( downto %) 0  egin  egin if(rstXswap ; 4$4 ) then if(rstXswap ; 4$4 ) then c =; 4%4 \ a( downto %) \ Z%%%%%%%%%Z 0 c =; 4%4 \ a( downto %) \ Z%%%%%%%%%Z 0 finishXswap =; 4%4 0 finishXswap =; 4%4 0 elsif(rstXswap ; 4%4) then elsif(rstXswap ; 4%4) then if(enXswap ; 4$4) then if(enXswap ; 4$4) then x &; a (% downto ) 0 x &; a (% downto ) 0 y &;  (% downto ) 0 y &;  (% downto ) 0  p &; a ( downto %) 0  p &; a ( downto %) 0 ! &;

! &;  ( downto  ( downto %) 0%) 0 if (cloc# ; 4$4) then if (cloc# ; 4$4) then if (x = y) then if (x = y) then

c =; 4$4 \ a ( downto %) \ Z%%%%%%%%%Z 0 -- 4$4 for chec#ing c =; 4$4 \ a ( downto %) \ Z%%%%%%%%%Z 0 -- 4$4 for chec#ing d =; 4$4 \  ( downto %) \ Z%%%%%%%%Z 0 -- 4$4 for implicit one d =; 4$4 \  ( downto %) \ Z%%%%%%%%Z 0 -- 4$4 for implicit one largeXexp =;  (% downto ) 0 largeXexp =;  (% downto ) 0 finishXswap =; 4$4 0 finishXswap =; 4$4 0 elsif (y = x) then elsif (y = x) then c =; 4$4 \  ( downto %) \ Z%%%%%%%%%Z 0 c =; 4$4 \  ( downto %) \ Z%%%%%%%%%Z 0 d =; 4$4 \ a

d =; 4$4 \ a ( downto %) \ Z%%%%%%%( downto %) \ Z%%%%%%%%Z 0 -- 4$4 for implicit $.%Z 0 -- 4$4 for implicit $. largeXexp =; a (% downto ) 0

(26)

finishXswap =; 4$4 0 finishXswap =; 4$4 0

elsif ( (x;y) and (p = !)) then elsif ( (x;y) and (p = !)) then

c =; 4$4 \ a ( downto %) \ Z%%%%%%%%%Z 0 -- 4$4 for chec#ing c =; 4$4 \ a ( downto %) \ Z%%%%%%%%%Z 0 -- 4$4 for chec#ing d =; 4$4 \  ( downto %) \ Z%%%%%%%%Z 0 -- 4$4 for implicit one d =; 4$4 \  ( downto %) \ Z%%%%%%%%Z 0 -- 4$4 for implicit one largeXexp =;  (% downto ) 0 largeXexp =;  (% downto ) 0 finishXswap =; 4$4 0 finishXswap =; 4$4 0 else else c =; 4$4 \  ( downto %) \ Z%%%%%%%%%Z 0 c =; 4$4 \  ( downto %) \ Z%%%%%%%%%Z 0 d =; 4$4 \ a

d =; 4$4 \ a ( downto %) \ Z%%%%%%%( downto %) \ Z%%%%%%%%Z 0 -- 4$4 for implicit $.%Z 0 -- 4$4 for implicit $. largeXexp =; a (% downto ) 0 largeXexp =; a (% downto ) 0 finishXswap =; 4$4 0 finishXswap =; 4$4 0 end if 0 end if 0 end if 0 end if 0 end if 0 end if 0 end if 0 end if 0 end process0 end process0 end rtl0 end rtl0

(27)

%mmer.=0* %mmer.=0* -- 6MK:  -- 6MK:  lirary ieee 0 lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0 use ieee.stdXlogicXunsigned.all 0 entity summer is entity summer is  port (  port (

num$ , num & in stdXlogicXvector ($ downto %) 0 num$ , num & in stdXlogicXvector ($ downto %) 0 exp

exp & & in in stdXlogicXvector stdXlogicXvector (N (N downto downto %) %) 00 addpulseXin

addpulseXin , , addsu addsu , , rstXsum rstXsum & & in in stdXlogic stdXlogic 00 addXfinish

addXfinish & & out out stdXlogic stdXlogic 00 sumout

sumout & & out out stdXlogicXvector stdXlogicXvector ( (   downto downto %) %) ) ) 00 end summer 0 end summer 0 architecture rtl of summer is architecture rtl of summer is  egin  egin

 process (num$ , num , addpulseXin , rstXsum)  process (num$ , num , addpulseXin , rstXsum)

variale tempXnum$ , tempXsum ,

variale tempXnum$ , tempXsum , tempXnum , tempXsum , res & stdXlogicXvector (tempXnum , tempXsum , res & stdXlogicXvector ( downto %)0

downto %)0

variale tempXexp & stdXlogicXvector (N downto %) 0 variale tempXexp & stdXlogicXvector (N downto %) 0  egin  egin if (rstXsum ; 4%4) then if (rstXsum ; 4%4) then if (addpulseXin ; 4$4) then if (addpulseXin ; 4$4) then tempXnum$ &; 4%4 \ num$

tempXnum$ &; 4%4 \ num$ ($ downto %) 0 --% to find ($ downto %) 0 --% to find whether normalisation is re!uired.whether normalisation is re!uired. tempXnum &; 4%4 \ num

tempXnum &; 4%4 \ num ($ downto %) 0 --if re!uired 6/ will e $ ($ downto %) 0 --if re!uired 6/ will e $ after additionafter addition if (addsu ; 4$4) then

if (addsu ; 4$4) then

tempXsum &; tempXnum$ < tempXnum 0 tempXsum &; tempXnum$ < tempXnum 0 sumout =; tempXsum 0 sumout =; tempXsum 0 addXfinish =; 4$4 0 addXfinish =; 4$4 0 else else

tempXsum &; tempXnum - tempXnum$ 0 tempXsum &; tempXnum - tempXnum$ 0 --res &; tempXsum < tempXnum$ 0

--res &; tempXsum < tempXnum$ 0 sumout =; tempXsum 0 sumout =; tempXsum 0 addXfinish =; 4$4 0 addXfinish =; 4$4 0 end if 0 end if 0 end if 0 end if 0

elsif (rstXsum ; 4$4) then elsif (rstXsum ; 4$4) then addXfinish =; 4%40 addXfinish =; 4%40 end if 0 end if 0 end process 0 end process 0

(28)
(29)

%"tractor.=0* -- 6M/T:AT': M"T lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0 entity sutractor is  port (

a & in stdXlogicXvector ($ downto %) 0  & in stdXlogicXvector ($ downto %) 0 cloc# , rstXsu , suXen & in stdXlogic 0

aXsmaller , finXsu , numXero & out stdXlogic 0 eroXdetect & out stdXlogicXvector($ downto %) 0 su & out stdXlogicXvector ( downto %) 0

change & out stdXlogic ) 0 end sutractor 0

architecture rtl of sutractor is  egin

 process (a ,  , cloc# , rstXsu , suXen)

variale temp ,c , d & stdXlogicXvector (N downto %) 0 variale e , f & stdXlogicXvector ( downto %) 0  egin if (rstXsu ; 4%4) then c &; a (% downto ) 0 d &;  (% downto ) 0 e &; a ( downto %) 0 f &;  ( downto %) 0 if(suXen ; 4$4) then if (cloc# ; 4$4) then if ((c;%)) then eroXdetect =; Z%$Z 0 numXero =; 4$4 0 elsif ((d;%)) then eroXdetect =; Z$%Z 0 numXero =; 4$4 0 elsif (c = d ) then temp &; d - c 0 aXsmaller =; 4$4 0

su =; 4$4 \ temp (N downto %) 0 finXsu =; 4$4 0

(30)

eroXdetect =; Z%%Z 0 numXero =; 4%4 0 elsif (d = c) then temp &; c - d 0 aXsmaller =; 4%4 0

su =; 4$4 \ temp (N downto %) 0 finXsu =; 4$4 0

eroXdetect =; Z%%Z 0 numXero =; 4%4 0

elsif((c;d) and e = f) then aXsmaller =; 4$4 0

temp&; c-d 0

su =; 4$4 \ temp (N downto %) 0 finXsu =; 4$4 0

eroXdetect =; Z%%Z 0 numXero =; 4%4 0

elsif ((c;d) and e Y f) then aXsmaller =; 4%4 0

temp &; c-d 0

su =; 4$4 \ temp (N downto %) 0 eroXdetect =; Z%%Z 0

numXero =; 4%4 0 finXsu =; 4$4 0

elsif ((c;d) and (e ; f)) then temp &; c-d 0 aXsmaller =; 4%4 0 su =; 4$4 \ Z%%%%%%%%Z 0 finXsu =; 4$4 0 eroXdetect =; Z%%Z 0 numXero =; 4%4 0 end if 0 end if 0 end if 0 elsif(rstXsu ; 4$4) then finXsu =; 4%4 0 su =; Z%%%%%%%%%Z 0 numXero =; 4%4 0 eroXdetect =; Z%%Z 0

(31)

end if 0

end process 0

 process(a , ) -- process to identify when a new numer comes  egin

change =; transport 4$4 after $ ns 0 change =; transport 4%4 after E ns 0 end process 0 end rtl 0 %tage.=0* -- 6TAJK M/K: JKK:AT':. lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0 entity stageXgen is  port (

addXstaged , addXclear & in stdXlogic 0

stXstage & out stdXlogicXvector($ downto %) ) 0 end stageXgen 0

architecture rtl of stageXgen is  egin

 process(addXstaged , addXclear)

variale sXcount & stdXlogicXvector($ downto %) 0  egin

if (addXclear ; 4$4) then stXstage =; Z%%Z 0 sXcount &; Z%%Z 0

elsif(addXstaged4event and addXstaged; 4$4 ) then stXstage =; sXcount < $ 0

sXcount &; sXcount < $ 0 end if 0

end process 0 end rtl 0

(32)

%0i&t2.=0* -- 68"FT M"T lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXarith.all 0 use ieee.stdXlogicXunsigned.all 0 entity shift is  port (

suXcontrol & in stdXlogicXvector ( downto %) 0 cXin & in stdXlogicXvector ( downto %) 0 shiftXout & out stdXlogicXvector ($ downto %) 0 cloc# , shiftXen , rstXshift & in stdXlogic 0

finishXout & out stdXlogic ) 0 end shift 0

architecture rtl of shift is  egin

 process(cloc#)

variale suXtemp & stdXlogicXvector(N downto %) 0

variale temp , tempB & stdXlogicXvector($ downto %) 0 variale temp , t & stdXlogic 0

 egin

if(rstXshift;4%4) then if(shiftXen ; 4$4) then if(temp ; 4$4) then

if(suXcontrol() ; 4$4) then

suXtemp &; suXcontrol (N downto %) 0

temp &; 4$4 \ cXin ($ downto $) 0 --4$4 for implicit one temp &; 4%4 0 end if 0 end if 0 end if 0 end if 0 if(rstXshift;4%4) then if(shiftXen ; 4$4) then if(t ; 4$4) then if (suXcontrol() ; 4$4) then

if (convXinteger(suXtemp(N downto %)) ; %) then shiftXout =; temp 0

finishXout =; 4$4 0 t &; 4%4 0

elsif ( cloc# ; 4$4) then

temp &; 4%4 \ temp ($ downto $) 0 suXtemp &; suXtemp - Z%%%%%%%$Z 0

(33)

end if 0 end if 0 end if 0 end if 0 elsif(rstXshift;4$4) then temp &; 4$4 0 finishXout =; 4%4 0 t &; 4$4 0 end if 0 end process 0 end rtl 0

(34)

roma**<gen.=0* -- ADD:K66 JKK:AT': F': :' lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0 entity romaddXgen is  port (

ioXrom,c%,c$,c,c & in stdXlogic 0

stageXrom & in stdXlogicXvector($ downto %) 0 utterflyXrom & in stdXlogicXvector( downto %) 0 romadd & out stdXlogicXvector( downto %) 0 romgenXen & in stdXlogic )0

end romaddXgen 0 architecture rtl of romaddXgen is  egin  process(ioXrom,c%,c$,c,c,stageXrom,utterflyXrom)  egin if(romgenXen ; 4$4) then if(ioXrom ; 4%4) then  case stageXrom is  when Z%%Z ;Y  if(c%;4$4 or c;4$4) then  romadd =; Z%%%Z 0  elsif(c$;4$4 or c;4$4) then  romadd =; Z%%$Z 0  end if 0  when Z%$Z ;Y

 if(utterflyXrom;% or utterflyXrom;$) then if(c%;4$4 or c;4$4) then

romadd =; Z%%%Z 0

elsif(c$;4$4 or c;4$4) then romadd =; Z%%$Z 0

end if 0

 elsif(utterflyXrom; or utterflyXrom;) then if(c%;4$4 or c;4$4) then romadd =; Z$%%Z 0 elsif(c$;4$4 or c;4$4) then romadd =; Z$%$Z 0 end if 0  end if 0

(35)

 when Z$%Z ;Y if(utterflyXrom;%) then if(c%;4$4 or c;4$4) then romadd =; Z%%%Z 0 elsif(c$;4$4 or c;4$4) then romadd =; Z%%$Z 0 end if 0 elsif(utterflyXrom;$) then if(c%;4$4 or c;4$4) then romadd =; Z$%%Z 0 elsif(c$;4$4 or c;4$4) then romadd =; Z$%$Z 0 end if 0 elsif(utterflyXrom;) then if(c%;4$4 or c;4$4) then romadd =; Z%$%Z 0 elsif(c$;4$4 or c;4$4) then romadd =; Z%$$Z 0 end if 0

elsif (utterflyXrom;) then if(c%;4$4 or c;4$4) then romadd =; Z$$%Z 0 elsif(c$;4$4 or c;4$4) then romadd =; Z$$$Z 0 end if 0 end if 0  when others ;Y romadd =; Z%%%Z 0  end case 0 end if 0 end if 0 end process 0 end rtl 0

(36)

rom.=0* -- :' T' 6T':K 6"K AD '6"K LAHMK6 lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0 entity rom is  port (

cloc# , enXrom & in stdXlogic 0

romadd & in stdXlogicXvector( downto %) 0

romXdata & out stdXlogicXvector($ downto %) ) 0 end rom 0 architecture rtl of rom is  egin  process(cloc#,enXrom)  egin if(enXrom ; 4$4) then if(cloc# ; 4$4) then case romadd is  when Z%%%Z ;Y  romXdata =; Z%%$$$$$$$%%%%%%%%%%%%%%%%%%%%%%%Z 0  when Z%%$Z ;Y  romXdata =; Z%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Z 0  when Z%$%Z ;Y  romXdata =; Z%%$$$$$$%%$$%$%$%%%%%$%%$%%%%%%$Z 0  when Z%$$Z ;Y  romXdata =; Z%%$$$$$$%%$$%$%$%%%%%$%%$%%%%%%$Z 0  when Z$%%Z ;Y  romXdata =; Z%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Z 0  when Z$%$Z ;Y  romXdata =; Z%%$$$$$$$%%%%%%%%%%%%%%%%%%%%%%%Z 0  when Z$$%Z ;Y  romXdata =; Z$%$$$$$$%%$$%$%$%%%%%$%%$%%%%%%$Z 0  when Z$$$Z ;Y  romXdata =; Z%%$$$$$$%%$$%$%$%%%%%$%%$%%%%%%$Z 0  when others ;Y romXdata =; Z%$%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%Z 0 end case 0 end if 0 end if 0 end process 0 end rtl 0

(37)

r"#oc?.=0* -- KJAT"LK KDJK T:"JJK:KD FH"7 FH'76 lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0 entity rXloc# is  port (

data & in stdXlogicXvector($ downto %) 0 trigger & in stdXlogic 0

rXout & out stdXlogicXvector($ downto %) ) 0 end rXloc# 0

architecture rtl of rXloc# is  egin

 process(data , trigger)  egin

if (trigger;4%4 and trigger4event) then rXout =; data($ downto %) 0

end if 0

end process 0 end rtl 0

(38)

ram<%0i&t.=0*

-- 7A:AHHK " 7A:AHHKH 'MT 68"FTK: " T8K ADD:K66 JKK:AT"' M"T.

-- :KOM":KD /KAM6K FFT "6 '7MTKD ' DATA AD 1:"TTK /A2 "T' T8K 6AK

-- H'AT"' AFTK: E HK6. 6' T8K :KAD ADD:K66 "6 68"FTKD T8:'MJ8 E HK6 -- AD J"LK A6 1:"TK ADD:K66. lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0 entity ramXshift is  port (

dataXin & in stdXlogicXvector( downto %) 0 cloc#Xmain & in stdXlogic 0

dataXout & out stdXlogicXvector( downto %) ) 0 end ramXshift 0

architecture rtl of ramXshift is  egin

 process(cloc#Xmain , dataXin)  egin

if (cloc#Xmain4event and cloc#Xmain ; 4%4) then dataXout =; dataXin( downto %) 0

end if 0

end process 0 end rtl 0

(39)

ram.=0*

-- /ehavioral description of dual-port 6:A with & -- Active 8igh write enale (1K)

-- Active 8igh read enale (:K) -- :ising cloc# edge (loc#) lirary ieee0 use ieee.stdXlogicX$$CB.all0 use "KKK.stdXlogicXarith.all0 use "KKK.stdXlogicXunsigned.all0 use wor#.utterXli.all 0 entity regXdpram is  port (

dataXfft , dataXio & in stdXlogicXvector ($ downto %)0 ! & out stdXlogicXvector ($ downto %)0

cloc# , ioXmode & in stdXlogic0 we , re & in stdXlogic0

waddress& in stdXlogicXvector ( downto %)0 raddress& in stdXlogicXvector ( downto %))0 end regXdpram0

architecture ehav of regXdpram is

type K is array (% to $E) of stdXlogicXvector($ downto %)0 signal ramTmp & K0

 egin

-- 1rite Functional 6ection  process (cloc#,waddress,we)  egin

if (cloc#;4%4) then if (we ; 4$4) then

if (ioXmode ; 4%4) then

ramTmp (convXinteger (waddress)) =; dataXfft 0 elsif (ioXmode ; 4$4) then

ramTmp (convXinteger (waddress)) =; dataXio 0 end if 0

end if 0 end if 0

end process 0

-- :ead Functional 6ection  process (cloc#,raddress,re)  egin if (cloc#;4$4) then if (re ; 4$4) then ! =; ramTmp(convXinteger (raddress)) 0 end if0

(40)

end if0

end process0 end ehav0

$rint.=0*

-- M6KD T' 7:"T T8K :K6MHT6 " A KAT F':AT. 'T 6T8K6"6A/HK. -- M6KD 'H F': 6"MHAT"' 7M:7'6K. lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use std.textio.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXtextio.all 0 use ieee.stdXlogicXunsigned.all 0 use "KKK.mathXreal.all0 use "KKK.stdXlogicXarith.all0 use wor#.txtXutil.all0 entity printXresult is

 port (cloc#,op & in stdXlogic 0

finXres & 'MT stdXlogicXvector($ downto %)0

result & in stdXlogicXvector($ downto %))0 end printXresult 0

architecture rtl of printXresult is

file vectorwXfile & text open writeXmode is ZJ&[PilinxGi[pro5ects[pro5XfftX""[result.txtZ 0  egin

 process(op,cloc#) variale l , l & line 0

variale ! , p & integer &; % 0 variale count & integer &; $ 0  egin

if (op ; 4$4) then if (count = $N) then

if(cloc#;4%4 and cloc#4event) then ! &; $ 0

count &; count < $ 0

for p in $ to  loop -- data from :A --write(l , result(p)) 0 ! &; ! - $ 0 end loop 0 ! &; $ 0 --writeline(vectorwXfile , l) 0 end if 0 end if 0

(41)

end if 0

end process 0 end rtl 0

(42)

ot<re%#t.=0* -- 'MT7MT :K6MHT6. 6T8K6"6A/HK lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use ieee.stdXlogicXarith.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXunsigned.all 0 entity printXresult is 7':T(

cloc# & " stdXlogic0 op & " stdXlogic0

finXres & 'MT stdXlogicXvector($ downto %)0 result & " stdXlogicXvector($ downto %))0 end printXresult 0

architecture rtl of printXresult is  egin

 process(op,cloc#)

variale count & integer &; $ 0  egin

if (op ; 4$4) then if (count = $N) then

if(cloc#;4%4 and cloc#4event) then finXres =; result 0

count &; count < $ 0 end if 0

end if 0 end if 0

end process 0 end rtl 0

(43)

norma#i@e.=0* lirary ieee 0 use ieee.stdXlogicX$$CB.all 0 use wor#.utterXli.all 0 use ieee.stdXlogicXarith.all 0 use std.textio.all 0 use ieee.stdXlogicXtextio.all 0 use ieee.stdXlogicXunsigned.all 0 entity normalie is  port (

a ,  & in stdXlogicXvector ($ downto %) 0 num & in stdXlogicXvector ( downto %) 0 exp & in stdXlogicXvector (N downto %) 0

signit , addsu , cloc# , enXnorm , rstXnorm & in stdXlogic 0 eroXdetect & in stdXlogicXvector($ downto %) 0

exitXn & out stdXlogic 0

normalXsum & out stdXlogicXvector ($ downto %) ) 0 end normalie 0

architecture rtl of normalie is  egin

 process (cloc#)

variale numXtemp & stdXlogicXvector ($ downto %) 0 variale tempXexp & stdXlogicXvector (N downto %) 0 variale t , t & stdXlogic &; 4$4 0

 egin

if (rstXnorm ; 4%4) then if (enXnorm ; 4$4) then if (t ; 4$4) then

numXtemp &; num($ downto %) 0 tempXexp &; exp (N downto %) 0 t &; 4%40

end if 0

if (t ; 4$4) then

if (eroXdetect ; %) then  if (addsu ; 4%4) then

if (numXtemp ; %) then

normalXsum =; numXtemp($ downto %) 0 exitXn =; 4$4 0

t &; 4%4 0

elsif (numXtemp($) ; 4$4 and cloc# ; 4$4) then

normalXsum =; signit \ tempXexp(N downto %) \ numXtemp(% downto ) 0--chec#]]

(44)

t &; 4%4 0

elsif (cloc# ; 4$4) then

numXtemp &; numXtemp(% downto %) \ 4%4 0 tempXexp &; tempXexp - Z%%%%%%%$Z 0

end if 0

 elsif (addsu ; 4$4 and num() ; 4$4 and cloc# ; 4$4) then  tempXexp &; tempXexp < Z%%%%%%%$Z 0

 normalXsum =; signit \ tempXexp(N downto %) \ numXtemp($ downto G) 0  exitXn =; 4$4 0

 t &; 4%4 0

 elsif (cloc# ; 4$4) then

 normalXsum =; signit \ tempXexp(N downto %) \ numXtemp(% downto ) 0  exitXn =; 4$4 0

 t &; 4%4 0  end if0

elsif (eroXdetect ; $) then normalXsum =; 0

exitXn =; 4$4 0 t &; 4%4 0

elsif (eroXdetect ; ) then normalXsum =; a 0 exitXn =; 4$4 0 t &; 4%4 0 end if 0 end if 0 end if 0

elsif (rstXnorm ; 4$4) then exitXn =; 4%4 0 t &; 4$4 0 t &; 4$4 0 end if 0 end process 0 end rtl 0

References

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