An Improved Low Power, High Speed CMOS
Adder Design for Multiplier
Siddharth Sharma Dr. Balwinder Singh
M. Tech (VLSI Design) Principal Engineer
ACS Division, C-DAC Mohali, Punjab- 160071, India ACS Division, C-DAC Mohali, Punjab- 160071, India
Vemu Sulochana Project Engineer
ACS Division, C-DAC Mohali, Punjab- 160071, India
Abstract
An improved CMOS full adder circuit for high speed and low power applications is proposed in this paper at 90 nm technology node with supply voltage 1.2 V. The proposed designs contain implementation of sum and carry circuit separately. The adder circuit contains carry circuit with transmission gate logic, which is the power reduction logic in any digital circuitry. Transmission logic decrease transistor count of our proposed carry circuitry. The proposed design gives 53% reduction in power, 63 % reduction in delay, respectively. A 2-bit multiplier is made using the proposed adder circuit which results in very less power consuming and very fast in operation in compared to the other multiplier circuits.
Keywords: Transmission Gate, Low Power, Arithmetic Circuits, Low Leakage, Full Adder
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I. INTRODUCTION
Full Adder is crucial door in numerous number of arithmetic operation, for example, Multiplier and Adder. As these circuits firmly influence the general speed execution in current computerized incorporated circuits, their speed improvement is essential in elite applications, and common place application by and large requires adjustment between power utilization and speed. Furthermore, as number integrated circuits essentially added to general power spending plan, their energy utilization lessening turns into the primary goal to seek after in low power ICs utilized as apart of versatile electronic equipment’s. A full adder has three terminal for input and two output terminal, where the source of info are used to be summed, A and B, and convey input bits Cin, which gets from the figuring of the past digits[1]. The yields are the aftereffect of the whole operation, S and the subsequent estimation of the convey yield bit Cout. All the more particularly, the total and convey yields are given by
Sum = A(EXOR)B(EXOR)Cin Carry= AB+BCin+ACin
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ULPFA Adder
Fig. 1: ULPFA Adder
ULP Full Adder is based on ultra-low power diode and XOR gate logic. This ultra-low power diode is configure with PMOS and NMOS such that if low weak logic 0 occurs then this logic 0 restored in ULP Diode as shown in fig. there are several different adder such as hybrid full adder which use low power XNOR gate and output inverter to observe voltage step in 0 1 transition. ULPFA performance is compared with CMOS Full adder, hybrid full adder and BBL PT adder and it found ULPFA is better than other adder in comparison of speed and delay. If technology reduce in ULPFA than power and delay increase so transmission gate logic is used for further improvement.
II. PROPOSED ADDER
Proposed design is as shown in Fig.2 working of proposed design adder is same as previous adder. Only differences is that we implement carry circuit bi transmission gate logic. As is notable, the fast increment in deferral in transmission gate viper chain keeps the TG topology from being utilized as a part of long Full Adder chains, in light of the fact that the delay turns out to be unsatisfactorily high. Be that as it may, as the TG topology offers a decent speed execution and low power utilization in short Full Adder fastens it bodes well to embrace a blended topology approach, where the TG chains are hindered by the intermitted inclusion of a static door having driving ability. In given circuit we can replace carry circuit with other techniques as it was taking large number of transistor due to which power, area, PDP of overall circuit increases.
Fig. 3: Design of 2-bit multiplier using proposed full-adder
Among the Full Adder topologies without driving capability, the TG adder is the fastest and has the lowest power consumption[7].
So, here we implement carry circuit with transmission gate which gives low transistor count for implementation.
Moreover half adder circuit made in sum circuit can be used in XOR operation in carry circuit, which further reduces transistor size.
Also fig.3 shows design of 2-bit multiplier using proposed full-adder.
III. SIMULATION RESULTS AND WAVEFORM
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Simulation were performed using Tanner EDA tool using 90nm TSMC technology file. Fig.4 and Fig. 5 shows simulation result for previous design and proposed design respectively. Obtained results are plotted in table and compare design with previous work. We find out separate delay for sum as well as carry circuit also static power is calculated for separate input all 1 and 0.
Table – 1
Comparison table for adder design
PARAMETERS BASE DESIGNS MODIFIED DESIGNS
POWER (uW) 1.8317 0.9737
DELAY SUM (ps) 36.271 60.922
DELAY CARRY(ps) 92.638 21.207
PDP SUM (aj) 66.437 59.32
PDP CARRY (aJ) 169.68 20.65
STATIC 0 POWER (nW) 23.606 20.926
STATIC 1 POWER (nW) 33.255 33.362
STATIC POWER (nW) 27.9305 27.144
The above table shows the comparison between the previous conventional adder and the proposed modified full adder. And the improvement is quite evident.
Fig. 5: Simulation results of proposed full-adder IV. CONCLUSION
As we are moving towards low power high speed device technology due to shrink in technology size it is very important to be device consume less power and high speed. A low power high speed adder is proposed in this paper. Here due to transmission gate we obtain large reduction in power delay and PDP. Proposed adder is used for application of making high speed multiplier which consume less power.
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