N Bit Asynchronous Binary Search Analog to Digital Converter Using N Comparator

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International Journal of Emerging Technology and Advanced Engineering

Website: www.ijetae.com (ISSN 2250-2459,ISO 9001:2008 Certified Journal, Volume 2, Issue 12, December 2012)

593

N Bit Asynchronous Binary Search Analog to Digital Converter

Using N Comparator

Deepak Sati

1_{Indian institute of information technology Allahabad}

Abstract— This paper represent an asynchronous binary search ADC with reduced comparator counts. The flash ADC needs 2n-1 comparator to for N bit ADC converter. An original binary search ADC requires 2n-1 comparators and modified binary search ADC requires 2n-1 comparators while the ADC proposed in the paper only needs N comparators.

The purposed ADC is a balance between flash ADC and successive approximation register ADC in term of power and speed. The purposed ADC is better than original binary search ADC and modified binary search ADC in terms of number of comparators.

Keywords— ADC, Asynchronous ADC, Binary search ADC, Modified ADC,

I. INTRODUCTION

ADC is an important part of digital communication system which converts a continuous signal into digital form. Digital communication has advantages over analog communication eg low noise, error detection, error correction, message can be stored, less sensitive to environmental effect, easy multiplexing etc. Now a days all the communications are done using digital communication. Types of ADC are

1. Flash ADC

2. Successive approximation register ADC

Binary search ADC is a balance between flash ADC and successive approximation ADC in terms of power and speed. Flash ADC is fastest ADC. N bit Flash type ADC need 2n-1 comparator, 2n-1 resister and a 2n-1 to N encoder. So flash ADC has highest power consumption.

Fig1. Block diagram of flash ADC

And the other type of ADC is Successive approximation register ADC. SAR ADC need only one comparator and SAR reference voltage generator circuit.

Fig2. SAR ADC block diagram.

There are two type of binary search ADC before proposed binary search ADC these are

1. Original binary search ADC

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International Journal of Emerging Technology and Advanced Engineering

594 Fig.3 depicts an original 3-bit asynchronous binary-search ADC. The number in the comparator represents the position of the reference level in the full scale range.

Fig3. The original asynchronous binary-search ADC

The first comparator compares the input signal with the middle reference level, 4/8. Depending on the decision of the first comparator, either Comp (6/8) or Comp (2/8) is activated. If Comp (6/8) is activated, then it will activate Comp (7/8) or Comp (5/8). The ADC repeats this procedure until the final bit is obtained. The original binary-search ADC suffers from large hardware overhead as a flash ADC due to the exponential relation between the resolution and comparator count.

An original -bit binary-search ADC requires 2n-1 comparators while the reduced comparator count binary search ADC only needs 2N-1 ones. Fig.4 shows the Reduced comparator count asynchronous binary-search ADC. The core idea of the work is based on a structural modification reduces the count of decision elements. The output signals of the first comparator are the trigger signals of the 2nd-stage comparators. Once the first comparator makes the decision, one of the 2nd-stage comparators starts the comparison. The decision of the first comparator also serves as the control signal of the reference switching network of the 3rd stage.

Fig4. An asynchronous binary-search ADC with reference range prediction

There are four possible reference levels in the 3rd stage. If the output of the first comparator shows Vin >4/8, then only 5/8 and 7/8 are the possible references since 1/8 and 3/8 are smaller than 4/8. The selected reference voltages, e.g., 5/8 and 7/8, are connected to the 3rd-stage comparators via the reference switching network. The comparison of the 2nd-stage comparator and reference voltage switching of the 3rd stage occur simultaneously. The settling time of the switched reference voltages must be shorter than the comparison time. When the comparison of the 2nd stage completes, the triggered 3rd-stage comparator begins its comparison. At this time, the reference voltages of the 3rd-stage comparators have already settled. The accuracy of comparison is guaranteed and no conversion time is wasted.

II. NBIT ASYNCHRONOUS BINARY SEARCH ANALOG TO

DIGITAL CONVERTER USING NCOMPARATOR

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International Journal of Emerging Technology and Advanced Engineering

595 Comparing to the previous one this ADC require less comparator so this is an improvement over the previous binary search ADC so this require less number of basic elements and also this will reduce the complexity and power consumption of ADC circuit.

Fig5. - proposed asynchronous binary-search ADC

Detailed working of Proposed binary search ADC is as follows with the step by step working of each separate component-

Working of comparator 1-comparator 1 will compare input voltage (vin) to the other fixed reference voltage level (Vmax/2) and generate a high or low voltage depend on the value of input voltage whether it is greater than (Vmax/2) or less than (Vmax/2).

Working of logic circuit 1- Now depending upon the value of output of comparator 1 this logic circuit will generate two reference level for a 2nd comparator.

Fig6. Logic circuit 1

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International Journal of Emerging Technology and Advanced Engineering

596 If the value at the output of comparator 1 is high then

it will generate a comparison reference level Vmax

and if the value at the output of comparator 1 is low then

it will generate a comparison reference level Vmax.

When comparator 1 output is high-

The output of comparator 1 is connected to gate of MOSFET. Here MOSFET will work as a switch. For a high value of output of comparator 1, this MOSFET switch will be in ON condition and provide a short circuit path for the Vcc supply and this supply voltage will totally appear on its drain end. From the above figure, if output of comparator 1 is high, then voltage at node 3 will be equal to Vcc. Now resistance R1 and R2 will work as a potential divider circuit for voltage Vcc and proper values of R1 and R2 will give the output of logic

circuit equal to Vmax according to the following

equation.

Now this value will be taken as a reference input level for the comparator 2 in the case when output of comparator 1 is high. For the high value of comparator 1 the diode path will be inactive.

Case 2-When comparator 1 output is low

For a low value of output of comparator 1 , this MOSFET switch will be in OFF condition and work as a open circuit and no supply voltage will appear on its drain end. From the above figure, if output of comparator 1 is low, then voltage at node 3 will be equal to 0 volt. In this case the diode path will be active and for the proper values of V1 and R3, voltage at node 4 (V4) will be equal

to according to the following equation.

Now this value will be taken as a reference input level for the comparator 2 in the case when output of comparator 1 is low.

Working of comparator 2

Now comparator 2 will compare input voltage (vin) to

the other fixed reference voltage level either

(for the high value of output at comparator 1) or

(for the low value of output at comparator 1)

and generate a high or low voltage depend on the value of input voltage whether it is greater than or less than reference voltage level.

Working of logic circuit 2

Depending upon the value of output of comparator 1 and comparator 2 this logic circuit will generate four reference levels for a 3rd comparator. Logic circuit will generate different reference level.

Fig7. Logic circuit 2

For the low voltage present at output of comparator 1 and comparator 2 the output of logic circuit will generate reference voltage 1/8 Vmax for comparator 3. For the low voltage present at output of comparator 1 and high voltage present at output of comparator 2 will generate reference voltage 3/8Vmax for comparator 3. Now , for the high voltage present at output of comparator 1 and low voltage present at output of comparator 2 will generate reference voltage 5/8 Vmax for comparator 3. And, for the high voltage present at output of comparator 1 and high voltage present at output of comparator 2 the output of logic circuit will generate reference voltage 7/8 Vmax for comparator 3.

Case 1: Low voltage at the output of both comparators 1 and 2

Then both mosfet switch will be in off condition and only diode D3 will conduct and the proper value of V1 will generate 1/8Vcc at node 6 which will be one of the comparision reference level for comparator3.

Case2: Low output at comparator1 and high output at comparator2

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International Journal of Emerging Technology and Advanced Engineering

597 Mosfet switch 4 will be in on condition and diode D2 will conduct and for the proper values of Vcc and the resistance R4 will generate reference voltage level 3/8Vmax at node 6 which will be another reference input level for comparator3.

Case3: High voltage at the output of comparator1 and low voltage at output of comparator2

In this case mosfet 1 will be off condition and mosfet 2 will be in on condition.For this case only diode D3 will conduct and generate 5/8 Vmax at node 6 for the set values of Vcc.D1 and D2 will be in reverse biased condition because voltage present at node 6 will be greater than voltage present at node 8 or supply v1.

Case 4: When high voltage present at the output of both comparators

In this case both MOSFET will be in on condtion and this will provide a short circuit path from supply Vcc to node 5 and for some set values of Vcc and resistance R4 voltage at node 6 will become equal to 7/8Vmax and which will work as a refernce input for comparator 3.All three diodes will be in off condition as they will be in reverse biased mode.

Working of comparator 3

Now comparator 3 will compare input voltage (vin) to

the other fixed reference voltage level either

(for the low value of output at both comparator

1 and comparator 2) or (for the low value of

output at comparator 1 and high value of output at

comparator 2) or (for the high value of output

at comparator 1 and low value of output at comparator 2)

or (for the high value of output at comparator

1 and high value of output at comparator 2) and generate a high or low voltage depend on the value of input voltage whether it is greater than or less than reference voltage level.

REFERENCES

[1] Ying-Zu Lin, Soon-Jyh Chang, Yen-Ting Liu, Chun-Cheng Liu,

and Guan-Ying Huang, AUGUST 2010. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS—I: REGULAR PAPERS, VOL. 57, NO. 8, An Asynchronous Binary-Search ADC Architecture with a Reduced Comparator Count.

[2] Wayne C.Goeke, ―An 8 1/2 Digit Integrating Analog-to-Digital Converter with 16- Bit, 100,000-Sample-Per-Second Performance,‖ Hewlett-Packard Journal, vol. 40, no. 2, pp. 8–15, April 1989.

[3] T.W.Henry and M.P.Morgenthaler, ―Direct Flash Analog-to-Digital Converter and Method,‖ U.S.Patent 4,386,339.

[4] Ken Poulton et al., ―A 2 GS/s HBT Sample and Hold,‖

Proceedings of the 1988 GaAs IC Symposium, November 1988, pp. 199-202