Test Circuit for Vectorless Open Lead Detection of CMOS ICs

Test Circuit for Vectorless Open Lead

Detection of CMOS ICs

M.Hashizume(†)_{, M.Ichimiya}(†)_,

A.Ono(‡)_{, H.Yotsuyanagi}(†)

†:The Univ. of Tokushima, JAPAN

Outline

1. Background

2. Our targeted problems:

=open lead detection in CMOS logic circuits

3. Our supply current test method

4. Our test circuit

5. Feasibility check by experiments

6. Conclusion

Background

qIt is demanded to develop electronic equipments of small size.

(ex.)mobile phones, notebooks, PDAs

qMany logic circuits are implemented with fine-pitch ICs and a PCB of fine line layout.

qDefects occur more frequently in soldering process.

open lead solder bridging peeling-off pattern pattern short Targeted defect

Conv. Tests for Open Leads

qTest based on image processing techniques [Limitation]

Geometrically good connection can not always assure electrically good connection.

qLogical test

(ex.) boundary scan etc.

qElectrical test

Difficulty of Logical Test

q[Measured characteristic parameter]

Voltage of leads and/or interconnection lines

q[Difficulty]

Behaviors generated by open lead can not be estimated precisely and controlled.

modeling

H L _{• Which logic level?}

• When it will be propagated?

open a b VDD C1 C2 R a b • R=?,C1=?,C2=?

Electrical Tests for Open Leads

q

Measured characteristic parameter:

§ Resistance between lead and pad(Hioki)

§ Capacitance between lead to pad (Teradyne,HP)

§ DC current through protection or parasitic diode (Teradyne, Hioki) § Induced AC voltage at lead(Teradyne) § Magnetic field

q

Difficulty:

Our Test Method Proposed in ICEP’01

qTest based on supply current flowing when time-varying electric field is provided from the outside of CMOS ICs

VDD Test vector Electric Field

i

If

i

CMOS logic IC electrodes

Property Used in Our Test

qIf CMOS IC to be tested is defect-free, IDD=0

qIf Vi1<Vi<Vi2, supply current flows in CMOS ICs.

(a)Measurement Circuit (b)DC characteristics Vi Vo IDD Vth Vi2 Vi1 Vi IDD IDD Vo nMOS:off _pMOS:off Vo VDD

Principle of Open Lead Detection

Test Stimuli for Our Test Method

qtest input vector: [IEICE Trans.2003]

qtime-varying electric field:

§ |v_E(t)| depends on package configurations of targeted ICs and faulty position.

§ |v_E(t)| may be larger than 100V. IC can be destroyed.

vE(t) VDD Test vector electric field

i

Our Test Method Proposed in EBTW ’06

qTest method:

[1]Contact a test probe to the top of a targeted IC lead [2]If i_DD(t) ≥I_th, it is concluded as faulty.

qFeature: Open leads will be detected with AC signal of smaller amplitude supplied. _|v

s|>>|vTS| ≈VDD/2

(a) Test method in ICEP’01

vS(t) electrode IC#1 IC#2 iDD(t) VDD lead open electrode test probe IC#1 IC#2 lead open |v_TS|≈V_DD/2 v_TS RTS iDD(t) VDD Test Stimulus Generator CTS

Our New Approach

qOur new targeted tests: Tests in subcontract factories Detailed information required for test generation are not provided from ordering manufactures.

Test vector generation may not be able to be performed.

qSoldering process should be optimized for each kinds of circuits.

[Requirements]

§ a powerful tester

§ test vectors and/or test generation for locating open leads

New Test Method and The Test Circuit

qTest based on supply current of our test circuit

qTest process:

[1]Attach a test probe to a targeted input lead [2]Provide AC signal

[3]Measure i_DDT(t)

[4]If Eq.(1) is satisfied, an open occurs at the

targeted input lead. i_DDT(t)≥I_th (1)

(rms)Open at an output lead is detected as open at an input lead. iDD(t) VDD Measured supply current

Principle of Open Detection

qWhen an open occurs at an input lead,

§ v_INV(t) will depend on v_s(t) regardless of logic value of b

§ When V_i1<v_INV(t)<V_i2, elevated i_DD(t) will flow.

(b)i (t) waveforms (a)Test of open lead

Tests of Defect-free Circuits

qv_INV(t) depends on output voltage from IC#i-1. i_DDT(t) is almost zero.

Good Points of Our New Test Method

qHigh resolution àRobust test

qOpens will be detected by low pressure probing.

qTest vector generation is not needed.

qSimple test circuit àDevelopment of low price testers

DUT

(a)Test circuit

(b)Attachment of

Test Circuit for Detecting Opens

qPurpose: detect more than one lead simultaneously

Necessity of R

qWhen opens do not occur at targeted leads, elevated current may flow and the CUT may be destroyed.

R_T’s makes

Experimental Evaluation

qPurpose: Feasibility of our tests with our test circuit

(b)Test Probe used

(c)Setting up

1k

i

Waveforms Measured

qi_DDT(t) of about 1mA flows in the faulty circuit. The open lead is detected.

qThe elevated current appears when CK=H and CK=L. Test vector generation is not needed.

(a)Defect-free circuit (b)Defective circuit

3.5Vpp 1KHz CK 0 2 4 1.75 1 2 0 0 -0.64 iDDT(t) [mA] vs(t) [V] 0 0.5 1.0 1.5 2.0 t [ms]

( Open leads in a LSI of QFP type are detected like in SSIs. )

CK 0 2 4 1.75 1 2 0 0 -0.64 iDDT(t) [mA] vs(t) [V] 0 0.5 1.0 1.5 2.0 t [ms] V_SD(t) _V SD(t)

Test Speed

qTest speed depends on R_T.

qThe open lead is detected with v_s(t) of 200kHz and R_T of 100kO.

= Targeted leads are tested per 5µsec.

?IDD[mA] fs[kHz] 2 5 20 50 200 500 RT=10M RT=30k RT=100k RT=300k RT=1M RT=3M where ?IDD=max(i_DDT(t))

Conclusion

qA new test circuit for detecting open leads of CMOS ICs

[features]

§ Open lead detection with small AC voltage supplied

§ Simple test circuit

§ Vectorless test method

§ Robust test

qEvaluation by experiments

§ Targeted faults: an open lead in DIP ICs, LSIs of QFP package

§ Open leads are detected per 5µsec with our test circuit

qDevelopment of test probes

qExamination of test speed

Future works

Future works