ECE 448 Lecture 19. Software/Hardware Co-design Using the FPro System Part 1: Sorting Core. George Mason University

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George Mason University

Software/Hardware Co-design

Using the FPro System

Part 1: Sorting Core

ECE 448

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2

Developing a software/hardware

implementation using an FPro system

Conceptual Design:

C1. Software/hardware partitioning C2. I/O register map of the IP core

Hardware Design:

H1. Basic circuit performing the required functionality

* datapath * controller * top-level * functional verification H2. A wrapper matching the interface of an MMIO core

* design adjustments * coding * functional verification

Software Design:

S1. Software driver

* declarations (.h) * implementations (.cpp) * testing

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3

Software/Hardware Co-design

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4

Software/Hardware Co-design

time C1 C2 H1 H2 S1 S2 C1 C2 H1 H2 S1 S2 C1 C2 H1 H2 S1’ S1”

Approach 1 Approach 2 Approach 3

S2’

S2’’

Driver development

App development Part 1 & preliminary testing

Driver testing

App development Part 2 & final testing

SW/HW partitioning

Custom core – basic function

I/O Register Map

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Software/Hardware Partitioning: Lab 5

5

• Setting Size of Memory • Initializing Memory

• Display Mode

• Sorting in Software • Cycle Count Display

• Sorting in Hardware Application [main_sorting.cpp]: Custom Core [sorting_core.vhd]: Custom Driver [sorting_core.h, sorting_core.cpp]: • SortingCore class • Transfer of Data SW=>HW • Sorting in Hardware • Reading Results HW=>SW

Independent of hardware core:

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Standard Drivers to be Used

6

Driver Major Functionality Description of functions in

TimerCore Measuring Time timer_core.h GpiCore Reading positions

of switches

gpio_cores.h

DebounceCore Detecting which button was pressed

gpio_cores.h

SsegCore Writing to seven segment displays

sseg_core.h

UartCore Debugging using

messages displayed in a terminal window of your computer

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#include "chu_init.h" #include "gpio_cores.h" #include "sseg_core.h"

Beginning of

main_sorting.cpp

No need to have #include "timer_core.h" #include "uart_core.h"

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8

Developing a software/hardware

implementation using an FPro system

Conceptual Design:

C1. Software/hardware partitioning

C2. I/O register map of the IP core

Hardware Design:

H1. Basic circuit performing the required functionality

* datapath * controller * top-level * functional verification

H2. A wrapper matching the interface of an MMIO core * design adjustments * coding * functional verification

Software Design:

S1. Software driver

* declarations (.h) * implementations (.cpp) * testing

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Sorting

clk reset DataIn w DataOut w Done RAdd k WrInit s (0=initialization/readout 1=computations) Rd

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Simulation results for the sort operation (1)

Loading memory and starting sorting

clk reset

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Simulation results for the sort operation (2)

Completing sorting and reading out memory

clk reset

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Before sorting

During Sorting

_After

sorting Address

0

1

2

3

2

1

2

3

2

4

3

1

2

3

4

i=0 i=0 i=0 i=1 i=1 i=2 j=1 j=2 j=3 j=2 j=3 j=3 M_i Mj Legend: position of memory indexed by i position of memory indexed by j

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Pseudocode

wait for s=1 for i=0 to N-2 do for j=i+1 to N-1 do if M_i > M_j then Swap M_i with M_j end if end for end for Done wait for s=0 go to the beginning

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DINA DOUTA ADDRA WEA DINB ADDRB WEB DOUTB RAM 2k _{x w} Mi Mj w w k w w k

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Pseudocode

wait for s=1 // initialize internal memory for i=0 to N-2 do for j=i+1 to N-1 do if M_i > M_j then Swap M_i with M_j end if end for end for Done wait for s=0 go to the beginning

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DINA DOUTA ADDRA WEA 0 1 _s WrInit clk Wr DataIn w w

Block diagram of the Datapath

s 0 1 DINB ADDRB WEB Wr DOUTB RAM 2k _{x w} Mi Mj w w w w Addr s 0 1 RAdd k i j k k w w k

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Pseudocode

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DINA DOUTA ADDRA WEA 0 1 _s WrInit clk Wr Addr s 0 1 DataIn RAdd ld en _Li Ei clk w k k k w w i j 0 k +1

s 0 1 counter DINB ADDRB WEB Wr DOUTB RAM 2k _{x w} w Mi Mj w ld en _Lj Ej clk counter w w w k k k

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Pseudocode

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DINA DOUTA ADDRA WEA 0 1 _s WrInit clk Wr Addr s 0 1 DataIn RAdd ld en _Li Ei clk == N-2 == N-1 zi _zj w k k k w w i j 0 k +1

s 0 1 counter DINB ADDRB WEB Wr DOUTB RAM 2k _{x w} w Mi Mj w ld en _Lj Ej clk counter w w w k k k

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Pseudocode

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DINA DOUTA ADDRA WEA A>B 0 1 _s WrInit clk Wr MigtMj Addr s 0 1 DataIn RAdd ld en _Li Ei clk == N-2 == N-1 zi _zj w k k k w w A i j 0 k +1

s 0 1 counter DINB ADDRB WEB Wr DOUTB RAM 2k _{x w} B AgtB w Mi Mj w ld en _Lj Ej clk counter w w w k k k

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Pseudocode

wait for s=1 // read out results

for i=0 to N-2 do for j=i+1 to N-1 do if M_i > M_j then Swap M_i with M_j end if end for end for Done wait for s=0 go to the beginning

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DINA DOUTA ADDRA WEA A>B 0 1 _s WrInit clk Wr 1 0 MigtMj Addr s 0 1 DataIn RAdd Rd DataOut ld en _Li Ei clk == N-2 == N-1 zi _zj w k k k w w w A i j 0 k +1

s 0 1 counter DINB ADDRB WEB Wr DOUTB RAM 2k _{x w} B AgtB w Mi Mj w 0 w ld en _Lj Ej clk counter w w w k k k

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w clk DataOut w WrInit s Done Wr Li Ei Lj Ej Datapath _Controller RAddr k zi

Interface with the division into

the Datapath and Controller

DataIn Rd

MigtMj zj

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Pseudocode

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ASM

Chart

i=0 s j=i+1 Read Mi Read Mj Mi>Mj Swap Mi with Mj j=N-1 i=N-2 s Done j++ i++ reset 0 1 T F T F F T 0 1 S0 S1 S2 S4 S3

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ASM

Chart

Li s Lj MigtMj zj zi s Done Ej Ei reset 0 1 1 0 1 0 0 1 0 1 S0 S1 S2 S4 S3 Wr

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Timing Analysis

S2 S3 S2 S3 State new j new j j new Mi new Mi Mi new Mj new Mj Mj

new MigtMj new MigtMj MigtMj

new Wr new Wr Wr