Available Online at www.ijpret.com 898
INTERNATIONAL JOURNAL OF PURE AND
APPLIED RESEARCH IN ENGINEERING AND
TECHNOLOGY
A PATH FOR HORIZING YOUR INNOVATIVE WORK
LOW POWER VITERBI DECODER FOR TCM USING T-ALGORITHM
CHETAN K. SHENDURKAR1, MRS. RADHIKA R. HARNE2
1.Electronics Engineering Department, M. Tech. in Electronics System and Communication, Government College of Engineering Amravati. 2.Electronics Engineering Department, Assistant Professor, Government College of Engineering Amravati.
Accepted Date: 05/03/2015; Published Date: 01/05/2015
\
Abstract: Convolutional encoding is technique that is widely used in digital communication, for encoding the digital data at the transmitter end to improve channel encoding capability. For decoding such convolutional codes there are two distinct algorithms which is mainly deployed for decoding; Viterbi algorithm and Sequential algorithm. Sequential decoding is more preferred for the convolutional codes which has larger constraint length because for long constraint length codes it gives better throughput. Viterbi decoding is the best technique for decoding the convolutional codes but it is limited to smaller constraint lengths as for larger constraint length it shows more complexity and reduced decoding speed with high power consumption. Viterbi decoder is able to correct errors in received data caused by channel noise. It gives optimal sequence estimation more efficiently for the convolutional codes so it is widely used in many digital communication channel decoding.This paper presents an efficient Low-Power Viterbi Decoder (VD) design using Trace back (TB) method along with pre-computational algorithm. We proposed an improved architecture for viterbi decoder for efficient decoding operation by modifying architecture for the Survivor Metric Unit to reduce the memory access power during the trace back operation. This architecture reduces the complexity and power consumption by as much as 70% without effecting the decoding speed.
Keywords: Convolutional Encoder, Viterbi Decoder (VD), Constraint Length(K), Code rate(k/n), VLSI, Trellis Coded Modulation(TCM)
Corresponding Author: MR. CHETAN K. SHENDURKAR
Access Online On:
www.ijpret.com
How to Cite This Article:
Available Online at www.ijpret.com 899
INTRODUCTION
In today’s digital communication, reliability and efficiency of transmission is the most concerning issue for communication channel and to meet these requirements error detection and correction techniques play vital role. onvolutional codes are most frequently used encoding technique to correct errors in noisy channels. They have excellent error correcting capability (with error probability of 10-3) and give efficient results even over a noisy communication channel. The features like little complexity and good performance makes viterbi algorithm a preferred decoding method for convolutional codes to get maximum efficiency by overcoming transmission errors. Viterbi decoding algorithm, proposed by Viterbi (in 1967), finds the most likely state transition sequence of symbols in state diagram for given sequence of symbol. Trellis’s code modulation (TCM) is preferred over other methods in most the bandwidth efficient system. Typically TCM scheme used for high rate convolutional encoders which lead to the high complexity of VD of TCM decoder. Even for the moderate constraint length convolutional encoder, it shows significant complexity because of large number of transition in trelli.Therefore VD is most dominant module in TCM decoder if power consumption is considered. So in order to achieve reduced complexity and power dissipation; low power schemes should be adopted for VD in TCM decoder.
This paper proposes the efficient method for implementation of the low power VD. Different techniques are discussed and detail architecture of techniques which is more efficient is given in this paper.
I. LITERATURE REVIEW
Available Online at www.ijpret.com 900 –algorithm is commonly used than M- algorithm as it only searches for optimal path metric (PM) instead of using sorting process in feedback loop like M-algorithm. Though T-algorithm has been proved very efficient in reducing power consumption, searching the optimal path in feedback loop still results in reduced decoding speed. To eliminate this flaw T-algorithm has been designed by two different techniques; one is relaxed adaptive which suggest the use of estimated optical path instead of finding actual one in each cycle and other is limited search parallel state VD which mainly based on scarce state transition (SST ).It has been proven that relaxed adaptive VD causes serious degradation of bit error rate when applied to the high rate convolutional codes because of inherent drifting error between estimated optimal PM and the accurate one.SST based scheme on the other hand requires pre-decoding and re-decoding process and it is therefore not applicable for TCM decoders. In TCM algorithm to get better coding gain a soft input VD should be applied at the receiver end. But it may result in high computational overhead and increased decoding latency because of pre-coding and re-coding of TCM signal. Pre-computation algorithm is used to design add compare select unit (ACSU)[2] architecture for VDs having with T-algorithm, which significantly increases the decoding speed of VD with T-algorithm.
III. COVOLUTIONAL ENCODER AND VITERBI DECODER
A. Convolutional Encoder
Available Online at www.ijpret.com 901
Fig.1.Convolutional Encoder with K=7 and k/n =1/2
The encoder has n generator polynomials one for each adder. Input to the encoder is given to the leftmost register and output n bits are obtained by convolution of bits using generator polynomials and the remaining bits in each registers. The code rate (k/n) is defined as the ratio of the number of bits(k) in to the encoder to the number of channel symbols at output by convolutional encoder (n) in given encoder cycle.
B. Viterbi Decoder
Fig.2. Functional diagram of a viterbi decoder
A basic block diagram of VD is shown in figure 2
A. Branch Metric Unit
Available Online at www.ijpret.com 902 B. Branch Metric Calculator
The Branch Metric directly computes the Euclidean distance which also called soft decoding distance and the calculated distances are stored it in memory. The branch Metrics simply reads the branch metric calculator [6]
C. Add and compare select unit
In the ACSU design BM's are accumulated in the Path Metric Unit (PMU) to determine the decoding path in the trellis diagram. We proposed an architecture using T-algorithm which uses the Pre-computation steps. The ACSU [2] reads BM from the memory and passes it to the Threshold Generator Unit (TMU) to calculate the computation step {PMopt + T}. Comparator will then compare the path metrics and the best path will stored in memory as a decision bits. The Purge Unit (PU) calculates the new path using computation steps.
D. Threshold Generator Unit
The Threshold Generator Unit estimates the optimal precomputation steps. The methodology used for this is explained in detail in section (IV). In TGU uses pipelining structure to find pre-computation steps
E. Survivor Metric Unit (SMU)
SMU can be designed with two different architecture; register exchange (RE) and trace back (TB). For higher speed RE method is preferred and for low power scheme TB method is employed. Here we are giving more emphasis on low power so TB method is more important for this architecture. When we use conventional T-algorithm it is impossible to appoint a fixed state for output the decoded bit (RE scheme) or trace back process (TB scheme) because here no state is guaranteed to be active all the time. Usually in conventional T- algorithm, decoder uses the optimal state(PMopt) which is active for all time during decoding operation. During the process of estimating the PMopt index of the optimal state is found out which is then used for decoding the data. However in our case PMopt is calculated from the PMs of the previous state so it becomes difficult to find out the index of the optimal state.
IV. METHODOLOGY
PRE-COMPUTATION METHOD
Available Online at www.ijpret.com 903 (n) ,we have to expand PMs at the current time slot n (PMs(n)) as function of PMs(n-1). Hamming distance and Euclidean distance[3] are the two techniques by which branch metric can be calculated. Hamming distance calculation is more easy and faster but its decoding results not give the efficient results, therefore Euclidean distance method used which gives more accurate output than previous one. If Euclidean distance is used for the branch metric calculation, PM opt (n) is the minimum value of PMs (n) obtained as
PM opt (n)
= min { PM0(n), PM 1 (n),……….. PMK 2k-1(n)}
=min {min [PM 0,0(n-1) + BM 0,0(n),
PM 0,1(n-1) + BM 0,1(n),……..,
PM 0,p(n-1) + BM 0,p(n)],
min [PM 1,0(n-1) + BM 1,0(n),
PM 1,1(n-1) + BM 1,1(n),…….,
PM 1,p(n-1) + BM 1,p(n)],
min [PM 2k-1-1,0(n-1) + BM2k-1-1,0(n),
PM 2k-1-1,1(n-1) + BM2k-1-1,1(n),…….,
PM 2k-1-1,p(n-1) + BM2k-1-1,p(n)]} ……(1)
In a VD the trellis butterflies structure mostly have a symmetric structure. So by taking the advantage of such structure we grouped the states into several clusters to minimize the computational overhead caused by look ahead computation. Thus all states can be grouped into m clusters in special way such that all the states that belongs to same cluster extended by the same BMs and all clusters should have same number of states. Thus, by making this modification,(1) can be redefined as;
PMopt(n) = min { min(PMs(n-1) in cluster 1)
+ min(BMs(n) for cluster 1), min(PMs(n-1) in cluster 2)
Available Online at www.ijpret.com 904 ………
min(PMs(n-1) in cluster m)
+ min(BMs(n) for cluster m)} ………. (2)
Then by using BMU or TMU min(BMs) can be easily calculated. Min(PMs) at time n-1 in each cluster can be precalculated at the same time when ACSU is updating the new PMs for time n. As we continuously decompose PMs (n-1),PMs(n-2),……., the precomputation scheme get extended to q steps as shown in pipelining topology in Fig. 7 theorotically, where q is the any positive integer that is less than n. Thus PMopt(n) can be calculated directly from PMs(n-q) in q cycles.
V. CONCLUSION
In this paper, a low power and high speed decoding algorithms are discussed. Viterbi decoder with modified T- algorithm with precomputation algorithm is presented. Trace back method is more efficient if low power dissipation and efficient decoding of data over noisy communication channel is concerned. This architecture reduces the power consumption significantly with negligible reduction in decoding clock speed. Systematic estimation of optimal precompuation steps is discussed in this paper while analyzing precomputation algorithm. This algorithm is applicable to high rate convolutional codes only for TCM system. Modified design for ACSU and SMU is also given for decoding correct output. Compared to RE method, TB method shows lower power consumption with reliable decoding speed .With precomputation algorithm VD shows about 70% power consumption reduction with only 11% reduction in decoding speed. Various decoding algorithm and their comparison on the basis of power consumption, complexity and decoding speed is analyzed.
ACKNOWLEDGMENT
I express my sincere gratitude to Mrs. R.R. Harne, Professor, Electronics Engineering Department, Government College of Engineering, Amravati, for extending his valuable insight for completion this work.
REFERENCES
Available Online at www.ijpret.com 905 2. J. He, H. Liu, and Z. Wang, “A fast ACSU architecture for viterbi decoder using T-algorithm,” in Proc. 43rd IEEE Asilomar Conf. Signals, Syst. Comput., Nov. 2009, pp.231–235.
3. J. B. Anderson and E. Offer, “Reduced-state sequence detection with convolutional codes,” IEEE Trans. Inf. Theory, vol. 40, no. 3, pp. 965–972, May 1994.
4. C.F.Lin and J.B.Anderson, “M-algorithm decoding of channel convolutional codes” ,presented at the Princeton Conf. Info. Sci. Syst., Princeton, NJ, Mar. 1996.
5. Joshi M.V.,Gosavi S.,Jegadeesan V.,Basu A.,Jaiswal S.,Al-Assadi W.K. and smith S.C., “NCL implementation of Dual Rail 2s Complement 8×8 Booth2 Multiplier Using Static and Semi- Static Primitives,” IEEE region 5 technical Conference, April 2011,pp 59-64.
6. R. A. Abdallah and N.R.Shanbhag, “Error-resilient loe power viterbi decoder architectures,” IEEE Trans. Signal process., vol.57,no. 12, pp. 4906-4917, Dec. 2009
7. P. Subhashini , D.R. Mahesh Varma, Y. David Solomon Raju ,"Implementation Analysis Of adaptive Viterbi Decoder for High Speed Operation", IJCA ,vol.31,No.2,October 2011.
